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RTEMS
5.1
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RTEMS
5.1
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Go to the source code of this file.
Macros | |
| #define | USE_QSPI_DMA |
| #define | Size(pAt25) ((pAt25)->pDesc->size) |
| #define | PageSize(pAt25) ((pAt25)->pDesc->pageSize) |
| #define | BlockSize(pAt25) ((pAt25)->pDesc->blockSize) |
| #define | Name(pAt25) ((pAt25)->pDesc->name) |
| #define | ManId(pAt25) (((pAt25)->pDesc->jedecId) & 0xFF) |
| #define | PageNumber(pAt25) (Size(pAt25) / PageSize(pAt25)) |
| #define | BlockNumber(pAt25) (Size(pAt25) / BlockSize(pAt25)) |
| #define | PagePerBlock(pAt25) (BlockSize(pAt25) / PageSize(pAt25)) |
| #define | BlockEraseCmd(pAt25) ((pAt25)->pDesc->blockEraseCmd) |
| #define | ERROR_PROTECTED 1 |
| #define | ERROR_BUSY 2 |
| #define | ERROR_PROGRAM 3 |
| #define | ERROR_SPI 4 |
| #define | STATUS_RDYBSY (1 << 0) |
| #define | STATUS_RDYBSY_READY (0 << 0) |
| #define | STATUS_RDYBSY_BUSY (1 << 0) |
| #define | STATUS_WEL (1 << 1) |
| #define | STATUS_WEL_DISABLED (0 << 1) |
| #define | STATUS_WEL_ENABLED (1 << 1) |
| #define | STATUS_SWP (3 << 2) |
| #define | STATUS_SWP_PROTALL (3 << 2) |
| #define | STATUS_SWP_PROTSOME (1 << 2) |
| #define | STATUS_SWP_PROTNONE (0 << 2) |
| #define | STATUS_WPP (1 << 4) |
| #define | STATUS_WPP_NOTASSERTED (0 << 4) |
| #define | STATUS_WPP_ASSERTED (1 << 4) |
| #define | STATUS_EPE (1 << 5) |
| #define | STATUS_EPE_SUCCESS (0 << 5) |
| #define | STATUS_EPE_ERROR (1 << 5) |
| #define | STATUS_SPRL (1 << 7) |
| #define | STATUS_SPRL_UNLOCKED (0 << 7) |
| #define | STATUS_SPRL_LOCKED (1 << 7) |
| #define | STATUS_QUAD_ENABLE (1 << 1) |
| #define | STATUS_WRAP_ENABLE (0 << 4) |
| #define | STATUS_LATENCY_CTRL (0xF << 0) |
| #define | STATUS_WRAP_BYTE (1 << 5) |
| #define | BLOCK_PROTECT_Msk (7 << 2) |
| #define | TOP_BTM_PROTECT_Msk (1 << 5) |
| #define | SEC_PROTECT_Msk (1 << 6) |
| #define | CHIP_PROTECT_Msk (0x1F << 2) |
| #define | READ_ARRAY 0x0B |
| #define | READ_ARRAY_LF 0x03 |
| #define | READ_ARRAY_DUAL 0x3B |
| #define | READ_ARRAY_QUAD 0x6B |
| #define | READ_ARRAY_DUAL_IO 0xBB |
| #define | READ_ARRAY_QUAD_IO 0xEB |
| #define | BLOCK_ERASE_4K 0x20 |
| #define | BLOCK_ERASE_32K 0x52 |
| #define | BLOCK_ERASE_64K 0xD8 |
| #define | CHIP_ERASE_1 0x60 |
| #define | CHIP_ERASE_2 0xC7 |
| #define | BYTE_PAGE_PROGRAM 0x02 |
| #define | SEQUENTIAL_PROGRAM_1 0xAD |
| #define | SEQUENTIAL_PROGRAM_2 0xAF |
| #define | WRITE_ENABLE 0x06 |
| #define | WRITE_DISABLE 0x04 |
| #define | PROTECT_SECTOR 0x36 |
| #define | UNPROTECT_SECTOR 0x39 |
| #define | READ_SECTOR_PROT 0x3C |
| #define | READ_STATUS_1 0x05 |
| #define | READ_STATUS_2 0x35 |
| #define | READ_STATUS_3 0x33 |
| #define | WRITE_STATUS 0x01 |
| #define | READ_JEDEC_ID 0x9F |
| #define | DEEP_PDOWN 0xB9 |
| #define | RES_DEEP_PDOWN 0xAB |
| #define | SOFT_RESET_ENABLE 0x66 |
| #define | SOFT_RESET 0x99 |
| #define | WRAP_ENABLE 0x77 |
| #define | CONT_MODE_RESET 0xFF |
| #define | ATMEL_SPI_FLASH 0x1F |
| #define | ST_SPI_FLASH 0x20 |
| #define | WINBOND_SPI_FLASH 0xEF |
| #define | MACRONIX_SPI_FLASH 0xC2 |
| #define | SST_SPI_FLASH 0xBF |
Functions | |
| uint32_t | S25FL1D_ReadJedecId (void) |
| void | S25FL1D_InitFlashInterface (uint8_t Mode) |
| void | S25FL1D_SoftReset (void) |
| void | S25FL1D_ContReadModeReset (void) |
| unsigned char | S25FL1D_Unprotect (void) |
| unsigned char | S25FL1D_Protect (uint32_t StartAddr, uint32_t Size) |
| void | S25FL1D_QuadMode (uint8_t Enable) |
| void | S25FL1D_EnableWrap (uint8_t ByetAlign) |
| void | S25FL1D_SetReadLatencyControl (uint8_t Latency) |
| unsigned char | S25FL1D_EraseChip (void) |
| unsigned char | S25FL1D_EraseSector (unsigned int address) |
| unsigned char | S25FL1D_Erase64KBlock (unsigned int address) |
| unsigned char | S25FL1D_Write (uint32_t *pData, uint32_t size, uint32_t address, uint8_t Secure) |
| unsigned char | S25FL1D_Read (uint32_t *pData, uint32_t size, uint32_t address) |
| unsigned char | S25FL1D_ReadDual (uint32_t *pData, uint32_t size, uint32_t address) |
| unsigned char | S25FL1D_ReadQuad (uint32_t *pData, uint32_t size, uint32_t address) |
| unsigned char | S25FL1D_ReadDualIO (uint32_t *pData, uint32_t size, uint32_t address, uint8_t ContMode, uint8_t Secure) |
| unsigned char | S25FL1D_ReadQuadIO (uint32_t *pData, uint32_t size, uint32_t address, uint8_t ContMode, uint8_t Secure) |
Interface for the S25fl1 Serial Flash driver.
| #define ATMEL_SPI_FLASH 0x1F |
SPI Flash Manufacturer JEDEC ID
| #define BLOCK_ERASE_32K 0x52 |
Block erase command code (32K block).
| #define BLOCK_ERASE_4K 0x20 |
Block erase command code (4K block).
| #define BLOCK_ERASE_64K 0xD8 |
Block erase command code (64K block).
| #define BYTE_PAGE_PROGRAM 0x02 |
Byte/page program command code.
| #define CHIP_ERASE_1 0x60 |
Chip erase command code 1.
| #define CHIP_ERASE_2 0xC7 |
Chip erase command code 2.
| #define CONT_MODE_RESET 0xFF |
Continuous Read Mode Reset command code.
| #define DEEP_PDOWN 0xB9 |
Deep power-down command code.
| #define ERROR_BUSY 2 |
Device is busy executing a command.
| #define ERROR_PROGRAM 3 |
There was a problem while trying to program page data.
| #define ERROR_PROTECTED 1 |
Device is protected, operation cannot be carried out.
| #define ERROR_SPI 4 |
There was an SPI communication error.
| #define PROTECT_SECTOR 0x36 |
Protect sector command code.
| #define READ_ARRAY 0x0B |
Read array command code.
| #define READ_ARRAY_DUAL 0x3B |
Fast Read array command code.
| #define READ_ARRAY_DUAL_IO 0xBB |
Fast Read array command code.
| #define READ_ARRAY_LF 0x03 |
Read array (low frequency) command code.
| #define READ_ARRAY_QUAD 0x6B |
Fast Read array command code.
| #define READ_ARRAY_QUAD_IO 0xEB |
Fast Read array command code.
| #define READ_JEDEC_ID 0x9F |
Read manufacturer and device ID command code.
| #define READ_SECTOR_PROT 0x3C |
Read sector protection registers command code.
| #define READ_STATUS_1 0x05 |
Read status register command code.
| #define READ_STATUS_2 0x35 |
Read status register command code.
| #define READ_STATUS_3 0x33 |
Read status register command code.
| #define RES_DEEP_PDOWN 0xAB |
Resume from deep power-down command code.
| #define SEQUENTIAL_PROGRAM_1 0xAD |
Sequential program mode command code 1.
| #define SEQUENTIAL_PROGRAM_2 0xAF |
Sequential program mode command code 2.
| #define SOFT_RESET 0x99 |
Resume from deep power-down command code.
| #define SOFT_RESET_ENABLE 0x66 |
Resume from deep power-down command code.
| #define STATUS_EPE (1 << 5) |
Erase/program error bit.
| #define STATUS_EPE_ERROR (1 << 5) |
Erase or program error detected.
| #define STATUS_EPE_SUCCESS (0 << 5) |
Erase or program operation was successful.
| #define STATUS_LATENCY_CTRL (0xF << 0) |
Latency control bits
| #define STATUS_QUAD_ENABLE (1 << 1) |
Quad enable bit
| #define STATUS_RDYBSY (1 << 0) |
Device ready/busy status bit.
| #define STATUS_RDYBSY_BUSY (1 << 0) |
Device is busy with internal operations.
| #define STATUS_RDYBSY_READY (0 << 0) |
Device is ready.
| #define STATUS_SPRL (1 << 7) |
Sector protection registers locked bit.
| #define STATUS_SPRL_LOCKED (1 << 7) |
Sector protection registers are locked.
| #define STATUS_SPRL_UNLOCKED (0 << 7) |
Sector protection registers are unlocked.
| #define STATUS_SWP (3 << 2) |
Software protection status bit-field.
| #define STATUS_SWP_PROTALL (3 << 2) |
All sectors are software protected.
| #define STATUS_SWP_PROTNONE (0 << 2) |
No sector is software protected.
| #define STATUS_SWP_PROTSOME (1 << 2) |
Some sectors are software protected.
| #define STATUS_WEL (1 << 1) |
Write enable latch status bit.
| #define STATUS_WEL_DISABLED (0 << 1) |
Device is not write enabled.
| #define STATUS_WEL_ENABLED (1 << 1) |
Device is write enabled.
| #define STATUS_WPP (1 << 4) |
Write protect pin status bit.
| #define STATUS_WPP_ASSERTED (1 << 4) |
Write protect signal is asserted.
| #define STATUS_WPP_NOTASSERTED (0 << 4) |
Write protect signal is not asserted.
| #define STATUS_WRAP_ENABLE (0 << 4) |
Quad enable bit
| #define UNPROTECT_SECTOR 0x39 |
Unprotected sector command code.
| #define WRAP_ENABLE 0x77 |
Resume from deep power-down command code.
| #define WRITE_DISABLE 0x04 |
Write disable command code.
| #define WRITE_ENABLE 0x06 |
Write enable command code.
| #define WRITE_STATUS 0x01 |
Write status register command code.
1.8.15