RTEMS
5.1
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Implementation of interrupt mechanisms for Time Test 27. More...
Go to the source code of this file.
Macros | |
#define | MUST_WAIT_FOR_INTERRUPT 0 |
#define | Install_tm27_vector(handler) |
#define | Cause_tm27_intr() __asm__ volatile("int $0x90" : :); |
#define | Clear_tm27_intr() /* empty */ |
#define | Lower_tm27_intr() /* empty */ |
Implementation of interrupt mechanisms for Time Test 27.