Media LB

Data Structures
struct	Mlb
	Mlb hardware registers. More...

Macros
#define	MLB_MLBC0_MLBEN   (0x1u << 0)
	(MLB_MLBC0) MediaLB Enable
#define	MLB_MLBC0_MLBCLK_Pos   2
#define	MLB_MLBC0_MLBCLK_Msk   (0x7u << MLB_MLBC0_MLBCLK_Pos)
	(MLB_MLBC0) MLBCLK (MediaLB clock) speed select
#define	MLB_MLBC0_MLBCLK(value)   ((MLB_MLBC0_MLBCLK_Msk & ((value) << MLB_MLBC0_MLBCLK_Pos)))
#define	MLB_MLBC0_MLBCLK_256_FS   (0x0u << 2)
	(MLB_MLBC0) 256xFs (for MLBPEN = 0)
#define	MLB_MLBC0_MLBCLK_512_FS   (0x1u << 2)
	(MLB_MLBC0) 512xFs (for MLBPEN = 0)
#define	MLB_MLBC0_MLBCLK_1024_FS   (0x2u << 2)
	(MLB_MLBC0) 1024xFs (for MLBPEN = 0)
#define	MLB_MLBC0_ZERO   (0x1u << 5)
	(MLB_MLBC0) Must be Written to 0
#define	MLB_MLBC0_MLBLK   (0x1u << 7)
	(MLB_MLBC0) MediaLB Lock Status (read-only)
#define	MLB_MLBC0_ASYRETRY   (0x1u << 12)
	(MLB_MLBC0) Asynchronous Tx Packet Retry
#define	MLB_MLBC0_CTLRETRY   (0x1u << 14)
	(MLB_MLBC0) Control Tx Packet Retry
#define	MLB_MLBC0_FCNT_Pos   15
#define	MLB_MLBC0_FCNT_Msk   (0x7u << MLB_MLBC0_FCNT_Pos)
	(MLB_MLBC0) The number of frames per sub-buffer for synchronous channels
#define	MLB_MLBC0_FCNT(value)   ((MLB_MLBC0_FCNT_Msk & ((value) << MLB_MLBC0_FCNT_Pos)))
#define	MLB_MLBC0_FCNT_1_FRAME   (0x0u << 15)
	(MLB_MLBC0) 1 frame per sub-buffer (Operation is the same as Standard mode.)
#define	MLB_MLBC0_FCNT_2_FRAMES   (0x1u << 15)
	(MLB_MLBC0) 2 frames per sub-buffer
#define	MLB_MLBC0_FCNT_4_FRAMES   (0x2u << 15)
	(MLB_MLBC0) 4 frames per sub-buffer
#define	MLB_MLBC0_FCNT_8_FRAMES   (0x3u << 15)
	(MLB_MLBC0) 8 frames per sub-buffer
#define	MLB_MLBC0_FCNT_16_FRAMES   (0x4u << 15)
	(MLB_MLBC0) 16 frames per sub-buffer
#define	MLB_MLBC0_FCNT_32_FRAMES   (0x5u << 15)
	(MLB_MLBC0) 32 frames per sub-buffer
#define	MLB_MLBC0_FCNT_64_FRAMES   (0x6u << 15)
	(MLB_MLBC0) 64 frames per sub-buffer
#define	MLB_MS0_MCS_Pos   0
#define	MLB_MS0_MCS_Msk   (0xffffffffu << MLB_MS0_MCS_Pos)
	(MLB_MS0) MediaLB Channel Status [31:0] (cleared by writing a 0)
#define	MLB_MS0_MCS(value)   ((MLB_MS0_MCS_Msk & ((value) << MLB_MS0_MCS_Pos)))
#define	MLB_MS1_MCS_Pos   0
#define	MLB_MS1_MCS_Msk   (0xffffffffu << MLB_MS1_MCS_Pos)
	(MLB_MS1) MediaLB Channel Status [63:32] (cleared by writing a 0)
#define	MLB_MS1_MCS(value)   ((MLB_MS1_MCS_Msk & ((value) << MLB_MS1_MCS_Pos)))
#define	MLB_MSS_RSTSYSCMD   (0x1u << 0)
	(MLB_MSS) Reset System Command Detected in the System Quadlet (cleared by writing a 0)
#define	MLB_MSS_LKSYSCMD   (0x1u << 1)
	(MLB_MSS) Network Lock System Command Detected in the System Quadlet (cleared by writing a 0)
#define	MLB_MSS_ULKSYSCMD   (0x1u << 2)
	(MLB_MSS) Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0)
#define	MLB_MSS_CSSYSCMD   (0x1u << 3)
	(MLB_MSS) Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0)
#define	MLB_MSS_SWSYSCMD   (0x1u << 4)
	(MLB_MSS) Software System Command Detected in the System Quadlet (cleared by writing a 0)
#define	MLB_MSS_SERVREQ   (0x1u << 5)
	(MLB_MSS) Service Request Enabled
#define	MLB_MSD_SD0_Pos   0
#define	MLB_MSD_SD0_Msk   (0xffu << MLB_MSD_SD0_Pos)
	(MLB_MSD) System Data (Byte 0)
#define	MLB_MSD_SD1_Pos   8
#define	MLB_MSD_SD1_Msk   (0xffu << MLB_MSD_SD1_Pos)
	(MLB_MSD) System Data (Byte 1)
#define	MLB_MSD_SD2_Pos   16
#define	MLB_MSD_SD2_Msk   (0xffu << MLB_MSD_SD2_Pos)
	(MLB_MSD) System Data (Byte 2)
#define	MLB_MSD_SD3_Pos   24
#define	MLB_MSD_SD3_Msk   (0xffu << MLB_MSD_SD3_Pos)
	(MLB_MSD) System Data (Byte 3)
#define	MLB_MIEN_ISOC_PE   (0x1u << 0)
	(MLB_MIEN) Isochronous Rx Protocol Error Enable
#define	MLB_MIEN_ISOC_BUFO   (0x1u << 1)
	(MLB_MIEN) Isochronous Rx Buffer Overflow Enable
#define	MLB_MIEN_SYNC_PE   (0x1u << 16)
	(MLB_MIEN) Synchronous Protocol Error Enable
#define	MLB_MIEN_ARX_DONE   (0x1u << 17)
	(MLB_MIEN) Asynchronous Rx Done Enable
#define	MLB_MIEN_ARX_PE   (0x1u << 18)
	(MLB_MIEN) Asynchronous Rx Protocol Error Enable
#define	MLB_MIEN_ARX_BREAK   (0x1u << 19)
	(MLB_MIEN) Asynchronous Rx Break Enable
#define	MLB_MIEN_ATX_DONE   (0x1u << 20)
	(MLB_MIEN) Asynchronous Tx Packet Done Enable
#define	MLB_MIEN_ATX_PE   (0x1u << 21)
	(MLB_MIEN) Asynchronous Tx Protocol Error Enable
#define	MLB_MIEN_ATX_BREAK   (0x1u << 22)
	(MLB_MIEN) Asynchronous Tx Break Enable
#define	MLB_MIEN_CRX_DONE   (0x1u << 24)
	(MLB_MIEN) Control Rx Packet Done Enable
#define	MLB_MIEN_CRX_PE   (0x1u << 25)
	(MLB_MIEN) Control Rx Protocol Error Enable
#define	MLB_MIEN_CRX_BREAK   (0x1u << 26)
	(MLB_MIEN) Control Rx Break Enable
#define	MLB_MIEN_CTX_DONE   (0x1u << 27)
	(MLB_MIEN) Control Tx Packet Done Enable
#define	MLB_MIEN_CTX_PE   (0x1u << 28)
	(MLB_MIEN) Control Tx Protocol Error Enable
#define	MLB_MIEN_CTX_BREAK   (0x1u << 29)
	(MLB_MIEN) Control Tx Break Enable
#define	MLB_MLBC1_LOCK   (0x1u << 6)
	(MLB_MLBC1) MediaLB Lock Error Status (cleared by writing a 0)
#define	MLB_MLBC1_CLKM   (0x1u << 7)
	(MLB_MLBC1) MediaLB Clock Missing Status (cleared by writing a 0)
#define	MLB_MLBC1_NDA_Pos   8
#define	MLB_MLBC1_NDA_Msk   (0xffu << MLB_MLBC1_NDA_Pos)
	(MLB_MLBC1) Node Device Address
#define	MLB_MLBC1_NDA(value)   ((MLB_MLBC1_NDA_Msk & ((value) << MLB_MLBC1_NDA_Pos)))
#define	MLB_HCTL_RST0   (0x1u << 0)
	(MLB_HCTL) Address Generation Unit 0 Software Reset
#define	MLB_HCTL_RST1   (0x1u << 1)
	(MLB_HCTL) Address Generation Unit 1 Software Reset
#define	MLB_HCTL_EN   (0x1u << 15)
	(MLB_HCTL) HBI Enable
#define	MLB_HCMR_CHM_Pos   0
#define	MLB_HCMR_CHM_Msk   (0xffffffffu << MLB_HCMR_CHM_Pos)
	(MLB_HCMR[2]) Bitwise Channel Mask Bit [31:0]
#define	MLB_HCMR_CHM(value)   ((MLB_HCMR_CHM_Msk & ((value) << MLB_HCMR_CHM_Pos)))
#define	MLB_HCER_CERR_Pos   0
#define	MLB_HCER_CERR_Msk   (0xffffffffu << MLB_HCER_CERR_Pos)
	(MLB_HCER[2]) Bitwise Channel Error Bit [31:0]
#define	MLB_HCBR_CHB_Pos   0
#define	MLB_HCBR_CHB_Msk   (0xffffffffu << MLB_HCBR_CHB_Pos)
	(MLB_HCBR[2]) Bitwise Channel Busy Bit [31:0]
#define	MLB_MDAT_DATA_Pos   0
#define	MLB_MDAT_DATA_Msk   (0xffffffffu << MLB_MDAT_DATA_Pos)
	(MLB_MDAT[4]) CRT or DBR Data
#define	MLB_MDAT_DATA(value)   ((MLB_MDAT_DATA_Msk & ((value) << MLB_MDAT_DATA_Pos)))
#define	MLB_MDWE_MASK_Pos   0
#define	MLB_MDWE_MASK_Msk   (0xffffffffu << MLB_MDWE_MASK_Pos)
	(MLB_MDWE[4]) Bitwise write enable for CTR data - bits[31:0]
#define	MLB_MDWE_MASK(value)   ((MLB_MDWE_MASK_Msk & ((value) << MLB_MDWE_MASK_Pos)))
#define	MLB_MCTL_XCMP   (0x1u << 0)
	(MLB_MCTL) Transfer Complete (Write 0 to Clear)
#define	MLB_MADR_ADDR_Pos   0
#define	MLB_MADR_ADDR_Msk   (0x3fffu << MLB_MADR_ADDR_Pos)
	(MLB_MADR) CTR or DBR Address
#define	MLB_MADR_ADDR(value)   ((MLB_MADR_ADDR_Msk & ((value) << MLB_MADR_ADDR_Pos)))
#define	MLB_MADR_TB   (0x1u << 30)
	(MLB_MADR) Target Location Bit
#define	MLB_MADR_TB_CTR   (0x0u << 30)
	(MLB_MADR) Selects CTR
#define	MLB_MADR_TB_DBR   (0x1u << 30)
	(MLB_MADR) Selects DBR
#define	MLB_MADR_WNR   (0x1u << 31)
	(MLB_MADR) Write-Not-Read Selection
#define	MLB_ACTL_SCE   (0x1u << 0)
	(MLB_ACTL) Software Clear Enable
#define	MLB_ACTL_SMX   (0x1u << 1)
	(MLB_ACTL) AHB Interrupt Mux Enable
#define	MLB_ACTL_DMA_MODE   (0x1u << 2)
	(MLB_ACTL) DMA Mode
#define	MLB_ACTL_MPB   (0x1u << 4)
	(MLB_ACTL) DMA Packet Buffering Mode
#define	MLB_ACTL_MPB_SINGLE_PACKET   (0x0u << 4)
	(MLB_ACTL) Single-packet mode
#define	MLB_ACTL_MPB_MULTIPLE_PACKET   (0x1u << 4)
	(MLB_ACTL) Multiple-packet mode
#define	MLB_ACSR_CHS_Pos   0
#define	MLB_ACSR_CHS_Msk   (0xffffffffu << MLB_ACSR_CHS_Pos)
	(MLB_ACSR[2]) Interrupt Status for Logical Channels [31:0] (cleared by writing a 1)
#define	MLB_ACSR_CHS(value)   ((MLB_ACSR_CHS_Msk & ((value) << MLB_ACSR_CHS_Pos)))
#define	MLB_ACMR_CHM_Pos   0
#define	MLB_ACMR_CHM_Msk   (0xffffffffu << MLB_ACMR_CHM_Pos)
	(MLB_ACMR[2]) Bitwise Channel Mask Bits 31 to 0
#define	MLB_ACMR_CHM(value)   ((MLB_ACMR_CHM_Msk & ((value) << MLB_ACMR_CHM_Pos)))

Detailed Description

SOFTWARE API DEFINITION FOR Media LB