|
|
#define | PIO_PER_P0 (0x1u << 0) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P1 (0x1u << 1) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P2 (0x1u << 2) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P3 (0x1u << 3) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P4 (0x1u << 4) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P5 (0x1u << 5) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P6 (0x1u << 6) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P7 (0x1u << 7) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P8 (0x1u << 8) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P9 (0x1u << 9) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P10 (0x1u << 10) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P11 (0x1u << 11) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P12 (0x1u << 12) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P13 (0x1u << 13) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P14 (0x1u << 14) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P15 (0x1u << 15) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P16 (0x1u << 16) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P17 (0x1u << 17) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P18 (0x1u << 18) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P19 (0x1u << 19) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P20 (0x1u << 20) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P21 (0x1u << 21) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P22 (0x1u << 22) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P23 (0x1u << 23) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P24 (0x1u << 24) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P25 (0x1u << 25) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P26 (0x1u << 26) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P27 (0x1u << 27) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P28 (0x1u << 28) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P29 (0x1u << 29) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P30 (0x1u << 30) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PER_P31 (0x1u << 31) |
| | (PIO_PER) PIO Enable
|
| |
|
#define | PIO_PDR_P0 (0x1u << 0) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P1 (0x1u << 1) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P2 (0x1u << 2) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P3 (0x1u << 3) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P4 (0x1u << 4) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P5 (0x1u << 5) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P6 (0x1u << 6) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P7 (0x1u << 7) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P8 (0x1u << 8) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P9 (0x1u << 9) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P10 (0x1u << 10) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P11 (0x1u << 11) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P12 (0x1u << 12) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P13 (0x1u << 13) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P14 (0x1u << 14) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P15 (0x1u << 15) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P16 (0x1u << 16) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P17 (0x1u << 17) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P18 (0x1u << 18) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P19 (0x1u << 19) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P20 (0x1u << 20) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P21 (0x1u << 21) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P22 (0x1u << 22) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P23 (0x1u << 23) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P24 (0x1u << 24) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P25 (0x1u << 25) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P26 (0x1u << 26) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P27 (0x1u << 27) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P28 (0x1u << 28) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P29 (0x1u << 29) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P30 (0x1u << 30) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PDR_P31 (0x1u << 31) |
| | (PIO_PDR) PIO Disable
|
| |
|
#define | PIO_PSR_P0 (0x1u << 0) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P1 (0x1u << 1) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P2 (0x1u << 2) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P3 (0x1u << 3) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P4 (0x1u << 4) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P5 (0x1u << 5) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P6 (0x1u << 6) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P7 (0x1u << 7) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P8 (0x1u << 8) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P9 (0x1u << 9) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P10 (0x1u << 10) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P11 (0x1u << 11) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P12 (0x1u << 12) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P13 (0x1u << 13) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P14 (0x1u << 14) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P15 (0x1u << 15) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P16 (0x1u << 16) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P17 (0x1u << 17) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P18 (0x1u << 18) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P19 (0x1u << 19) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P20 (0x1u << 20) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P21 (0x1u << 21) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P22 (0x1u << 22) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P23 (0x1u << 23) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P24 (0x1u << 24) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P25 (0x1u << 25) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P26 (0x1u << 26) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P27 (0x1u << 27) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P28 (0x1u << 28) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P29 (0x1u << 29) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P30 (0x1u << 30) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_PSR_P31 (0x1u << 31) |
| | (PIO_PSR) PIO Status
|
| |
|
#define | PIO_OER_P0 (0x1u << 0) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P1 (0x1u << 1) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P2 (0x1u << 2) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P3 (0x1u << 3) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P4 (0x1u << 4) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P5 (0x1u << 5) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P6 (0x1u << 6) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P7 (0x1u << 7) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P8 (0x1u << 8) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P9 (0x1u << 9) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P10 (0x1u << 10) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P11 (0x1u << 11) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P12 (0x1u << 12) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P13 (0x1u << 13) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P14 (0x1u << 14) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P15 (0x1u << 15) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P16 (0x1u << 16) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P17 (0x1u << 17) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P18 (0x1u << 18) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P19 (0x1u << 19) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P20 (0x1u << 20) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P21 (0x1u << 21) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P22 (0x1u << 22) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P23 (0x1u << 23) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P24 (0x1u << 24) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P25 (0x1u << 25) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P26 (0x1u << 26) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P27 (0x1u << 27) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P28 (0x1u << 28) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P29 (0x1u << 29) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P30 (0x1u << 30) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_OER_P31 (0x1u << 31) |
| | (PIO_OER) Output Enable
|
| |
|
#define | PIO_ODR_P0 (0x1u << 0) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P1 (0x1u << 1) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P2 (0x1u << 2) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P3 (0x1u << 3) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P4 (0x1u << 4) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P5 (0x1u << 5) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P6 (0x1u << 6) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P7 (0x1u << 7) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P8 (0x1u << 8) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P9 (0x1u << 9) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P10 (0x1u << 10) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P11 (0x1u << 11) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P12 (0x1u << 12) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P13 (0x1u << 13) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P14 (0x1u << 14) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P15 (0x1u << 15) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P16 (0x1u << 16) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P17 (0x1u << 17) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P18 (0x1u << 18) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P19 (0x1u << 19) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P20 (0x1u << 20) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P21 (0x1u << 21) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P22 (0x1u << 22) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P23 (0x1u << 23) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P24 (0x1u << 24) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P25 (0x1u << 25) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P26 (0x1u << 26) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P27 (0x1u << 27) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P28 (0x1u << 28) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P29 (0x1u << 29) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P30 (0x1u << 30) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_ODR_P31 (0x1u << 31) |
| | (PIO_ODR) Output Disable
|
| |
|
#define | PIO_OSR_P0 (0x1u << 0) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P1 (0x1u << 1) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P2 (0x1u << 2) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P3 (0x1u << 3) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P4 (0x1u << 4) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P5 (0x1u << 5) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P6 (0x1u << 6) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P7 (0x1u << 7) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P8 (0x1u << 8) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P9 (0x1u << 9) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P10 (0x1u << 10) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P11 (0x1u << 11) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P12 (0x1u << 12) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P13 (0x1u << 13) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P14 (0x1u << 14) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P15 (0x1u << 15) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P16 (0x1u << 16) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P17 (0x1u << 17) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P18 (0x1u << 18) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P19 (0x1u << 19) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P20 (0x1u << 20) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P21 (0x1u << 21) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P22 (0x1u << 22) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P23 (0x1u << 23) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P24 (0x1u << 24) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P25 (0x1u << 25) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P26 (0x1u << 26) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P27 (0x1u << 27) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P28 (0x1u << 28) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P29 (0x1u << 29) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P30 (0x1u << 30) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_OSR_P31 (0x1u << 31) |
| | (PIO_OSR) Output Status
|
| |
|
#define | PIO_IFER_P0 (0x1u << 0) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P1 (0x1u << 1) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P2 (0x1u << 2) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P3 (0x1u << 3) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P4 (0x1u << 4) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P5 (0x1u << 5) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P6 (0x1u << 6) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P7 (0x1u << 7) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P8 (0x1u << 8) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P9 (0x1u << 9) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P10 (0x1u << 10) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P11 (0x1u << 11) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P12 (0x1u << 12) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P13 (0x1u << 13) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P14 (0x1u << 14) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P15 (0x1u << 15) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P16 (0x1u << 16) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P17 (0x1u << 17) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P18 (0x1u << 18) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P19 (0x1u << 19) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P20 (0x1u << 20) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P21 (0x1u << 21) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P22 (0x1u << 22) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P23 (0x1u << 23) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P24 (0x1u << 24) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P25 (0x1u << 25) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P26 (0x1u << 26) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P27 (0x1u << 27) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P28 (0x1u << 28) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P29 (0x1u << 29) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P30 (0x1u << 30) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFER_P31 (0x1u << 31) |
| | (PIO_IFER) Input Filter Enable
|
| |
|
#define | PIO_IFDR_P0 (0x1u << 0) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P1 (0x1u << 1) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P2 (0x1u << 2) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P3 (0x1u << 3) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P4 (0x1u << 4) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P5 (0x1u << 5) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P6 (0x1u << 6) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P7 (0x1u << 7) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P8 (0x1u << 8) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P9 (0x1u << 9) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P10 (0x1u << 10) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P11 (0x1u << 11) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P12 (0x1u << 12) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P13 (0x1u << 13) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P14 (0x1u << 14) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P15 (0x1u << 15) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P16 (0x1u << 16) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P17 (0x1u << 17) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P18 (0x1u << 18) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P19 (0x1u << 19) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P20 (0x1u << 20) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P21 (0x1u << 21) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P22 (0x1u << 22) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P23 (0x1u << 23) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P24 (0x1u << 24) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P25 (0x1u << 25) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P26 (0x1u << 26) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P27 (0x1u << 27) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P28 (0x1u << 28) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P29 (0x1u << 29) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P30 (0x1u << 30) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFDR_P31 (0x1u << 31) |
| | (PIO_IFDR) Input Filter Disable
|
| |
|
#define | PIO_IFSR_P0 (0x1u << 0) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P1 (0x1u << 1) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P2 (0x1u << 2) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P3 (0x1u << 3) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P4 (0x1u << 4) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P5 (0x1u << 5) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P6 (0x1u << 6) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P7 (0x1u << 7) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P8 (0x1u << 8) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P9 (0x1u << 9) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P10 (0x1u << 10) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P11 (0x1u << 11) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P12 (0x1u << 12) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P13 (0x1u << 13) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P14 (0x1u << 14) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P15 (0x1u << 15) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P16 (0x1u << 16) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P17 (0x1u << 17) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P18 (0x1u << 18) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P19 (0x1u << 19) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P20 (0x1u << 20) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P21 (0x1u << 21) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P22 (0x1u << 22) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P23 (0x1u << 23) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P24 (0x1u << 24) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P25 (0x1u << 25) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P26 (0x1u << 26) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P27 (0x1u << 27) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P28 (0x1u << 28) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P29 (0x1u << 29) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P30 (0x1u << 30) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_IFSR_P31 (0x1u << 31) |
| | (PIO_IFSR) Input Filter Status
|
| |
|
#define | PIO_SODR_P0 (0x1u << 0) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P1 (0x1u << 1) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P2 (0x1u << 2) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P3 (0x1u << 3) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P4 (0x1u << 4) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P5 (0x1u << 5) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P6 (0x1u << 6) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P7 (0x1u << 7) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P8 (0x1u << 8) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P9 (0x1u << 9) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P10 (0x1u << 10) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P11 (0x1u << 11) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P12 (0x1u << 12) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P13 (0x1u << 13) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P14 (0x1u << 14) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P15 (0x1u << 15) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P16 (0x1u << 16) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P17 (0x1u << 17) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P18 (0x1u << 18) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P19 (0x1u << 19) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P20 (0x1u << 20) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P21 (0x1u << 21) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P22 (0x1u << 22) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P23 (0x1u << 23) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P24 (0x1u << 24) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P25 (0x1u << 25) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P26 (0x1u << 26) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P27 (0x1u << 27) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P28 (0x1u << 28) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P29 (0x1u << 29) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P30 (0x1u << 30) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_SODR_P31 (0x1u << 31) |
| | (PIO_SODR) Set Output Data
|
| |
|
#define | PIO_CODR_P0 (0x1u << 0) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P1 (0x1u << 1) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P2 (0x1u << 2) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P3 (0x1u << 3) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P4 (0x1u << 4) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P5 (0x1u << 5) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P6 (0x1u << 6) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P7 (0x1u << 7) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P8 (0x1u << 8) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P9 (0x1u << 9) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P10 (0x1u << 10) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P11 (0x1u << 11) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P12 (0x1u << 12) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P13 (0x1u << 13) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P14 (0x1u << 14) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P15 (0x1u << 15) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P16 (0x1u << 16) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P17 (0x1u << 17) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P18 (0x1u << 18) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P19 (0x1u << 19) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P20 (0x1u << 20) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P21 (0x1u << 21) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P22 (0x1u << 22) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P23 (0x1u << 23) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P24 (0x1u << 24) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P25 (0x1u << 25) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P26 (0x1u << 26) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P27 (0x1u << 27) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P28 (0x1u << 28) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P29 (0x1u << 29) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P30 (0x1u << 30) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_CODR_P31 (0x1u << 31) |
| | (PIO_CODR) Clear Output Data
|
| |
|
#define | PIO_ODSR_P0 (0x1u << 0) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P1 (0x1u << 1) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P2 (0x1u << 2) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P3 (0x1u << 3) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P4 (0x1u << 4) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P5 (0x1u << 5) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P6 (0x1u << 6) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P7 (0x1u << 7) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P8 (0x1u << 8) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P9 (0x1u << 9) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P10 (0x1u << 10) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P11 (0x1u << 11) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P12 (0x1u << 12) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P13 (0x1u << 13) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P14 (0x1u << 14) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P15 (0x1u << 15) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P16 (0x1u << 16) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P17 (0x1u << 17) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P18 (0x1u << 18) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P19 (0x1u << 19) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P20 (0x1u << 20) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P21 (0x1u << 21) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P22 (0x1u << 22) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P23 (0x1u << 23) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P24 (0x1u << 24) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P25 (0x1u << 25) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P26 (0x1u << 26) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P27 (0x1u << 27) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P28 (0x1u << 28) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P29 (0x1u << 29) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P30 (0x1u << 30) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_ODSR_P31 (0x1u << 31) |
| | (PIO_ODSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P0 (0x1u << 0) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P1 (0x1u << 1) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P2 (0x1u << 2) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P3 (0x1u << 3) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P4 (0x1u << 4) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P5 (0x1u << 5) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P6 (0x1u << 6) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P7 (0x1u << 7) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P8 (0x1u << 8) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P9 (0x1u << 9) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P10 (0x1u << 10) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P11 (0x1u << 11) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P12 (0x1u << 12) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P13 (0x1u << 13) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P14 (0x1u << 14) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P15 (0x1u << 15) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P16 (0x1u << 16) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P17 (0x1u << 17) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P18 (0x1u << 18) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P19 (0x1u << 19) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P20 (0x1u << 20) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P21 (0x1u << 21) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P22 (0x1u << 22) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P23 (0x1u << 23) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P24 (0x1u << 24) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P25 (0x1u << 25) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P26 (0x1u << 26) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P27 (0x1u << 27) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P28 (0x1u << 28) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P29 (0x1u << 29) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P30 (0x1u << 30) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_PDSR_P31 (0x1u << 31) |
| | (PIO_PDSR) Output Data Status
|
| |
|
#define | PIO_IER_P0 (0x1u << 0) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P1 (0x1u << 1) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P2 (0x1u << 2) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P3 (0x1u << 3) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P4 (0x1u << 4) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P5 (0x1u << 5) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P6 (0x1u << 6) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P7 (0x1u << 7) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P8 (0x1u << 8) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P9 (0x1u << 9) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P10 (0x1u << 10) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P11 (0x1u << 11) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P12 (0x1u << 12) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P13 (0x1u << 13) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P14 (0x1u << 14) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P15 (0x1u << 15) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P16 (0x1u << 16) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P17 (0x1u << 17) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P18 (0x1u << 18) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P19 (0x1u << 19) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P20 (0x1u << 20) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P21 (0x1u << 21) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P22 (0x1u << 22) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P23 (0x1u << 23) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P24 (0x1u << 24) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P25 (0x1u << 25) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P26 (0x1u << 26) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P27 (0x1u << 27) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P28 (0x1u << 28) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P29 (0x1u << 29) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P30 (0x1u << 30) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IER_P31 (0x1u << 31) |
| | (PIO_IER) Input Change Interrupt Enable
|
| |
|
#define | PIO_IDR_P0 (0x1u << 0) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P1 (0x1u << 1) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P2 (0x1u << 2) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P3 (0x1u << 3) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P4 (0x1u << 4) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P5 (0x1u << 5) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P6 (0x1u << 6) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P7 (0x1u << 7) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P8 (0x1u << 8) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P9 (0x1u << 9) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P10 (0x1u << 10) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P11 (0x1u << 11) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P12 (0x1u << 12) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P13 (0x1u << 13) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P14 (0x1u << 14) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P15 (0x1u << 15) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P16 (0x1u << 16) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P17 (0x1u << 17) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P18 (0x1u << 18) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P19 (0x1u << 19) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P20 (0x1u << 20) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P21 (0x1u << 21) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P22 (0x1u << 22) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P23 (0x1u << 23) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P24 (0x1u << 24) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P25 (0x1u << 25) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P26 (0x1u << 26) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P27 (0x1u << 27) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P28 (0x1u << 28) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P29 (0x1u << 29) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P30 (0x1u << 30) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IDR_P31 (0x1u << 31) |
| | (PIO_IDR) Input Change Interrupt Disable
|
| |
|
#define | PIO_IMR_P0 (0x1u << 0) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P1 (0x1u << 1) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P2 (0x1u << 2) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P3 (0x1u << 3) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P4 (0x1u << 4) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P5 (0x1u << 5) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P6 (0x1u << 6) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P7 (0x1u << 7) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P8 (0x1u << 8) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P9 (0x1u << 9) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P10 (0x1u << 10) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P11 (0x1u << 11) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P12 (0x1u << 12) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P13 (0x1u << 13) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P14 (0x1u << 14) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P15 (0x1u << 15) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P16 (0x1u << 16) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P17 (0x1u << 17) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P18 (0x1u << 18) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P19 (0x1u << 19) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P20 (0x1u << 20) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P21 (0x1u << 21) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P22 (0x1u << 22) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P23 (0x1u << 23) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P24 (0x1u << 24) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P25 (0x1u << 25) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P26 (0x1u << 26) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P27 (0x1u << 27) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P28 (0x1u << 28) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P29 (0x1u << 29) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P30 (0x1u << 30) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_IMR_P31 (0x1u << 31) |
| | (PIO_IMR) Input Change Interrupt Mask
|
| |
|
#define | PIO_ISR_P0 (0x1u << 0) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P1 (0x1u << 1) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P2 (0x1u << 2) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P3 (0x1u << 3) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P4 (0x1u << 4) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P5 (0x1u << 5) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P6 (0x1u << 6) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P7 (0x1u << 7) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P8 (0x1u << 8) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P9 (0x1u << 9) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P10 (0x1u << 10) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P11 (0x1u << 11) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P12 (0x1u << 12) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P13 (0x1u << 13) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P14 (0x1u << 14) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P15 (0x1u << 15) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P16 (0x1u << 16) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P17 (0x1u << 17) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P18 (0x1u << 18) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P19 (0x1u << 19) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P20 (0x1u << 20) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P21 (0x1u << 21) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P22 (0x1u << 22) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P23 (0x1u << 23) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P24 (0x1u << 24) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P25 (0x1u << 25) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P26 (0x1u << 26) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P27 (0x1u << 27) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P28 (0x1u << 28) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P29 (0x1u << 29) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P30 (0x1u << 30) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_ISR_P31 (0x1u << 31) |
| | (PIO_ISR) Input Change Interrupt Status
|
| |
|
#define | PIO_MDER_P0 (0x1u << 0) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P1 (0x1u << 1) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P2 (0x1u << 2) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P3 (0x1u << 3) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P4 (0x1u << 4) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P5 (0x1u << 5) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P6 (0x1u << 6) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P7 (0x1u << 7) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P8 (0x1u << 8) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P9 (0x1u << 9) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P10 (0x1u << 10) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P11 (0x1u << 11) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P12 (0x1u << 12) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P13 (0x1u << 13) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P14 (0x1u << 14) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P15 (0x1u << 15) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P16 (0x1u << 16) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P17 (0x1u << 17) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P18 (0x1u << 18) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P19 (0x1u << 19) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P20 (0x1u << 20) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P21 (0x1u << 21) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P22 (0x1u << 22) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P23 (0x1u << 23) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P24 (0x1u << 24) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P25 (0x1u << 25) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P26 (0x1u << 26) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P27 (0x1u << 27) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P28 (0x1u << 28) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P29 (0x1u << 29) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P30 (0x1u << 30) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDER_P31 (0x1u << 31) |
| | (PIO_MDER) Multi-drive Enable
|
| |
|
#define | PIO_MDDR_P0 (0x1u << 0) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P1 (0x1u << 1) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P2 (0x1u << 2) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P3 (0x1u << 3) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P4 (0x1u << 4) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P5 (0x1u << 5) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P6 (0x1u << 6) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P7 (0x1u << 7) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P8 (0x1u << 8) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P9 (0x1u << 9) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P10 (0x1u << 10) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P11 (0x1u << 11) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P12 (0x1u << 12) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P13 (0x1u << 13) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P14 (0x1u << 14) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P15 (0x1u << 15) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P16 (0x1u << 16) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P17 (0x1u << 17) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P18 (0x1u << 18) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P19 (0x1u << 19) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P20 (0x1u << 20) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P21 (0x1u << 21) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P22 (0x1u << 22) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P23 (0x1u << 23) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P24 (0x1u << 24) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P25 (0x1u << 25) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P26 (0x1u << 26) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P27 (0x1u << 27) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P28 (0x1u << 28) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P29 (0x1u << 29) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P30 (0x1u << 30) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDDR_P31 (0x1u << 31) |
| | (PIO_MDDR) Multi-drive Disable
|
| |
|
#define | PIO_MDSR_P0 (0x1u << 0) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P1 (0x1u << 1) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P2 (0x1u << 2) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P3 (0x1u << 3) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P4 (0x1u << 4) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P5 (0x1u << 5) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P6 (0x1u << 6) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P7 (0x1u << 7) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P8 (0x1u << 8) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P9 (0x1u << 9) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P10 (0x1u << 10) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P11 (0x1u << 11) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P12 (0x1u << 12) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P13 (0x1u << 13) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P14 (0x1u << 14) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P15 (0x1u << 15) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P16 (0x1u << 16) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P17 (0x1u << 17) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P18 (0x1u << 18) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P19 (0x1u << 19) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P20 (0x1u << 20) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P21 (0x1u << 21) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P22 (0x1u << 22) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P23 (0x1u << 23) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P24 (0x1u << 24) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P25 (0x1u << 25) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P26 (0x1u << 26) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P27 (0x1u << 27) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P28 (0x1u << 28) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P29 (0x1u << 29) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P30 (0x1u << 30) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_MDSR_P31 (0x1u << 31) |
| | (PIO_MDSR) Multi-drive Status
|
| |
|
#define | PIO_PUDR_P0 (0x1u << 0) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P1 (0x1u << 1) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P2 (0x1u << 2) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P3 (0x1u << 3) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P4 (0x1u << 4) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P5 (0x1u << 5) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P6 (0x1u << 6) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P7 (0x1u << 7) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P8 (0x1u << 8) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P9 (0x1u << 9) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P10 (0x1u << 10) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P11 (0x1u << 11) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P12 (0x1u << 12) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P13 (0x1u << 13) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P14 (0x1u << 14) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P15 (0x1u << 15) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P16 (0x1u << 16) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P17 (0x1u << 17) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P18 (0x1u << 18) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P19 (0x1u << 19) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P20 (0x1u << 20) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P21 (0x1u << 21) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P22 (0x1u << 22) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P23 (0x1u << 23) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P24 (0x1u << 24) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P25 (0x1u << 25) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P26 (0x1u << 26) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P27 (0x1u << 27) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P28 (0x1u << 28) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P29 (0x1u << 29) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P30 (0x1u << 30) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUDR_P31 (0x1u << 31) |
| | (PIO_PUDR) Pull-Up Disable
|
| |
|
#define | PIO_PUER_P0 (0x1u << 0) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P1 (0x1u << 1) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P2 (0x1u << 2) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P3 (0x1u << 3) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P4 (0x1u << 4) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P5 (0x1u << 5) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P6 (0x1u << 6) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P7 (0x1u << 7) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P8 (0x1u << 8) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P9 (0x1u << 9) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P10 (0x1u << 10) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P11 (0x1u << 11) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P12 (0x1u << 12) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P13 (0x1u << 13) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P14 (0x1u << 14) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P15 (0x1u << 15) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P16 (0x1u << 16) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P17 (0x1u << 17) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P18 (0x1u << 18) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P19 (0x1u << 19) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P20 (0x1u << 20) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P21 (0x1u << 21) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P22 (0x1u << 22) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P23 (0x1u << 23) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P24 (0x1u << 24) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P25 (0x1u << 25) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P26 (0x1u << 26) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P27 (0x1u << 27) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P28 (0x1u << 28) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P29 (0x1u << 29) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P30 (0x1u << 30) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUER_P31 (0x1u << 31) |
| | (PIO_PUER) Pull-Up Enable
|
| |
|
#define | PIO_PUSR_P0 (0x1u << 0) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P1 (0x1u << 1) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P2 (0x1u << 2) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P3 (0x1u << 3) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P4 (0x1u << 4) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P5 (0x1u << 5) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P6 (0x1u << 6) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P7 (0x1u << 7) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P8 (0x1u << 8) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P9 (0x1u << 9) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P10 (0x1u << 10) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P11 (0x1u << 11) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P12 (0x1u << 12) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P13 (0x1u << 13) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P14 (0x1u << 14) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P15 (0x1u << 15) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P16 (0x1u << 16) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P17 (0x1u << 17) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P18 (0x1u << 18) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P19 (0x1u << 19) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P20 (0x1u << 20) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P21 (0x1u << 21) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P22 (0x1u << 22) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P23 (0x1u << 23) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P24 (0x1u << 24) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P25 (0x1u << 25) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P26 (0x1u << 26) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P27 (0x1u << 27) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P28 (0x1u << 28) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P29 (0x1u << 29) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P30 (0x1u << 30) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_PUSR_P31 (0x1u << 31) |
| | (PIO_PUSR) Pull-Up Status
|
| |
|
#define | PIO_ABCDSR_P0 (0x1u << 0) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P1 (0x1u << 1) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P2 (0x1u << 2) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P3 (0x1u << 3) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P4 (0x1u << 4) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P5 (0x1u << 5) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P6 (0x1u << 6) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P7 (0x1u << 7) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P8 (0x1u << 8) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P9 (0x1u << 9) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P10 (0x1u << 10) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P11 (0x1u << 11) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P12 (0x1u << 12) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P13 (0x1u << 13) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P14 (0x1u << 14) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P15 (0x1u << 15) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P16 (0x1u << 16) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P17 (0x1u << 17) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P18 (0x1u << 18) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P19 (0x1u << 19) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P20 (0x1u << 20) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P21 (0x1u << 21) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P22 (0x1u << 22) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P23 (0x1u << 23) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P24 (0x1u << 24) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P25 (0x1u << 25) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P26 (0x1u << 26) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P27 (0x1u << 27) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P28 (0x1u << 28) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P29 (0x1u << 29) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P30 (0x1u << 30) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_ABCDSR_P31 (0x1u << 31) |
| | (PIO_ABCDSR[2]) Peripheral Select
|
| |
|
#define | PIO_IFSCDR_P0 (0x1u << 0) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P1 (0x1u << 1) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P2 (0x1u << 2) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P3 (0x1u << 3) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P4 (0x1u << 4) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P5 (0x1u << 5) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P6 (0x1u << 6) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P7 (0x1u << 7) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P8 (0x1u << 8) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P9 (0x1u << 9) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P10 (0x1u << 10) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P11 (0x1u << 11) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P12 (0x1u << 12) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P13 (0x1u << 13) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P14 (0x1u << 14) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P15 (0x1u << 15) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P16 (0x1u << 16) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P17 (0x1u << 17) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P18 (0x1u << 18) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P19 (0x1u << 19) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P20 (0x1u << 20) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P21 (0x1u << 21) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P22 (0x1u << 22) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P23 (0x1u << 23) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P24 (0x1u << 24) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P25 (0x1u << 25) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P26 (0x1u << 26) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P27 (0x1u << 27) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P28 (0x1u << 28) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P29 (0x1u << 29) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P30 (0x1u << 30) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCDR_P31 (0x1u << 31) |
| | (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select
|
| |
|
#define | PIO_IFSCER_P0 (0x1u << 0) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P1 (0x1u << 1) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P2 (0x1u << 2) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P3 (0x1u << 3) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P4 (0x1u << 4) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P5 (0x1u << 5) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P6 (0x1u << 6) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P7 (0x1u << 7) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P8 (0x1u << 8) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P9 (0x1u << 9) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P10 (0x1u << 10) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P11 (0x1u << 11) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P12 (0x1u << 12) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P13 (0x1u << 13) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P14 (0x1u << 14) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P15 (0x1u << 15) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P16 (0x1u << 16) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P17 (0x1u << 17) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P18 (0x1u << 18) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P19 (0x1u << 19) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P20 (0x1u << 20) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P21 (0x1u << 21) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P22 (0x1u << 22) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P23 (0x1u << 23) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P24 (0x1u << 24) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P25 (0x1u << 25) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P26 (0x1u << 26) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P27 (0x1u << 27) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P28 (0x1u << 28) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P29 (0x1u << 29) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P30 (0x1u << 30) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCER_P31 (0x1u << 31) |
| | (PIO_IFSCER) Slow Clock Debouncing Filtering Select
|
| |
|
#define | PIO_IFSCSR_P0 (0x1u << 0) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P1 (0x1u << 1) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P2 (0x1u << 2) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P3 (0x1u << 3) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P4 (0x1u << 4) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P5 (0x1u << 5) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P6 (0x1u << 6) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P7 (0x1u << 7) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P8 (0x1u << 8) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P9 (0x1u << 9) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P10 (0x1u << 10) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P11 (0x1u << 11) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P12 (0x1u << 12) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P13 (0x1u << 13) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P14 (0x1u << 14) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P15 (0x1u << 15) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P16 (0x1u << 16) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P17 (0x1u << 17) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P18 (0x1u << 18) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P19 (0x1u << 19) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P20 (0x1u << 20) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P21 (0x1u << 21) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P22 (0x1u << 22) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P23 (0x1u << 23) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P24 (0x1u << 24) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P25 (0x1u << 25) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P26 (0x1u << 26) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P27 (0x1u << 27) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P28 (0x1u << 28) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P29 (0x1u << 29) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P30 (0x1u << 30) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_IFSCSR_P31 (0x1u << 31) |
| | (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status
|
| |
|
#define | PIO_SCDR_DIV_Pos 0 |
| |
|
#define | PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) |
| | (PIO_SCDR) Slow Clock Divider Selection for Debouncing
|
| |
|
#define | PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) |
| |
|
#define | PIO_PPDDR_P0 (0x1u << 0) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P1 (0x1u << 1) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P2 (0x1u << 2) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P3 (0x1u << 3) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P4 (0x1u << 4) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P5 (0x1u << 5) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P6 (0x1u << 6) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P7 (0x1u << 7) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P8 (0x1u << 8) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P9 (0x1u << 9) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P10 (0x1u << 10) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P11 (0x1u << 11) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P12 (0x1u << 12) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P13 (0x1u << 13) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P14 (0x1u << 14) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P15 (0x1u << 15) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P16 (0x1u << 16) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P17 (0x1u << 17) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P18 (0x1u << 18) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P19 (0x1u << 19) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P20 (0x1u << 20) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P21 (0x1u << 21) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P22 (0x1u << 22) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P23 (0x1u << 23) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P24 (0x1u << 24) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P25 (0x1u << 25) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P26 (0x1u << 26) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P27 (0x1u << 27) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P28 (0x1u << 28) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P29 (0x1u << 29) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P30 (0x1u << 30) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDDR_P31 (0x1u << 31) |
| | (PIO_PPDDR) Pull-Down Disable
|
| |
|
#define | PIO_PPDER_P0 (0x1u << 0) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P1 (0x1u << 1) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P2 (0x1u << 2) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P3 (0x1u << 3) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P4 (0x1u << 4) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P5 (0x1u << 5) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P6 (0x1u << 6) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P7 (0x1u << 7) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P8 (0x1u << 8) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P9 (0x1u << 9) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P10 (0x1u << 10) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P11 (0x1u << 11) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P12 (0x1u << 12) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P13 (0x1u << 13) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P14 (0x1u << 14) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P15 (0x1u << 15) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P16 (0x1u << 16) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P17 (0x1u << 17) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P18 (0x1u << 18) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P19 (0x1u << 19) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P20 (0x1u << 20) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P21 (0x1u << 21) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P22 (0x1u << 22) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P23 (0x1u << 23) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P24 (0x1u << 24) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P25 (0x1u << 25) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P26 (0x1u << 26) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P27 (0x1u << 27) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P28 (0x1u << 28) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P29 (0x1u << 29) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P30 (0x1u << 30) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDER_P31 (0x1u << 31) |
| | (PIO_PPDER) Pull-Down Enable
|
| |
|
#define | PIO_PPDSR_P0 (0x1u << 0) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P1 (0x1u << 1) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P2 (0x1u << 2) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P3 (0x1u << 3) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P4 (0x1u << 4) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P5 (0x1u << 5) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P6 (0x1u << 6) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P7 (0x1u << 7) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P8 (0x1u << 8) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P9 (0x1u << 9) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P10 (0x1u << 10) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P11 (0x1u << 11) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P12 (0x1u << 12) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P13 (0x1u << 13) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P14 (0x1u << 14) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P15 (0x1u << 15) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P16 (0x1u << 16) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P17 (0x1u << 17) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P18 (0x1u << 18) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P19 (0x1u << 19) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P20 (0x1u << 20) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P21 (0x1u << 21) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P22 (0x1u << 22) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P23 (0x1u << 23) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P24 (0x1u << 24) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P25 (0x1u << 25) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P26 (0x1u << 26) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P27 (0x1u << 27) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P28 (0x1u << 28) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P29 (0x1u << 29) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P30 (0x1u << 30) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_PPDSR_P31 (0x1u << 31) |
| | (PIO_PPDSR) Pull-Down Status
|
| |
|
#define | PIO_OWER_P0 (0x1u << 0) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P1 (0x1u << 1) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P2 (0x1u << 2) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P3 (0x1u << 3) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P4 (0x1u << 4) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P5 (0x1u << 5) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P6 (0x1u << 6) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P7 (0x1u << 7) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P8 (0x1u << 8) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P9 (0x1u << 9) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P10 (0x1u << 10) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P11 (0x1u << 11) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P12 (0x1u << 12) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P13 (0x1u << 13) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P14 (0x1u << 14) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P15 (0x1u << 15) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P16 (0x1u << 16) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P17 (0x1u << 17) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P18 (0x1u << 18) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P19 (0x1u << 19) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P20 (0x1u << 20) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P21 (0x1u << 21) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P22 (0x1u << 22) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P23 (0x1u << 23) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P24 (0x1u << 24) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P25 (0x1u << 25) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P26 (0x1u << 26) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P27 (0x1u << 27) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P28 (0x1u << 28) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P29 (0x1u << 29) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P30 (0x1u << 30) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWER_P31 (0x1u << 31) |
| | (PIO_OWER) Output Write Enable
|
| |
|
#define | PIO_OWDR_P0 (0x1u << 0) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P1 (0x1u << 1) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P2 (0x1u << 2) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P3 (0x1u << 3) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P4 (0x1u << 4) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P5 (0x1u << 5) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P6 (0x1u << 6) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P7 (0x1u << 7) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P8 (0x1u << 8) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P9 (0x1u << 9) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P10 (0x1u << 10) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P11 (0x1u << 11) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P12 (0x1u << 12) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P13 (0x1u << 13) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P14 (0x1u << 14) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P15 (0x1u << 15) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P16 (0x1u << 16) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P17 (0x1u << 17) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P18 (0x1u << 18) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P19 (0x1u << 19) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P20 (0x1u << 20) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P21 (0x1u << 21) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P22 (0x1u << 22) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P23 (0x1u << 23) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P24 (0x1u << 24) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P25 (0x1u << 25) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P26 (0x1u << 26) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P27 (0x1u << 27) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P28 (0x1u << 28) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P29 (0x1u << 29) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P30 (0x1u << 30) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWDR_P31 (0x1u << 31) |
| | (PIO_OWDR) Output Write Disable
|
| |
|
#define | PIO_OWSR_P0 (0x1u << 0) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P1 (0x1u << 1) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P2 (0x1u << 2) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P3 (0x1u << 3) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P4 (0x1u << 4) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P5 (0x1u << 5) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P6 (0x1u << 6) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P7 (0x1u << 7) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P8 (0x1u << 8) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P9 (0x1u << 9) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P10 (0x1u << 10) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P11 (0x1u << 11) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P12 (0x1u << 12) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P13 (0x1u << 13) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P14 (0x1u << 14) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P15 (0x1u << 15) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P16 (0x1u << 16) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P17 (0x1u << 17) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P18 (0x1u << 18) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P19 (0x1u << 19) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P20 (0x1u << 20) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P21 (0x1u << 21) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P22 (0x1u << 22) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P23 (0x1u << 23) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P24 (0x1u << 24) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P25 (0x1u << 25) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P26 (0x1u << 26) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P27 (0x1u << 27) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P28 (0x1u << 28) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P29 (0x1u << 29) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P30 (0x1u << 30) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_OWSR_P31 (0x1u << 31) |
| | (PIO_OWSR) Output Write Status
|
| |
|
#define | PIO_AIMER_P0 (0x1u << 0) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P1 (0x1u << 1) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P2 (0x1u << 2) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P3 (0x1u << 3) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P4 (0x1u << 4) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P5 (0x1u << 5) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P6 (0x1u << 6) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P7 (0x1u << 7) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P8 (0x1u << 8) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P9 (0x1u << 9) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P10 (0x1u << 10) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P11 (0x1u << 11) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P12 (0x1u << 12) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P13 (0x1u << 13) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P14 (0x1u << 14) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P15 (0x1u << 15) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P16 (0x1u << 16) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P17 (0x1u << 17) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P18 (0x1u << 18) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P19 (0x1u << 19) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P20 (0x1u << 20) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P21 (0x1u << 21) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P22 (0x1u << 22) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P23 (0x1u << 23) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P24 (0x1u << 24) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P25 (0x1u << 25) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P26 (0x1u << 26) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P27 (0x1u << 27) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P28 (0x1u << 28) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P29 (0x1u << 29) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P30 (0x1u << 30) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMER_P31 (0x1u << 31) |
| | (PIO_AIMER) Additional Interrupt Modes Enable
|
| |
|
#define | PIO_AIMDR_P0 (0x1u << 0) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P1 (0x1u << 1) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P2 (0x1u << 2) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P3 (0x1u << 3) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P4 (0x1u << 4) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P5 (0x1u << 5) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P6 (0x1u << 6) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P7 (0x1u << 7) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P8 (0x1u << 8) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P9 (0x1u << 9) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P10 (0x1u << 10) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P11 (0x1u << 11) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P12 (0x1u << 12) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P13 (0x1u << 13) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P14 (0x1u << 14) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P15 (0x1u << 15) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P16 (0x1u << 16) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P17 (0x1u << 17) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P18 (0x1u << 18) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P19 (0x1u << 19) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P20 (0x1u << 20) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P21 (0x1u << 21) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P22 (0x1u << 22) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P23 (0x1u << 23) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P24 (0x1u << 24) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P25 (0x1u << 25) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P26 (0x1u << 26) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P27 (0x1u << 27) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P28 (0x1u << 28) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P29 (0x1u << 29) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P30 (0x1u << 30) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMDR_P31 (0x1u << 31) |
| | (PIO_AIMDR) Additional Interrupt Modes Disable
|
| |
|
#define | PIO_AIMMR_P0 (0x1u << 0) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P1 (0x1u << 1) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P2 (0x1u << 2) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P3 (0x1u << 3) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P4 (0x1u << 4) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P5 (0x1u << 5) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P6 (0x1u << 6) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P7 (0x1u << 7) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P8 (0x1u << 8) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P9 (0x1u << 9) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P10 (0x1u << 10) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P11 (0x1u << 11) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P12 (0x1u << 12) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P13 (0x1u << 13) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P14 (0x1u << 14) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P15 (0x1u << 15) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P16 (0x1u << 16) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P17 (0x1u << 17) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P18 (0x1u << 18) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P19 (0x1u << 19) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P20 (0x1u << 20) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P21 (0x1u << 21) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P22 (0x1u << 22) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P23 (0x1u << 23) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P24 (0x1u << 24) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P25 (0x1u << 25) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P26 (0x1u << 26) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P27 (0x1u << 27) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P28 (0x1u << 28) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P29 (0x1u << 29) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P30 (0x1u << 30) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_AIMMR_P31 (0x1u << 31) |
| | (PIO_AIMMR) IO Line Index
|
| |
|
#define | PIO_ESR_P0 (0x1u << 0) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P1 (0x1u << 1) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P2 (0x1u << 2) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P3 (0x1u << 3) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P4 (0x1u << 4) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P5 (0x1u << 5) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P6 (0x1u << 6) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P7 (0x1u << 7) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P8 (0x1u << 8) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P9 (0x1u << 9) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P10 (0x1u << 10) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P11 (0x1u << 11) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P12 (0x1u << 12) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P13 (0x1u << 13) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P14 (0x1u << 14) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P15 (0x1u << 15) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P16 (0x1u << 16) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P17 (0x1u << 17) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P18 (0x1u << 18) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P19 (0x1u << 19) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P20 (0x1u << 20) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P21 (0x1u << 21) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P22 (0x1u << 22) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P23 (0x1u << 23) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P24 (0x1u << 24) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P25 (0x1u << 25) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P26 (0x1u << 26) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P27 (0x1u << 27) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P28 (0x1u << 28) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P29 (0x1u << 29) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P30 (0x1u << 30) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_ESR_P31 (0x1u << 31) |
| | (PIO_ESR) Edge Interrupt Selection
|
| |
|
#define | PIO_LSR_P0 (0x1u << 0) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P1 (0x1u << 1) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P2 (0x1u << 2) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P3 (0x1u << 3) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P4 (0x1u << 4) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P5 (0x1u << 5) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P6 (0x1u << 6) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P7 (0x1u << 7) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P8 (0x1u << 8) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P9 (0x1u << 9) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P10 (0x1u << 10) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P11 (0x1u << 11) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P12 (0x1u << 12) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P13 (0x1u << 13) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P14 (0x1u << 14) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P15 (0x1u << 15) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P16 (0x1u << 16) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P17 (0x1u << 17) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P18 (0x1u << 18) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P19 (0x1u << 19) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P20 (0x1u << 20) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P21 (0x1u << 21) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P22 (0x1u << 22) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P23 (0x1u << 23) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P24 (0x1u << 24) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P25 (0x1u << 25) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P26 (0x1u << 26) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P27 (0x1u << 27) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P28 (0x1u << 28) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P29 (0x1u << 29) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P30 (0x1u << 30) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_LSR_P31 (0x1u << 31) |
| | (PIO_LSR) Level Interrupt Selection
|
| |
|
#define | PIO_ELSR_P0 (0x1u << 0) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P1 (0x1u << 1) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P2 (0x1u << 2) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P3 (0x1u << 3) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P4 (0x1u << 4) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P5 (0x1u << 5) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P6 (0x1u << 6) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P7 (0x1u << 7) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P8 (0x1u << 8) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P9 (0x1u << 9) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P10 (0x1u << 10) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P11 (0x1u << 11) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P12 (0x1u << 12) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P13 (0x1u << 13) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P14 (0x1u << 14) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P15 (0x1u << 15) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P16 (0x1u << 16) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P17 (0x1u << 17) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P18 (0x1u << 18) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P19 (0x1u << 19) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P20 (0x1u << 20) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P21 (0x1u << 21) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P22 (0x1u << 22) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P23 (0x1u << 23) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P24 (0x1u << 24) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P25 (0x1u << 25) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P26 (0x1u << 26) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P27 (0x1u << 27) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P28 (0x1u << 28) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P29 (0x1u << 29) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P30 (0x1u << 30) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_ELSR_P31 (0x1u << 31) |
| | (PIO_ELSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FELLSR_P0 (0x1u << 0) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P1 (0x1u << 1) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P2 (0x1u << 2) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P3 (0x1u << 3) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P4 (0x1u << 4) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P5 (0x1u << 5) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P6 (0x1u << 6) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P7 (0x1u << 7) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P8 (0x1u << 8) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P9 (0x1u << 9) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P10 (0x1u << 10) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P11 (0x1u << 11) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P12 (0x1u << 12) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P13 (0x1u << 13) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P14 (0x1u << 14) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P15 (0x1u << 15) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P16 (0x1u << 16) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P17 (0x1u << 17) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P18 (0x1u << 18) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P19 (0x1u << 19) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P20 (0x1u << 20) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P21 (0x1u << 21) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P22 (0x1u << 22) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P23 (0x1u << 23) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P24 (0x1u << 24) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P25 (0x1u << 25) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P26 (0x1u << 26) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P27 (0x1u << 27) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P28 (0x1u << 28) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P29 (0x1u << 29) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P30 (0x1u << 30) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_FELLSR_P31 (0x1u << 31) |
| | (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P0 (0x1u << 0) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P1 (0x1u << 1) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P2 (0x1u << 2) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P3 (0x1u << 3) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P4 (0x1u << 4) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P5 (0x1u << 5) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P6 (0x1u << 6) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P7 (0x1u << 7) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P8 (0x1u << 8) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P9 (0x1u << 9) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P10 (0x1u << 10) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P11 (0x1u << 11) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P12 (0x1u << 12) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P13 (0x1u << 13) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P14 (0x1u << 14) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P15 (0x1u << 15) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P16 (0x1u << 16) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P17 (0x1u << 17) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P18 (0x1u << 18) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P19 (0x1u << 19) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P20 (0x1u << 20) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P21 (0x1u << 21) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P22 (0x1u << 22) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P23 (0x1u << 23) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P24 (0x1u << 24) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P25 (0x1u << 25) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P26 (0x1u << 26) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P27 (0x1u << 27) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P28 (0x1u << 28) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P29 (0x1u << 29) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P30 (0x1u << 30) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_REHLSR_P31 (0x1u << 31) |
| | (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection
|
| |
|
#define | PIO_FRLHSR_P0 (0x1u << 0) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P1 (0x1u << 1) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P2 (0x1u << 2) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P3 (0x1u << 3) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P4 (0x1u << 4) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P5 (0x1u << 5) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P6 (0x1u << 6) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P7 (0x1u << 7) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P8 (0x1u << 8) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P9 (0x1u << 9) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P10 (0x1u << 10) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P11 (0x1u << 11) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P12 (0x1u << 12) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P13 (0x1u << 13) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P14 (0x1u << 14) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P15 (0x1u << 15) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P16 (0x1u << 16) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P17 (0x1u << 17) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P18 (0x1u << 18) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P19 (0x1u << 19) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P20 (0x1u << 20) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P21 (0x1u << 21) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P22 (0x1u << 22) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P23 (0x1u << 23) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P24 (0x1u << 24) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P25 (0x1u << 25) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P26 (0x1u << 26) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P27 (0x1u << 27) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P28 (0x1u << 28) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P29 (0x1u << 29) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P30 (0x1u << 30) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_FRLHSR_P31 (0x1u << 31) |
| | (PIO_FRLHSR) Edge/Level Interrupt Source Selection
|
| |
|
#define | PIO_LOCKSR_P0 (0x1u << 0) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P1 (0x1u << 1) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P2 (0x1u << 2) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P3 (0x1u << 3) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P4 (0x1u << 4) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P5 (0x1u << 5) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P6 (0x1u << 6) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P7 (0x1u << 7) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P8 (0x1u << 8) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P9 (0x1u << 9) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P10 (0x1u << 10) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P11 (0x1u << 11) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P12 (0x1u << 12) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P13 (0x1u << 13) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P14 (0x1u << 14) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P15 (0x1u << 15) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P16 (0x1u << 16) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P17 (0x1u << 17) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P18 (0x1u << 18) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P19 (0x1u << 19) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P20 (0x1u << 20) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P21 (0x1u << 21) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P22 (0x1u << 22) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P23 (0x1u << 23) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P24 (0x1u << 24) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P25 (0x1u << 25) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P26 (0x1u << 26) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P27 (0x1u << 27) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P28 (0x1u << 28) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P29 (0x1u << 29) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P30 (0x1u << 30) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_LOCKSR_P31 (0x1u << 31) |
| | (PIO_LOCKSR) Lock Status
|
| |
|
#define | PIO_WPMR_WPEN (0x1u << 0) |
| | (PIO_WPMR) Write Protection Enable
|
| |
|
#define | PIO_WPMR_WPKEY_Pos 8 |
| |
|
#define | PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) |
| | (PIO_WPMR) Write Protection Key
|
| |
|
#define | PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) |
| |
|
#define | PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) |
| | (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
|
| |
|
#define | PIO_WPSR_WPVS (0x1u << 0) |
| | (PIO_WPSR) Write Protection Violation Status
|
| |
|
#define | PIO_WPSR_WPVSRC_Pos 8 |
| |
|
#define | PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) |
| | (PIO_WPSR) Write Protection Violation Source
|
| |
|
#define | PIO_SCHMITT_SCHMITT0 (0x1u << 0) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT1 (0x1u << 1) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT2 (0x1u << 2) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT3 (0x1u << 3) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT4 (0x1u << 4) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT5 (0x1u << 5) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT6 (0x1u << 6) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT7 (0x1u << 7) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT8 (0x1u << 8) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT9 (0x1u << 9) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT10 (0x1u << 10) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT11 (0x1u << 11) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT12 (0x1u << 12) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT13 (0x1u << 13) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT14 (0x1u << 14) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT15 (0x1u << 15) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT16 (0x1u << 16) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT17 (0x1u << 17) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT18 (0x1u << 18) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT19 (0x1u << 19) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT20 (0x1u << 20) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT21 (0x1u << 21) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT22 (0x1u << 22) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT23 (0x1u << 23) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT24 (0x1u << 24) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT25 (0x1u << 25) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT26 (0x1u << 26) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT27 (0x1u << 27) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT28 (0x1u << 28) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT29 (0x1u << 29) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT30 (0x1u << 30) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_SCHMITT_SCHMITT31 (0x1u << 31) |
| | (PIO_SCHMITT) Schmitt Trigger Control
|
| |
|
#define | PIO_DRIVER_LINE0 (0x1u << 0) |
| | (PIO_DRIVER) Drive of PIO Line 0
|
| |
|
#define | PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE1 (0x1u << 1) |
| | (PIO_DRIVER) Drive of PIO Line 1
|
| |
|
#define | PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE2 (0x1u << 2) |
| | (PIO_DRIVER) Drive of PIO Line 2
|
| |
|
#define | PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE3 (0x1u << 3) |
| | (PIO_DRIVER) Drive of PIO Line 3
|
| |
|
#define | PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE4 (0x1u << 4) |
| | (PIO_DRIVER) Drive of PIO Line 4
|
| |
|
#define | PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE5 (0x1u << 5) |
| | (PIO_DRIVER) Drive of PIO Line 5
|
| |
|
#define | PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE6 (0x1u << 6) |
| | (PIO_DRIVER) Drive of PIO Line 6
|
| |
|
#define | PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE7 (0x1u << 7) |
| | (PIO_DRIVER) Drive of PIO Line 7
|
| |
|
#define | PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE8 (0x1u << 8) |
| | (PIO_DRIVER) Drive of PIO Line 8
|
| |
|
#define | PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE9 (0x1u << 9) |
| | (PIO_DRIVER) Drive of PIO Line 9
|
| |
|
#define | PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE10 (0x1u << 10) |
| | (PIO_DRIVER) Drive of PIO Line 10
|
| |
|
#define | PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE11 (0x1u << 11) |
| | (PIO_DRIVER) Drive of PIO Line 11
|
| |
|
#define | PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE12 (0x1u << 12) |
| | (PIO_DRIVER) Drive of PIO Line 12
|
| |
|
#define | PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE13 (0x1u << 13) |
| | (PIO_DRIVER) Drive of PIO Line 13
|
| |
|
#define | PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE14 (0x1u << 14) |
| | (PIO_DRIVER) Drive of PIO Line 14
|
| |
|
#define | PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE15 (0x1u << 15) |
| | (PIO_DRIVER) Drive of PIO Line 15
|
| |
|
#define | PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE16 (0x1u << 16) |
| | (PIO_DRIVER) Drive of PIO Line 16
|
| |
|
#define | PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE17 (0x1u << 17) |
| | (PIO_DRIVER) Drive of PIO Line 17
|
| |
|
#define | PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE18 (0x1u << 18) |
| | (PIO_DRIVER) Drive of PIO Line 18
|
| |
|
#define | PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE19 (0x1u << 19) |
| | (PIO_DRIVER) Drive of PIO Line 19
|
| |
|
#define | PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE20 (0x1u << 20) |
| | (PIO_DRIVER) Drive of PIO Line 20
|
| |
|
#define | PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE21 (0x1u << 21) |
| | (PIO_DRIVER) Drive of PIO Line 21
|
| |
|
#define | PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE22 (0x1u << 22) |
| | (PIO_DRIVER) Drive of PIO Line 22
|
| |
|
#define | PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE23 (0x1u << 23) |
| | (PIO_DRIVER) Drive of PIO Line 23
|
| |
|
#define | PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE24 (0x1u << 24) |
| | (PIO_DRIVER) Drive of PIO Line 24
|
| |
|
#define | PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE25 (0x1u << 25) |
| | (PIO_DRIVER) Drive of PIO Line 25
|
| |
|
#define | PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE26 (0x1u << 26) |
| | (PIO_DRIVER) Drive of PIO Line 26
|
| |
|
#define | PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE27 (0x1u << 27) |
| | (PIO_DRIVER) Drive of PIO Line 27
|
| |
|
#define | PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE28 (0x1u << 28) |
| | (PIO_DRIVER) Drive of PIO Line 28
|
| |
|
#define | PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE29 (0x1u << 29) |
| | (PIO_DRIVER) Drive of PIO Line 29
|
| |
|
#define | PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE30 (0x1u << 30) |
| | (PIO_DRIVER) Drive of PIO Line 30
|
| |
|
#define | PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_DRIVER_LINE31 (0x1u << 31) |
| | (PIO_DRIVER) Drive of PIO Line 31
|
| |
|
#define | PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31) |
| | (PIO_DRIVER) Lowest drive
|
| |
|
#define | PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31) |
| | (PIO_DRIVER) Highest drive
|
| |
|
#define | PIO_PCMR_PCEN (0x1u << 0) |
| | (PIO_PCMR) Parallel Capture Mode Enable
|
| |
|
#define | PIO_PCMR_DSIZE_Pos 4 |
| |
|
#define | PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) |
| | (PIO_PCMR) Parallel Capture Mode Data Size
|
| |
|
#define | PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) |
| |
|
#define | PIO_PCMR_DSIZE_BYTE (0x0u << 4) |
| | (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit)
|
| |
|
#define | PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) |
| | (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit)
|
| |
|
#define | PIO_PCMR_DSIZE_WORD (0x2u << 4) |
| | (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit)
|
| |
|
#define | PIO_PCMR_ALWYS (0x1u << 9) |
| | (PIO_PCMR) Parallel Capture Mode Always Sampling
|
| |
|
#define | PIO_PCMR_HALFS (0x1u << 10) |
| | (PIO_PCMR) Parallel Capture Mode Half Sampling
|
| |
|
#define | PIO_PCMR_FRSTS (0x1u << 11) |
| | (PIO_PCMR) Parallel Capture Mode First Sample
|
| |
|
#define | PIO_PCIER_DRDY (0x1u << 0) |
| | (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable
|
| |
|
#define | PIO_PCIER_OVRE (0x1u << 1) |
| | (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable
|
| |
|
#define | PIO_PCIER_ENDRX (0x1u << 2) |
| | (PIO_PCIER) End of Reception Transfer Interrupt Enable
|
| |
|
#define | PIO_PCIER_RXBUFF (0x1u << 3) |
| | (PIO_PCIER) Reception Buffer Full Interrupt Enable
|
| |
|
#define | PIO_PCIDR_DRDY (0x1u << 0) |
| | (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable
|
| |
|
#define | PIO_PCIDR_OVRE (0x1u << 1) |
| | (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable
|
| |
|
#define | PIO_PCIDR_ENDRX (0x1u << 2) |
| | (PIO_PCIDR) End of Reception Transfer Interrupt Disable
|
| |
|
#define | PIO_PCIDR_RXBUFF (0x1u << 3) |
| | (PIO_PCIDR) Reception Buffer Full Interrupt Disable
|
| |
|
#define | PIO_PCIMR_DRDY (0x1u << 0) |
| | (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask
|
| |
|
#define | PIO_PCIMR_OVRE (0x1u << 1) |
| | (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask
|
| |
|
#define | PIO_PCIMR_ENDRX (0x1u << 2) |
| | (PIO_PCIMR) End of Reception Transfer Interrupt Mask
|
| |
|
#define | PIO_PCIMR_RXBUFF (0x1u << 3) |
| | (PIO_PCIMR) Reception Buffer Full Interrupt Mask
|
| |
|
#define | PIO_PCISR_DRDY (0x1u << 0) |
| | (PIO_PCISR) Parallel Capture Mode Data Ready
|
| |
|
#define | PIO_PCISR_OVRE (0x1u << 1) |
| | (PIO_PCISR) Parallel Capture Mode Overrun Error
|
| |
|
#define | PIO_PCRHR_RDATA_Pos 0 |
| |
|
#define | PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) |
| | (PIO_PCRHR) Parallel Capture Mode Reception Data
|
| |
1.8.15