Xilinx Zynq

Xilinx Zynq Board Support Package. More...

Modules
	Interrupt Support
	Interrupt Support.
	TM27 Test Support
	Interrupt Mechanisms for tm27 test.
	UART Support
	UART Support.

Files
file	bsp.h
	Global BSP definitions.

Macros
#define	BSP_FEATURE_IRQ_EXTENSION
#define	BSP_ARM_A9MPCORE_SCU_BASE   0xf8f00000
#define	BSP_ARM_GIC_CPUIF_BASE   0xf8f00100
#define	BSP_ARM_A9MPCORE_GT_BASE   0xf8f00200
#define	BSP_ARM_A9MPCORE_PT_BASE   0xf8f00600
#define	BSP_ARM_GIC_DIST_BASE   0xf8f01000
#define	BSP_ARM_L2C_310_BASE   0xf8f02000
#define	BSP_ARM_L2C_310_ID   0x410000c8

Functions
BSP_START_TEXT_SECTION void	zynq_setup_mmu_and_cache (void)
	Zynq specific set up of the MMU. More...
uint32_t	zynq_clock_cpu_1x (void)

Variables
zynq_uart_context	zynq_uart_instances [2]

Detailed Description

Xilinx Zynq Board Support Package.

Function Documentation

zynq_setup_mmu_and_cache()

BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache

(

void

)

Zynq specific set up of the MMU.

Provide in the application to override the defaults in the BSP. Note the defaults do not map in the GP0 and GP1 AXI ports. You should add the specific regions that map into your PL rather than just open the whole of the GP[01] address space up.