RTEMS  5.1
can-defs.h
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1 
9 /*
10  * Copyright (c) 2014 Taller Technologies.
11  *
12  * @author Diaz Marcos (marcos.diaz@tallertechnologies.com)
13  * @author Daniel Chicco (daniel.chicco@tallertechnologies.com)
14  *
15  * The license and distribution terms for this file may be
16  * found in the file LICENSE in this distribution or at
17  * http://www.rtems.org/license/LICENSE.
18  */
19 
20 #ifndef LPC176X_TIMER_DEFS_H
21 #define LPC176X_TIMER_DEFS_H
22 
23 #include <bsp/common-types.h>
24 #include <bsp/can.h>
25 
26 /* CAN ACCEPTANCE FILTER */
27 #define CAN_ACCEPT_BASE_ADDR 0x4003C000
28 
29 #define CAN_DRIVER_IS_MINOR_VALID( minor ) ( minor < CAN_DEVICES_NUMBER )
30 #define CAN_DEFAULT_BAUD_RATE 1000000u
31 #define CAN_DEFAULT_INTERRUPT_CONFIGURATION 0
32 
33 #define MAX_NUMBER_OF_CAN_BITS 25u
34 #define MIN_NUMBER_OF_CAN_BITS 4u
35 #define CAN_BRP_EXTRA_BIT 1u
36 #define CAN_TSEG_EXTRA_BITS 3u
37 #define MAX_TSEG1_TSEG2_BITS 22u
38 
39 #define CAN_GSR_RBS_MASK 1u
40 #define CAN_CMR_RRB_MASK 4u
41 
42 #define CAN_MAXIMUM_DATA_SIZE 8u
43 #define CAN10_MAXIMUM_ID 0x7FFu
44 
48 typedef enum {
49  CAN_TSEG1,
50  CAN_TSEG2,
51  CAN_NUMBER_OF_TSEG,
53 
54 #define CAN_BTR_TSEG1_SHIFT 16u
55 #define CAN_BTR_TSEG2_SHIFT 20u
56 #define CAN_BTR_SJW_SHIFT 14u
57 #define CAN_BTR_BRP_SHIFT 0u
58 
59 #define CAN_BTR_TSEG1_MASK 0x000F0000U
60 #define CAN_BTR_TSEG2_MASK 0x00700000U
61 #define CAN_BTR_SJW_MASK 0x0000C000U
62 #define CAN_BTR_BRP_MASK 0x000003FFU
63 
64 #define WRONG_BTR_VALUE 0xFFFFFFFF
65 
69 typedef enum {
70  CAN_TRANSMIT1,
71  CAN_TRANSMIT2,
72  CAN_TRANSMIT3,
73  CAN_NUMBER_OF_TRANSMIT_BUFFERS
75 
80 typedef struct {
81  uint32_t can_status_mask;
82  uint32_t not_cc_cmr_value;
84 
86 typedef struct {
87  volatile uint32_t MOD;
88  volatile uint32_t CMR;
89  volatile uint32_t GSR;
90  volatile uint32_t ICR;
91  volatile uint32_t IER;
92  volatile uint32_t BTR;
93  volatile uint32_t EWL;
94  volatile uint32_t SR;
95  volatile registers_can_message receive;
96  volatile registers_can_message transmit[ CAN_NUMBER_OF_TRANSMIT_BUFFERS ];
97 } can_device;
98 
102 typedef enum {
103  CAN_TX_PIN,
104  CAN_RX_PIN,
105  NUMBER_OF_CAN_PINS
107 
111 typedef struct {
112  can_device *const device;
113  const lpc176x_module module;
114  const uint32_t pconp_pin;
115  const uint32_t pins[ NUMBER_OF_CAN_PINS ];
116  const lpc176x_pin_function pinfunction;
118 
120 typedef struct {
121  volatile uint32_t TX_SR;
122  volatile uint32_t RX_SR;
123  volatile uint32_t MSR;
124 } can_central;
125 
127 typedef struct {
128  volatile uint32_t AFMR;
129  volatile uint32_t SFF_SA;
130  volatile uint32_t SFF_GRP_SA;
131  volatile uint32_t EFF_SA;
132  volatile uint32_t EFF_GRP_SA;
133  volatile uint32_t EOT;
134  volatile uint32_t LUT_ERR_ADR;
135  volatile uint32_t LUT_ERR;
136  volatile uint32_t FCANIE;
137  volatile uint32_t FCANIC0;
138  volatile uint32_t FCANIC1;
140 
144 typedef enum {
145  CANStandard = 0,
146  CANExtended = 1,
147  CANAny = 2
148 } can_format;
149 
153 typedef enum {
154  CANData = 0,
155  CANRemote = 1
156 } can_type;
157 
158 #define CAN_INTERRUPT_TYPE_MASK 0x1ffu
159 
163 typedef lpc176x_can_isr lpc176x_can_isr_vector[ CAN_IRQ_NUMBER ];
164 
165 #define CAN_MOD_RM 0x00000001U
166 
167 #define CAN_ACCF_AFMR_ACCOF 0x00000001U
168 #define CAN_ACCF_AFMR_ACCBP 0x00000002U
169 #define CAN_ACCF_AFMR_EFCAN 0x00000004U
170 
171 #define CAN_IER_RIE 0x000000001U
172 #define CAN_IER_TIE1 0x000000002U
173 #define CAN_IER_EIE 0x000000004U
174 #define CAN_IER_DOIE 0x000000008U
175 #define CAN_IER_WUIE 0x000000010U
176 #define CAN_IER_EPIEX 0x000000020U
177 #define CAN_IER_ALIEX 0x000000040U
178 #define CAN_IER_BEIEX 0x000000080U
179 #define CAN_IER_IDIEX 0x000000100U
180 #define CAN_IER_TIE2 0x000000200U
181 #define CAN_IER_TIE3 0x000000400U
182 
183 #endif /*LPC176X_TIMER_DEFS_H*/
Represents the CAN controller registers.
Definition: can-defs.h:86
The CAN status and control masks to send a message for each transmit buffer.
Definition: can-defs.h:80
A driver entry for each low level device.
Definition: can-defs.h:111
can_pin_number
A TX or RX pin for each CAN device .
Definition: can-defs.h:102
Definition: rtemscompat1.h:15
#define MSR
Modem Status Register.
Definition: uart.h:93
Represents the CAN centralized registers.
Definition: can-defs.h:120
can_tseg_number
The Time segments of a CAN bit.
Definition: can-defs.h:48
can_format
The possible CAN formats for a message.
Definition: can-defs.h:144
lpc176x_pin_function
Defines the functions according to the pin.
Definition: io-defs.h:68
Definitions types used by some devices in common.
void(* lpc176x_can_isr)(lpc176x_can_number number)
An isr for a CAN interrupt.
Definition: can.h:92
lpc176x_module
lpc176x module representation.
Definition: common-types.h:44
can_type
The types of message.
Definition: can-defs.h:153
can_transmit_number
The transmit buffers of the CAN device.
Definition: can-defs.h:69
#define IER
Interrupt Enable Register.
Definition: uart.h:85
A CAN message represented for the registers of the device.
Definition: can.h:43
CAN controller for the mbed lpc1768 board.
lpc176x_can_isr lpc176x_can_isr_vector[CAN_IRQ_NUMBER]
The vector with all the callbacks for the CAN isr.
Definition: can-defs.h:163
Represents the acceptance filter registers.
Definition: can-defs.h:127