RTEMS
grlib.h
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1 
7 /*
8  * COPYRIGHT (c) 2012
9  * Aeroflex Gaisler
10  *
11  * The license and distribution terms for this file may be
12  * found in the file LICENSE in this distribution or at
13  * http://www.rtems.org/license/LICENSE.
14  */
15 
16 #ifndef __GRLIB_H__
17 #define __GRLIB_H__
18 
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22 
31 /* ESA MEMORY CONTROLLER */
32 struct mctrl_regs {
33  unsigned int mcfg1;
34  unsigned int mcfg2;
35  unsigned int mcfg3;
36 };
37 
38 /* APB UART */
39 struct apbuart_regs {
40  volatile unsigned int data;
41  volatile unsigned int status;
42  volatile unsigned int ctrl;
43  volatile unsigned int scaler;
44 };
45 
46 /* IRQMP and IRQAMP interrupt controller timestamps */
48  volatile unsigned int counter; /* 0x00 */
49  volatile unsigned int control; /* 0x04 */
50  volatile unsigned int assertion; /* 0x08 */
51  volatile unsigned int ack; /* 0x0c */
52 };
53 
54 static inline bool irqmp_has_timestamp(
55  volatile struct irqmp_timestamp_regs *irqmp_ts
56 )
57 {
58  return (irqmp_ts->control >> 27) > 0;
59 }
60 
61 /* IRQMP and IRQAMP interrupt controllers */
62 struct irqmp_regs {
63  volatile unsigned int ilevel; /* 0x00 */
64  volatile unsigned int ipend; /* 0x04 */
65  volatile unsigned int iforce; /* 0x08 */
66  volatile unsigned int iclear; /* 0x0c */
67  volatile unsigned int mpstat; /* 0x10 */
68  volatile unsigned int bcast; /* 0x14 */
69  volatile unsigned int notused02; /* 0x18 */
70  volatile unsigned int wdgctrl; /* 0x1c */
71  volatile unsigned int ampctrl; /* 0x20 */
72  volatile unsigned int icsel[2]; /* 0x24,0x28 */
73  volatile unsigned int notused13; /* 0x2c */
74  volatile unsigned int notused20; /* 0x30 */
75  volatile unsigned int notused21; /* 0x34 */
76  volatile unsigned int notused22; /* 0x38 */
77  volatile unsigned int notused23; /* 0x3c */
78  volatile unsigned int mask[16]; /* 0x40 */
79  volatile unsigned int force[16]; /* 0x80 */
80  /* Extended IRQ registers */
81  volatile unsigned int intid[16]; /* 0xc0 */
82  volatile struct irqmp_timestamp_regs timestamp[16]; /* 0x100 */
83  volatile unsigned int resetaddr[4]; /* 0x200 */
84  volatile unsigned int resv0[12]; /* 0x210 - 0x23C */
85  volatile unsigned int pboot; /* 0x240 */
86  volatile unsigned int resv1[47]; /* 0x244 - 0x2FC */
87  volatile unsigned int irqmap[8]; /* 0x300 - 0x31C */
88  volatile unsigned int resv2[824]; /* 0x320 - 0x1000 */
89 };
90 
91 /* GPTIMER Timer instance */
93  volatile unsigned int value;
94  volatile unsigned int reload;
95  volatile unsigned int ctrl;
96  volatile unsigned int notused;
97 };
98 
99 #define GPTIMER_TIMER_CTRL_EN 0x00000001U
100 #define GPTIMER_TIMER_CTRL_RS 0x00000002U
101 #define GPTIMER_TIMER_CTRL_LD 0x00000004U
102 #define GPTIMER_TIMER_CTRL_IE 0x00000008U
103 #define GPTIMER_TIMER_CTRL_IP 0x00000010U
104 #define GPTIMER_TIMER_CTRL_CH 0x00000020U
105 #define GPTIMER_TIMER_CTRL_DH 0x00000040U
106 
107 /* GPTIMER common registers */
108 struct gptimer_regs {
109  volatile unsigned int scaler_value; /* common timer registers */
110  volatile unsigned int scaler_reload;
111  volatile unsigned int cfg;
112  volatile unsigned int notused;
113  struct gptimer_timer_regs timer[7];
114 };
115 
116 /* GRGPIO GPIO */
117 struct grgpio_regs {
118  volatile unsigned int data; /* 0x00 I/O port data register */
119  volatile unsigned int output; /* 0x04 I/O port output register */
120  volatile unsigned int dir; /* 0x08 I/O port direction register */
121  volatile unsigned int imask; /* 0x0C Interrupt mask register */
122  volatile unsigned int ipol; /* 0x10 Interrupt polarity register */
123  volatile unsigned int iedge; /* 0x14 Interrupt edge register */
124  volatile unsigned int bypass; /* 0x18 Bypass register */
125  volatile unsigned int cap; /* 0x1C Capability register */
126  volatile unsigned int irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */
127  volatile unsigned int res_30; /* 0x30 Reserved */
128  volatile unsigned int res_34; /* 0x34 Reserved */
129  volatile unsigned int res_38; /* 0x38 Reserved */
130  volatile unsigned int res_3C; /* 0x3C Reserved */
131  volatile unsigned int iavail; /* 0x40 Interrupt available register */
132  volatile unsigned int iflag; /* 0x44 Interrupt flag register */
133  volatile unsigned int res_48; /* 0x48 Reserved */
134  volatile unsigned int pulse; /* 0x4C Pulse register */
135  volatile unsigned int res_50; /* 0x50 Reserved */
136  volatile unsigned int output_or; /* 0x54 I/O port output register, logical-OR */
137  volatile unsigned int dir_or; /* 0x58 I/O port direction register, logical-OR */
138  volatile unsigned int imask_or; /* 0x5C Interrupt mask register, logical-OR */
139  volatile unsigned int res_60; /* 0x60 Reserved */
140  volatile unsigned int output_and; /* 0x64 I/O port output register, logical-AND */
141  volatile unsigned int dir_and; /* 0x68 I/O port direction register, logical-AND */
142  volatile unsigned int imask_and; /* 0x6C Interrupt mask register, logical-AND */
143  volatile unsigned int res_70; /* 0x70 Reserved */
144  volatile unsigned int output_xor; /* 0x74 I/O port output register, logical-XOR */
145  volatile unsigned int dir_xor; /* 0x78 I/O port direction register, logical-XOR */
146  volatile unsigned int imask_xor; /* 0x7C Interrupt mask register, logical-XOR */
147 };
148 
149 /* L2C - Level 2 Cache Controller registers */
150 struct l2c_regs {
151  volatile unsigned int control; /* 0x00 Control register */
152  volatile unsigned int status; /* 0x04 Status register */
153  volatile unsigned int flush_mem_addr; /* 0x08 Flush (Memory address) */
154  volatile unsigned int flush_set_index; /* 0x0c Flush (set, index) */
155  volatile unsigned int access_counter; /* 0x10 */
156  volatile unsigned int hit_counter; /* 0x14 */
157  volatile unsigned int bus_cycle_counter; /* 0x18 */
158  volatile unsigned int bus_usage_counter; /* 0x1c */
159  volatile unsigned int error_status_control; /* 0x20 Error status/control */
160  volatile unsigned int error_addr; /* 0x24 Error address */
161  volatile unsigned int tag_check_bit; /* 0x28 TAG-check-bit */
162  volatile unsigned int data_check_bit; /* 0x2c Data-check-bit */
163  volatile unsigned int scrub_control_status; /* 0x30 Scrub Control/Status */
164  volatile unsigned int scrub_delay; /* 0x34 Scrub Delay */
165  volatile unsigned int error_injection; /* 0x38 Error injection */
166  volatile unsigned int access_control; /* 0x3c Access control */
167  volatile unsigned int reserved_40[16]; /* 0x40 Reserved */
168  volatile unsigned int mtrr[32]; /* 0x80 - 0xFC MTRR registers */
169  volatile unsigned int reserved_100[131008]; /* 0x100 Reserved */
170  volatile unsigned int diag_iface_tag[16384]; /* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */
171  volatile unsigned int reserved_90000[376832]; /* 0x90000 Reserved */
172  volatile unsigned int diag_iface_data[524288];/* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */
173 };
174 
175 #ifdef __cplusplus
176 }
177 #endif
178 
179 #endif