86 #if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) 91 #if CPU_DATA_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES 92 #error "CPU_DATA_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES" 95 #if CPU_INSTRUCTION_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES 96 #error "CPU_INSTRUCTION_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES" 111 #if defined(CPU_DATA_CACHE_ALIGNMENT) 112 #if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) 113 _CPU_cache_flush_data_range( d_addr, n_bytes );
115 const void * final_address;
127 final_address = (
void *)((
size_t)d_addr + n_bytes - 1);
128 d_addr = (
void *)((
size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
129 while( d_addr <= final_address ) {
130 _CPU_cache_flush_1_data_line( d_addr );
131 d_addr = (
void *)((
size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
145 #if defined(CPU_DATA_CACHE_ALIGNMENT) 146 #if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) 147 _CPU_cache_invalidate_data_range( d_addr, n_bytes );
149 const void * final_address;
161 final_address = (
void *)((
size_t)d_addr + n_bytes - 1);
162 d_addr = (
void *)((
size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
163 while( final_address >= d_addr ) {
164 _CPU_cache_invalidate_1_data_line( d_addr );
165 d_addr = (
void *)((
size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
178 #if defined(CPU_DATA_CACHE_ALIGNMENT) 182 _CPU_cache_flush_entire_data();
193 #if defined(CPU_DATA_CACHE_ALIGNMENT) 198 _CPU_cache_invalidate_entire_data();
208 #if defined(CPU_DATA_CACHE_ALIGNMENT) 209 return CPU_DATA_CACHE_ALIGNMENT;
218 #if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS) 219 return _CPU_cache_get_data_cache_size( level );
232 #if defined(CPU_DATA_CACHE_ALIGNMENT) 233 _CPU_cache_freeze_data();
239 #if defined(CPU_DATA_CACHE_ALIGNMENT) 240 _CPU_cache_unfreeze_data();
247 #if defined(CPU_DATA_CACHE_ALIGNMENT) 248 _CPU_cache_enable_data();
252 #if !defined(CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA) 256 #if defined(CPU_DATA_CACHE_ALIGNMENT) 257 _CPU_cache_disable_data();
266 #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \ 267 && defined(RTEMS_SMP) \ 268 && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) 275 static void smp_cache_inst_inv(
void *arg)
277 smp_cache_area *area = arg;
279 _CPU_cache_invalidate_instruction_range(area->addr, area->size);
282 static void smp_cache_inst_inv_all(
void *arg)
284 _CPU_cache_invalidate_entire_instruction();
287 static void smp_cache_broadcast( SMP_Action_handler handler,
void *arg )
294 if ( isr_level == 0 ) {
297 cpu_self = _Per_CPU_Get();
302 if ( isr_level == 0 ) {
314 #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \ 315 && !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) 317 _CPU_cache_invalidate_instruction_range(
322 const void * final_address;
334 final_address = (
void *)((
size_t)i_addr + n_bytes - 1);
335 i_addr = (
void *)((
size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1));
336 while( final_address >= i_addr ) {
337 _CPU_cache_invalidate_1_instruction_line( i_addr );
338 i_addr = (
void *)((
size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT);
349 #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) 350 #if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) 351 smp_cache_area area = { i_addr, n_bytes };
353 smp_cache_broadcast( smp_cache_inst_inv, &area );
355 _CPU_cache_invalidate_instruction_range( i_addr, n_bytes );
367 #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) 368 #if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) 369 smp_cache_broadcast( smp_cache_inst_inv_all, NULL );
371 _CPU_cache_invalidate_entire_instruction();
382 #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) 383 return CPU_INSTRUCTION_CACHE_ALIGNMENT;
392 #if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS) 393 return _CPU_cache_get_instruction_cache_size( level );
406 #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) 407 _CPU_cache_freeze_instruction();
413 #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) 414 _CPU_cache_unfreeze_instruction();
421 #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) 422 _CPU_cache_enable_instruction();
429 #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) 430 _CPU_cache_disable_instruction();
437 #if defined(CPU_MAXIMAL_CACHE_ALIGNMENT) 438 return CPU_MAXIMAL_CACHE_ALIGNMENT;
440 size_t max_line_size = 0;
441 #if defined(CPU_DATA_CACHE_ALIGNMENT) 443 size_t data_line_size = CPU_DATA_CACHE_ALIGNMENT;
444 if ( max_line_size < data_line_size )
445 max_line_size = data_line_size;
448 #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) 450 size_t instruction_line_size = CPU_INSTRUCTION_CACHE_ALIGNMENT;
451 if ( max_line_size < instruction_line_size )
452 max_line_size = instruction_line_size;
455 return max_line_size;
466 const void *code_addr,
470 #if defined(CPU_CACHE_SUPPORT_PROVIDES_INSTRUCTION_SYNC_FUNCTION) 471 _CPU_cache_instruction_sync_after_code_change( code_addr, n_bytes );
void rtems_cache_invalidate_multiple_instruction_lines(const void *i_addr, size_t n_bytes)
%
size_t rtems_cache_get_data_cache_size(uint32_t level)
%
Constants and Structures Related with Thread Dispatch.
size_t rtems_cache_get_maximal_line_size(void)
%
size_t rtems_cache_get_instruction_line_size(void)
%
void rtems_cache_instruction_sync_after_code_change(const void *code_addr, size_t n_bytes)
%
void rtems_cache_disable_instruction(void)
%
void rtems_cache_unfreeze_data(void)
%
size_t rtems_cache_get_instruction_cache_size(uint32_t level)
%
#define _ISR_Get_level()
Return current interrupt level.
void rtems_cache_flush_entire_data(void)
%
void rtems_cache_freeze_data(void)
%
void rtems_cache_enable_data(void)
%
void rtems_cache_invalidate_entire_data(void)
%
void rtems_cache_invalidate_multiple_data_lines(const void *d_addr, size_t n_bytes)
%
void _Thread_Dispatch_enable(Per_CPU_Control *cpu_self)
Enables thread dispatching.
This header file defines the RTEMS Classic API.
static __inline__ Per_CPU_Control * _Thread_Dispatch_disable(void)
Disables thread dispatching.
size_t rtems_cache_get_data_line_size(void)
%
void rtems_cache_unfreeze_instruction(void)
%
void rtems_cache_freeze_instruction(void)
%
void rtems_cache_invalidate_entire_instruction(void)
%
void _SMP_Broadcast_action(SMP_Action_handler handler, void *arg)
Initiates an SMP multicast action to the set of all online processors.
void rtems_cache_disable_data(void)
%
void rtems_cache_enable_instruction(void)
%
SuperCore SMP Implementation.
void rtems_cache_flush_multiple_data_lines(const void *d_addr, size_t n_bytes)
%