32#ifndef STM32H7xx_LL_UTILS_H
33#define STM32H7xx_LL_UTILS_H
63#define LL_MAX_DELAY 0xFFFFFFFFU
68#define UID_BASE_ADDRESS UID_BASE
73#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
78#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
198#define LL_UTILS_HSEBYPASS_OFF 0x00000000U
199#define LL_UTILS_HSEBYPASS_ON 0x00000001U
208#if (STM32H7_DEV_ID == 0x450UL)
209#define LL_UTILS_PACKAGETYPE_LQFP100 LL_SYSCFG_LQFP100_PACKAGE
210#define LL_UTILS_PACKAGETYPE_TQFP144 LL_SYSCFG_TQFP144_PACKAGE
211#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 LL_SYSCFG_TQFP176_UFBGA176_PACKAGE
212#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 LL_SYSCFG_LQFP208_TFBGA240_PACKAGE
213#elif (STM32H7_DEV_ID == 0x480UL)
214#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000UL
215#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 0x00000001UL
216#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x00000002UL
217#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS 0x00000003UL
218#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS 0x00000004UL
219#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL
220#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL
221#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL
222#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000008UL
223#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000009UL
224#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000AUL
225#define LL_UTILS_PACKAGETYPE_TFBGA216 0x0000000CUL
226#define LL_UTILS_PACKAGETYPE_TFBGA225 0x0000000EUL
227#elif (STM32H7_DEV_ID == 0x483UL)
228#define LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS LL_SYSCFG_VFQFPN68_INDUS_PACKAGE
229#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 LL_SYSCFG_TFBGA100_LQFP100_PACKAGE
230#define LL_UTILS_PACKAGETYPE_LQFP100_INDUS LL_SYSCFG_LQFP100_INDUS_PACKAGE
231#define LL_UTILS_PACKAGETYPE_TFBGA100_INDUS LL_SYSCFG_TFBGA100_INDUS_PACKAGE
232#define LL_UTILS_PACKAGETYPE_WLCSP115_INDUS LL_SYSCFG_WLCSP115_INDUS_PACKAGE
233#define LL_UTILS_PACKAGETYPE_LQFP144 LL_SYSCFG_LQFP144_PACKAGE
234#define LL_UTILS_PACKAGETYPE_UFBGA144 LL_SYSCFG_UFBGA144_PACKAGE
235#define LL_UTILS_PACKAGETYPE_LQFP144_INDUS LL_SYSCFG_LQFP144_INDUS_PACKAGE
236#define LL_UTILS_PACKAGETYPE_UFBGA169_INDUS LL_SYSCFG_UFBGA169_INDUS_PACKAGE
237#define LL_UTILS_PACKAGETYPE_UFBGA176PLUS25_INDUS LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE
238#define LL_UTILS_PACKAGETYPE_LQFP176_INDUS LL_SYSCFG_LQFP176_INDUS_PACKAGE
335#if defined(SYSCFG_PKGR_PKG)
337 return LL_SYSCFG_GetPackage();
361__STATIC_INLINE
void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
364 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL);
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm4.h:795
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm4.h:789
#define SysTick
Definition: core_cm4.h:1573
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
Get Flash memory size.
Definition: stm32h7xx_ll_utils.h:294
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
Get Word0 of the unique device identifier (UID based on 96 bits)
Definition: stm32h7xx_ll_utils.h:265
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
Get Word1 of the unique device identifier (UID based on 96 bits)
Definition: stm32h7xx_ll_utils.h:274
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
Get Word2 of the unique device identifier (UID based on 96 bits)
Definition: stm32h7xx_ll_utils.h:283
__STATIC_INLINE uint32_t LL_GetPackageType(void)
Get Package type.
Definition: stm32h7xx_ll_utils.h:333
void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
This function sets directly SystemCoreClock CMSIS variable.
Definition: stm32h7xx_ll_utils.c:475
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
Update number of Flash wait states in line with new frequency and current voltage range.
Definition: stm32h7xx_ll_utils.c:692
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
Definition: stm32h7xx_ll_utils.c:502
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.
Definition: stm32h7xx_ll_utils.c:598
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.
Definition: stm32h7xx_ll_utils.h:361
void LL_mDelay(uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
Definition: stm32h7xx_ll_utils.c:307
void LL_Init1msTick(uint32_t CPU_Frequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
Definition: stm32h7xx_ll_utils.c:290
#define UID_BASE_ADDRESS
Unique device ID register base address.
Definition: stm32h7xx_ll_utils.h:68
#define FLASHSIZE_BASE_ADDRESS
Flash size data register base address.
Definition: stm32h7xx_ll_utils.h:73
#define PACKAGE_BASE_ADDRESS
Package data register base address.
Definition: stm32h7xx_ll_utils.h:78
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
Header file of BUS LL module.
Header file of SYSTEM LL module.
UTILS System, AHB and APB buses clock configuration structure definition.
Definition: stm32h7xx_ll_utils.h:145
uint32_t SYSCLKDivider
Definition: stm32h7xx_ll_utils.h:146
uint32_t APB1CLKDivider
Definition: stm32h7xx_ll_utils.h:158
uint32_t APB2CLKDivider
Definition: stm32h7xx_ll_utils.h:164
uint32_t APB4CLKDivider
Definition: stm32h7xx_ll_utils.h:176
uint32_t AHBCLKDivider
Definition: stm32h7xx_ll_utils.h:152
uint32_t APB3CLKDivider
Definition: stm32h7xx_ll_utils.h:170
UTILS PLL structure definition.
Definition: stm32h7xx_ll_utils.h:101
uint32_t PLLP
Definition: stm32h7xx_ll_utils.h:114
uint32_t PLLM
Definition: stm32h7xx_ll_utils.h:102
uint32_t VCO_Output
Definition: stm32h7xx_ll_utils.h:133
uint32_t FRACN
Definition: stm32h7xx_ll_utils.h:121
uint32_t VCO_Input
Definition: stm32h7xx_ll_utils.h:127
uint32_t PLLN
Definition: stm32h7xx_ll_utils.h:108