20#ifndef STM32H7xx_LL_USB_H
21#define STM32H7xx_LL_USB_H
30#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
40#ifndef HAL_USB_TIMEOUT
41#define HAL_USB_TIMEOUT 0xF000000U
44#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS
45#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U
95 uint8_t dev_endpoints;
99 uint8_t Host_channels;
117 uint8_t low_power_enable;
121 uint8_t battery_charging_enable;
123 uint8_t vbus_sensing_enable;
125 uint8_t use_dedicated_ep1;
127 uint8_t use_external_vbus;
142 uint8_t is_iso_incomplete;
148 uint8_t data_pid_start;
160 uint8_t even_odd_frame;
163 uint16_t tx_fifo_num;
192 uint8_t ep_ss_schedule;
193 uint32_t iso_splt_xactPos;
195 uint8_t hub_port_nbr;
226 USB_URBStateTypeDef urb_state;
229 USB_HCStateTypeDef state;
233typedef USB_ModeTypeDef USB_OTG_ModeTypeDef;
234typedef USB_CfgTypeDef USB_OTG_CfgTypeDef;
235typedef USB_EPTypeDef USB_OTG_EPTypeDef;
236typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef;
237typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef;
238typedef USB_HCTypeDef USB_OTG_HCTypeDef;
247#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
252#define USB_OTG_CORE_ID_300A 0x4F54300AU
253#define USB_OTG_CORE_ID_310A 0x4F54310AU
262#define USB_OTG_MODE_DEVICE 0U
263#define USB_OTG_MODE_HOST 1U
264#define USB_OTG_MODE_DRD 2U
273#define USB_OTG_SPEED_HIGH 0U
274#define USB_OTG_SPEED_HIGH_IN_FULL 1U
275#define USB_OTG_SPEED_FULL 3U
284#define USB_OTG_ULPI_PHY 1U
285#define USB_OTG_EMBEDDED_PHY 2U
294#ifndef USBD_HS_TRDT_VALUE
295#define USBD_HS_TRDT_VALUE 9U
297#ifndef USBD_FS_TRDT_VALUE
298#define USBD_FS_TRDT_VALUE 5U
299#define USBD_DEFAULT_TRDT_VALUE 9U
309#define USB_OTG_HS_MAX_PACKET_SIZE 512U
310#define USB_OTG_FS_MAX_PACKET_SIZE 64U
311#define USB_OTG_MAX_EP0_SIZE 64U
320#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
321#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
322#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
331#define DCFG_FRAME_INTERVAL_80 0U
332#define DCFG_FRAME_INTERVAL_85 1U
333#define DCFG_FRAME_INTERVAL_90 2U
334#define DCFG_FRAME_INTERVAL_95 3U
355#define EP_TYPE_CTRL 0U
356#define EP_TYPE_ISOC 1U
357#define EP_TYPE_BULK 2U
358#define EP_TYPE_INTR 3U
359#define EP_TYPE_MSK 3U
368#define EP_SPEED_LOW 0U
369#define EP_SPEED_FULL 1U
370#define EP_SPEED_HIGH 2U
379#define HC_PID_DATA0 0U
380#define HC_PID_DATA2 1U
381#define HC_PID_DATA1 2U
382#define HC_PID_SETUP 3U
391#define USBD_HS_SPEED 0U
392#define USBD_HSINFS_SPEED 1U
393#define USBH_HS_SPEED 0U
394#define USBD_FS_SPEED 2U
395#define USBH_FSLS_SPEED 1U
400#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
405#define STS_GOUT_NAK 1U
406#define STS_DATA_UPDT 2U
407#define STS_XFER_COMP 3U
408#define STS_SETUP_COMP 4U
409#define STS_SETUP_UPDT 6U
418#define HCFG_30_60_MHZ 0U
419#define HCFG_48_MHZ 1U
429#define HFIR_6_MHZ 6000U
430#define HFIR_60_MHZ 60000U
431#define HFIR_48_MHZ 48000U
440#define HPRT0_PRTSPD_HIGH_SPEED 0U
441#define HPRT0_PRTSPD_FULL_SPEED 1U
442#define HPRT0_PRTSPD_LOW_SPEED 2U
447#define HCCHAR_CTRL 0U
448#define HCCHAR_ISOC 1U
449#define HCCHAR_BULK 2U
450#define HCCHAR_INTR 3U
452#define GRXSTS_PKTSTS_IN 2U
453#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
454#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
455#define GRXSTS_PKTSTS_CH_HALTED 7U
457#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU
459#define HC_MAX_PKT_CNT 256U
460#define ISO_SPLT_MPS 188U
462#define HCSPLT_BEGIN 1U
463#define HCSPLT_MIDDLE 2U
465#define HCSPLT_FULL 4U
469#define TEST_SE0_NAK 3U
470#define TEST_PACKET 4U
471#define TEST_FORCE_EN 5U
473#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
474#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
476#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
477#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
478 + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
480#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
481 + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
483#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
485#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
486#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
487 + USB_OTG_HOST_CHANNEL_BASE\
488 + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
491#define EP_ADDR_MSK 0xFU
502#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
503#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
504#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
506#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
507#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
517#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
533 uint8_t ch_ep_num, uint16_t len, uint8_t dma);
562 uint8_t epnum, uint8_t dev_address, uint8_t speed,
563 uint8_t ep_type, uint16_t mps);
565 USB_OTG_HCTypeDef *hc, uint8_t dma);
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
USB_OTG_Core_Registers.
Definition: stm32h723xx.h:1761