Semc

Data Structures
struct	_semc_sdram_config
	SEMC SDRAM configuration structure. More...
struct	_semc_nand_timing_config
	SEMC NAND device timing configuration structure. More...
struct	_semc_nand_config
	SEMC NAND configuration structure. More...
struct	_semc_nor_config
	SEMC NOR configuration structure. More...
struct	_semc_sram_config
	SEMC SRAM configuration structure. More...
struct	_semc_dbi_config
	SEMC DBI configuration structure. More...
struct	_semc_queuea_weight_struct
	SEMC AXI queue a weight setting structure. More...
union	_semc_queuea_weight
	SEMC AXI queue a weight setting union. More...
struct	_semc_queueb_weight_struct
	SEMC AXI queue b weight setting structure. More...
union	_semc_queueb_weight
	SEMC AXI queue b weight setting union. More...
struct	_semc_axi_queueweight
	SEMC AXI queue weight setting. More...
struct	_semc_config_t
	SEMC configuration structure. More...

Variables
semc_iomux_pin	_semc_sdram_config::csxPinMux
uint32_t	_semc_sdram_config::address
uint32_t	_semc_sdram_config::memsize_kbytes
smec_port_size_t	_semc_sdram_config::portSize
sem_sdram_burst_len_t	_semc_sdram_config::burstLen
semc_sdram_column_bit_num_t	_semc_sdram_config::columnAddrBitNum
semc_caslatency_t	_semc_sdram_config::casLatency
uint8_t	_semc_sdram_config::tPrecharge2Act_Ns
uint8_t	_semc_sdram_config::tAct2ReadWrite_Ns
uint8_t	_semc_sdram_config::tRefreshRecovery_Ns
uint8_t	_semc_sdram_config::tWriteRecovery_Ns
uint8_t	_semc_sdram_config::tCkeOff_Ns
uint8_t	_semc_sdram_config::tAct2Prechage_Ns
uint8_t	_semc_sdram_config::tSelfRefRecovery_Ns
uint8_t	_semc_sdram_config::tRefresh2Refresh_Ns
uint8_t	_semc_sdram_config::tAct2Act_Ns
uint32_t	_semc_sdram_config::tPrescalePeriod_Ns
uint32_t	_semc_sdram_config::tIdleTimeout_Ns
uint32_t	_semc_sdram_config::refreshPeriod_nsPerRow
uint32_t	_semc_sdram_config::refreshUrgThreshold
uint8_t	_semc_sdram_config::refreshBurstLen
uint8_t	_semc_nand_timing_config::tCeSetup_Ns
uint8_t	_semc_nand_timing_config::tCeHold_Ns
uint8_t	_semc_nand_timing_config::tCeInterval_Ns
uint8_t	_semc_nand_timing_config::tWeLow_Ns
uint8_t	_semc_nand_timing_config::tWeHigh_Ns
uint8_t	_semc_nand_timing_config::tReLow_Ns
uint8_t	_semc_nand_timing_config::tReHigh_Ns
uint8_t	_semc_nand_timing_config::tTurnAround_Ns
uint8_t	_semc_nand_timing_config::tWehigh2Relow_Ns
uint8_t	_semc_nand_timing_config::tRehigh2Welow_Ns
uint8_t	_semc_nand_timing_config::tAle2WriteStart_Ns
uint8_t	_semc_nand_timing_config::tReady2Relow_Ns
uint8_t	_semc_nand_timing_config::tWehigh2Busy_Ns
semc_iomux_pin	_semc_nand_config::cePinMux
uint32_t	_semc_nand_config::axiAddress
uint32_t	_semc_nand_config::axiMemsize_kbytes
uint32_t	_semc_nand_config::ipgAddress
uint32_t	_semc_nand_config::ipgMemsize_kbytes
semc_rdy_polarity_t	_semc_nand_config::rdyactivePolarity
bool	_semc_nand_config::edoModeEnabled
semc_nand_column_bit_num_t	_semc_nand_config::columnAddrBitNum
semc_nand_address_option_t	_semc_nand_config::arrayAddrOption
sem_nand_burst_len_t	_semc_nand_config::burstLen
smec_port_size_t	_semc_nand_config::portSize
semc_nand_timing_config_t *	_semc_nand_config::timingConfig
semc_iomux_pin	_semc_nor_config::cePinMux
semc_iomux_nora27_pin	_semc_nor_config::addr27
uint32_t	_semc_nor_config::address
uint32_t	_semc_nor_config::memsize_kbytes
uint8_t	_semc_nor_config::addrPortWidth
semc_rdy_polarity_t	_semc_nor_config::rdyactivePolarity
semc_adv_polarity_t	_semc_nor_config::advActivePolarity
semc_norsram_column_bit_num_t	_semc_nor_config::columnAddrBitNum
semc_addr_mode_t	_semc_nor_config::addrMode
sem_norsram_burst_len_t	_semc_nor_config::burstLen
smec_port_size_t	_semc_nor_config::portSize
uint8_t	_semc_nor_config::tCeSetup_Ns
uint8_t	_semc_nor_config::tCeHold_Ns
uint8_t	_semc_nor_config::tCeInterval_Ns
uint8_t	_semc_nor_config::tAddrSetup_Ns
uint8_t	_semc_nor_config::tAddrHold_Ns
uint8_t	_semc_nor_config::tWeLow_Ns
uint8_t	_semc_nor_config::tWeHigh_Ns
uint8_t	_semc_nor_config::tReLow_Ns
uint8_t	_semc_nor_config::tReHigh_Ns
uint8_t	_semc_nor_config::tTurnAround_Ns
uint8_t	_semc_nor_config::tAddr2WriteHold_Ns
semc_iomux_pin	_semc_sram_config::cePinMux
semc_iomux_nora27_pin	_semc_sram_config::addr27
uint32_t	_semc_sram_config::address
uint32_t	_semc_sram_config::memsize_kbytes
uint8_t	_semc_sram_config::addrPortWidth
semc_adv_polarity_t	_semc_sram_config::advActivePolarity
semc_addr_mode_t	_semc_sram_config::addrMode
sem_norsram_burst_len_t	_semc_sram_config::burstLen
smec_port_size_t	_semc_sram_config::portSize
uint8_t	_semc_sram_config::tCeSetup_Ns
uint8_t	_semc_sram_config::tCeHold_Ns
uint8_t	_semc_sram_config::tCeInterval_Ns
uint8_t	_semc_sram_config::tAddrSetup_Ns
uint8_t	_semc_sram_config::tAddrHold_Ns
uint8_t	_semc_sram_config::tWeLow_Ns
uint8_t	_semc_sram_config::tWeHigh_Ns
uint8_t	_semc_sram_config::tReLow_Ns
uint8_t	_semc_sram_config::tReHigh_Ns
uint8_t	_semc_sram_config::tTurnAround_Ns
uint8_t	_semc_sram_config::tAddr2WriteHold_Ns
semc_iomux_pin	_semc_dbi_config::csxPinMux
uint32_t	_semc_dbi_config::address
uint32_t	_semc_dbi_config::memsize_kbytes
semc_dbi_column_bit_num_t	_semc_dbi_config::columnAddrBitNum
sem_dbi_burst_len_t	_semc_dbi_config::burstLen
smec_port_size_t	_semc_dbi_config::portSize
uint8_t	_semc_dbi_config::tCsxSetup_Ns
uint8_t	_semc_dbi_config::tCsxHold_Ns
uint8_t	_semc_dbi_config::tWexLow_Ns
uint8_t	_semc_dbi_config::tWexHigh_Ns
uint8_t	_semc_dbi_config::tRdxLow_Ns
uint8_t	_semc_dbi_config::tRdxHigh_Ns
uint8_t	_semc_dbi_config::tCsxInterval_Ns
uint32_t	_semc_queuea_weight_struct::qos: 4
uint32_t	_semc_queuea_weight_struct::aging: 4
uint32_t	_semc_queuea_weight_struct::slaveHitSwith: 8
uint32_t	_semc_queuea_weight_struct::slaveHitNoswitch: 8
semc_queuea_weight_struct_t	_semc_queuea_weight::queueaConfig
uint32_t	_semc_queuea_weight::queueaValue
uint32_t	_semc_queueb_weight_struct::qos: 4
uint32_t	_semc_queueb_weight_struct::aging: 4
uint32_t	_semc_queueb_weight_struct::slaveHitSwith: 8
uint32_t	_semc_queueb_weight_struct::weightPagehit: 8
uint32_t	_semc_queueb_weight_struct::bankRotation: 8
semc_queueb_weight_struct_t	_semc_queueb_weight::queuebConfig
uint32_t	_semc_queueb_weight::queuebValue
bool	_semc_axi_queueweight::queueaEnable
semc_queuea_weight_t	_semc_axi_queueweight::queueaWeight
bool	_semc_axi_queueweight::queuebEnable
semc_queueb_weight_t	_semc_axi_queueweight::queuebWeight
semc_dqs_mode_t	_semc_config_t::dqsMode
uint8_t	_semc_config_t::cmdTimeoutCycles
uint8_t	_semc_config_t::busTimeoutCycles
semc_axi_queueweight_t	_semc_config_t::queueWeight

Driver version
enum	{   kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0) , kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1) , kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2) , kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3) ,   kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4) , kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5) , kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6) , kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7) ,   kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8) , kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9) , kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10) , kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11) }
	SEMC status, _semc_status. More...
enum	_semc_mem_type {   kSEMC_MemType_SDRAM = 0 , kSEMC_MemType_SRAM , kSEMC_MemType_NOR , kSEMC_MemType_NAND ,   kSEMC_MemType_8080 }
	SEMC memory device type. More...
enum	_semc_waitready_polarity { kSEMC_LowActive = 0 , kSEMC_HighActive }
	SEMC WAIT/RDY polarity. More...
enum	_semc_sdram_cs { kSEMC_SDRAM_CS0 = 0 , kSEMC_SDRAM_CS1 , kSEMC_SDRAM_CS2 , kSEMC_SDRAM_CS3 }
	SEMC SDRAM Chip selection . More...
enum	_semc_sram_cs { kSEMC_SRAM_CS0 = 0 }
	SEMC SRAM Chip selection . More...
enum	_semc_nand_access_type { kSEMC_NAND_ACCESS_BY_AXI = 0 , kSEMC_NAND_ACCESS_BY_IPCMD }
	SEMC NAND device type. More...
enum	_semc_interrupt_enable { kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK , kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK , kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK , kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK }
	SEMC interrupts . More...
enum	_semc_ipcmd_datasize { kSEMC_IPcmdDataSize_1bytes = 1 , kSEMC_IPcmdDataSize_2bytes , kSEMC_IPcmdDataSize_3bytes , kSEMC_IPcmdDataSize_4bytes }
	SEMC IP command data size in bytes. More...
enum	_semc_refresh_time { kSEMC_RefreshThreeClocks = 0x0U , kSEMC_RefreshSixClocks , kSEMC_RefreshNineClocks }
	SEMC auto-refresh timing. More...
enum	_semc_caslatency { kSEMC_LatencyOne = 1 , kSEMC_LatencyTwo , kSEMC_LatencyThree }
	CAS latency. More...
enum	_semc_sdram_column_bit_num { kSEMC_SdramColunm_12bit = 0x0U , kSEMC_SdramColunm_11bit , kSEMC_SdramColunm_10bit , kSEMC_SdramColunm_9bit }
	SEMC sdram column address bit number. More...
enum	_semc_sdram_burst_len { kSEMC_Sdram_BurstLen1 = 0 , kSEMC_Sdram_BurstLen2 , kSEMC_Sdram_BurstLen4 , kSEMC_Sdram_BurstLen8 }
	SEMC sdram burst length. More...
enum	_semc_nand_column_bit_num {   kSEMC_NandColum_16bit = 0x0U , kSEMC_NandColum_15bit , kSEMC_NandColum_14bit , kSEMC_NandColum_13bit ,   kSEMC_NandColum_12bit , kSEMC_NandColum_11bit , kSEMC_NandColum_10bit , kSEMC_NandColum_9bit }
	SEMC nand column address bit number. More...
enum	_semc_nand_burst_len {   kSEMC_Nand_BurstLen1 = 0 , kSEMC_Nand_BurstLen2 , kSEMC_Nand_BurstLen4 , kSEMC_Nand_BurstLen8 ,   kSEMC_Nand_BurstLen16 , kSEMC_Nand_BurstLen32 , kSEMC_Nand_BurstLen64 }
	SEMC nand burst length. More...
enum	_semc_norsram_column_bit_num {   kSEMC_NorColum_12bit = 0x0U , kSEMC_NorColum_11bit , kSEMC_NorColum_10bit , kSEMC_NorColum_9bit ,   kSEMC_NorColum_8bit , kSEMC_NorColum_7bit , kSEMC_NorColum_6bit , kSEMC_NorColum_5bit ,   kSEMC_NorColum_4bit , kSEMC_NorColum_3bit , kSEMC_NorColum_2bit }
	SEMC nor/sram column address bit number. More...
enum	_semc_norsram_burst_len {   kSEMC_Nor_BurstLen1 = 0 , kSEMC_Nor_BurstLen2 , kSEMC_Nor_BurstLen4 , kSEMC_Nor_BurstLen8 ,   kSEMC_Nor_BurstLen16 , kSEMC_Nor_BurstLen32 , kSEMC_Nor_BurstLen64 }
	SEMC nor/sram burst length. More...
enum	_semc_dbi_column_bit_num {   kSEMC_Dbi_Colum_12bit = 0x0U , kSEMC_Dbi_Colum_11bit , kSEMC_Dbi_Colum_10bit , kSEMC_Dbi_Colum_9bit ,   kSEMC_Dbi_Colum_8bit , kSEMC_Dbi_Colum_7bit , kSEMC_Dbi_Colum_6bit , kSEMC_Dbi_Colum_5bit ,   kSEMC_Dbi_Colum_4bit , kSEMC_Dbi_Colum_3bit , kSEMC_Dbi_Colum_2bit }
	SEMC dbi column address bit number. More...
enum	_semc_dbi_burst_len {   kSEMC_Dbi_BurstLen1 = 0 , kSEMC_Dbi_BurstLen2 , kSEMC_Dbi_Dbi_BurstLen4 , kSEMC_Dbi_BurstLen8 ,   kSEMC_Dbi_BurstLen16 , kSEMC_Dbi_BurstLen32 , kSEMC_Dbi_BurstLen64 }
	SEMC dbi burst length. More...
enum	_semc_iomux_pin {   kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT , kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT , kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT , kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT ,   kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT , kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT }
	SEMC IOMUXC. More...
enum	_semc_iomux_nora27_pin { kSEMC_MORA27_NONE = 0 , kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT , kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT }
	SEMC NOR/PSRAM Address bit 27 A27. More...
enum	_semc_port_size { kSEMC_PortSize8Bit = 0 , kSEMC_PortSize16Bit }
	SEMC port size. More...
enum	_semc_addr_mode { kSEMC_AddrDataMux = 0 , kSEMC_AdvAddrdataMux , kSEMC_AddrDataNonMux }
	SEMC address mode. More...
enum	_semc_dqs_mode { kSEMC_Loopbackinternal = 0 , kSEMC_Loopbackdqspad }
	SEMC DQS read strobe mode. More...
enum	_semc_adv_polarity { kSEMC_AdvActiveLow = 0 , kSEMC_AdvActiveHigh }
	SEMC ADV signal active polarity. More...
enum	_semc_sync_mode { kSEMC_AsyncMode = 0 , kSEMC_SyncMode }
	SEMC sync mode. More...
enum	_semc_adv_level_control { kSEMC_AdvHigh = 0 , kSEMC_AdvLow }
	SEMC ADV signal level control. More...
enum	_semc_rdy_polarity { kSEMC_RdyActiveLow = 0 , kSEMC_RdyActivehigh }
	SEMC RDY signal active polarity. More...
enum	_semc_ipcmd_nand_addrmode {   kSEMC_NANDAM_ColumnRow = 0x0U , kSEMC_NANDAM_ColumnCA0 , kSEMC_NANDAM_ColumnCA0CA1 , kSEMC_NANDAM_RawRA0 ,   kSEMC_NANDAM_RawRA0RA1 , kSEMC_NANDAM_RawRA0RA1RA2 }
	SEMC IP command for NAND: address mode. More...
enum	_semc_ipcmd_nand_cmdmode {   kSEMC_NANDCM_Command = 0x2U , kSEMC_NANDCM_CommandHold , kSEMC_NANDCM_CommandAddress , kSEMC_NANDCM_CommandAddressHold ,   kSEMC_NANDCM_CommandAddressRead , kSEMC_NANDCM_CommandAddressWrite , kSEMC_NANDCM_CommandRead , kSEMC_NANDCM_CommandWrite ,   kSEMC_NANDCM_Read , kSEMC_NANDCM_Write }
	SEMC IP command for NAND： command mode. More...
enum	_semc_nand_address_option {   kSEMC_NandAddrOption_5byte_CA2RA3 = 0U , kSEMC_NandAddrOption_4byte_CA2RA2 = 2U , kSEMC_NandAddrOption_3byte_CA2RA1 = 4U , kSEMC_NandAddrOption_4byte_CA1RA3 = 1U ,   kSEMC_NandAddrOption_3byte_CA1RA2 = 3U , kSEMC_NandAddrOption_2byte_CA1RA1 = 7U }
	SEMC NAND address option. More...
enum	_semc_ipcmd_nor_dbi { kSEMC_NORDBICM_Read = 0x2U , kSEMC_NORDBICM_Write }
	SEMC IP command for NOR. More...
enum	_semc_ipcmd_sram { kSEMC_SRAMCM_ArrayRead = 0x2U , kSEMC_SRAMCM_ArrayWrite , kSEMC_SRAMCM_RegRead , kSEMC_SRAMCM_RegWrite }
	SEMC IP command for SRAM. More...
enum	_semc_ipcmd_sdram {   kSEMC_SDRAMCM_Read = 0x8U , kSEMC_SDRAMCM_Write , kSEMC_SDRAMCM_Modeset , kSEMC_SDRAMCM_Active ,   kSEMC_SDRAMCM_AutoRefresh , kSEMC_SDRAMCM_SelfRefresh , kSEMC_SDRAMCM_Precharge , kSEMC_SDRAMCM_Prechargeall }
	SEMC IP command for SDARM. More...
typedef enum _semc_mem_type	semc_mem_type_t
	SEMC memory device type.
typedef enum _semc_waitready_polarity	semc_waitready_polarity_t
	SEMC WAIT/RDY polarity.
typedef enum _semc_sdram_cs	semc_sdram_cs_t
	SEMC SDRAM Chip selection .
typedef enum _semc_sram_cs	semc_sram_cs_t
	SEMC SRAM Chip selection .
typedef enum _semc_nand_access_type	semc_nand_access_type_t
	SEMC NAND device type.
typedef enum _semc_interrupt_enable	semc_interrupt_enable_t
	SEMC interrupts .
typedef enum _semc_ipcmd_datasize	semc_ipcmd_datasize_t
	SEMC IP command data size in bytes.
typedef enum _semc_refresh_time	semc_refresh_time_t
	SEMC auto-refresh timing.
typedef enum _semc_caslatency	semc_caslatency_t
	CAS latency.
typedef enum _semc_sdram_column_bit_num	semc_sdram_column_bit_num_t
	SEMC sdram column address bit number.
typedef enum _semc_sdram_burst_len	sem_sdram_burst_len_t
	SEMC sdram burst length.
typedef enum _semc_nand_column_bit_num	semc_nand_column_bit_num_t
	SEMC nand column address bit number.
typedef enum _semc_nand_burst_len	sem_nand_burst_len_t
	SEMC nand burst length.
typedef enum _semc_norsram_column_bit_num	semc_norsram_column_bit_num_t
	SEMC nor/sram column address bit number.
typedef enum _semc_norsram_burst_len	sem_norsram_burst_len_t
	SEMC nor/sram burst length.
typedef enum _semc_dbi_column_bit_num	semc_dbi_column_bit_num_t
	SEMC dbi column address bit number.
typedef enum _semc_dbi_burst_len	sem_dbi_burst_len_t
	SEMC dbi burst length.
typedef enum _semc_iomux_pin	semc_iomux_pin
	SEMC IOMUXC.
typedef enum _semc_iomux_nora27_pin	semc_iomux_nora27_pin
	SEMC NOR/PSRAM Address bit 27 A27.
typedef enum _semc_port_size	smec_port_size_t
	SEMC port size.
typedef enum _semc_addr_mode	semc_addr_mode_t
	SEMC address mode.
typedef enum _semc_dqs_mode	semc_dqs_mode_t
	SEMC DQS read strobe mode.
typedef enum _semc_adv_polarity	semc_adv_polarity_t
	SEMC ADV signal active polarity.
typedef enum _semc_sync_mode	semc_sync_mode_t
	SEMC sync mode.
typedef enum _semc_adv_level_control	semc_adv_level_control_t
	SEMC ADV signal level control.
typedef enum _semc_rdy_polarity	semc_rdy_polarity_t
	SEMC RDY signal active polarity.
typedef enum _semc_ipcmd_nand_addrmode	semc_ipcmd_nand_addrmode_t
	SEMC IP command for NAND: address mode.
typedef enum _semc_ipcmd_nand_cmdmode	semc_ipcmd_nand_cmdmode_t
	SEMC IP command for NAND： command mode.
typedef enum _semc_nand_address_option	semc_nand_address_option_t
	SEMC NAND address option.
typedef enum _semc_ipcmd_nor_dbi	semc_ipcmd_nor_dbi_t
	SEMC IP command for NOR.
typedef enum _semc_ipcmd_sram	semc_ipcmd_sram_t
	SEMC IP command for SRAM.
typedef enum _semc_ipcmd_sdram	semc_ipcmd_sdram_t
	SEMC IP command for SDARM.
typedef struct _semc_sdram_config	semc_sdram_config_t
	SEMC SDRAM configuration structure.
typedef struct _semc_nand_timing_config	semc_nand_timing_config_t
	SEMC NAND device timing configuration structure.
typedef struct _semc_nand_config	semc_nand_config_t
	SEMC NAND configuration structure.
typedef struct _semc_nor_config	semc_nor_config_t
	SEMC NOR configuration structure.
typedef struct _semc_sram_config	semc_sram_config_t
	SEMC SRAM configuration structure.
typedef struct _semc_dbi_config	semc_dbi_config_t
	SEMC DBI configuration structure.
typedef struct _semc_queuea_weight_struct	semc_queuea_weight_struct_t
	SEMC AXI queue a weight setting structure.
typedef union _semc_queuea_weight	semc_queuea_weight_t
	SEMC AXI queue a weight setting union.
typedef struct _semc_queueb_weight_struct	semc_queueb_weight_struct_t
	SEMC AXI queue b weight setting structure.
typedef union _semc_queueb_weight	semc_queueb_weight_t
	SEMC AXI queue b weight setting union.
typedef struct _semc_axi_queueweight	semc_axi_queueweight_t
	SEMC AXI queue weight setting.
typedef struct _semc_config_t	semc_config_t
	SEMC configuration structure.
#define	FSL_SEMC_DRIVER_VERSION   (MAKE_VERSION(2, 4, 3))
	SEMC driver version.

SEMC Initialization and De-initialization
void	SEMC_GetDefaultConfig (semc_config_t *config)
	Gets the SEMC default basic configuration structure.
void	SEMC_Init (SEMC_Type *base, semc_config_t *configure)
	Initializes SEMC. This function ungates the SEMC clock and initializes SEMC. This function must be called before calling any other SEMC driver functions.
void	SEMC_Deinit (SEMC_Type *base)
	Deinitializes the SEMC module and gates the clock.

SEMC Configuration Operation For Each Memory Type
status_t	SEMC_ConfigureSDRAM (SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz)
	Configures SDRAM controller in SEMC.
status_t	SEMC_ConfigureNAND (SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz)
	Configures NAND controller in SEMC.
status_t	SEMC_ConfigureNOR (SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz)
	Configures NOR controller in SEMC.
status_t	SEMC_ConfigureSRAMWithChipSelection (SEMC_Type *base, semc_sram_cs_t cs, semc_sram_config_t *config, uint32_t clkSrc_Hz)
	Configures SRAM controller in SEMC.
status_t	SEMC_ConfigureSRAM (SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz)
	Configures SRAM controller in SEMC.
status_t	SEMC_ConfigureDBI (SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz)
	Configures DBI controller in SEMC.

SEMC Memory Access Operation
status_t	SEMC_SendIPCommand (SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read)
	SEMC IP command access.
status_t	SEMC_IPCommandNandWrite (SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
	SEMC NAND device memory write through IP command.
status_t	SEMC_IPCommandNandRead (SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
	SEMC NAND device memory read through IP command.
status_t	SEMC_IPCommandNorWrite (SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
	SEMC NOR device memory write through IP command.
status_t	SEMC_IPCommandNorRead (SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes)
	SEMC NOR device memory read through IP command.

Detailed Description

Typedef Documentation

semc_config_t

typedef struct _semc_config_t semc_config_t

SEMC configuration structure.

busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. cmdTimeoutCycles: is used for command execution timeout cycles. it's similar to the busTimeoutCycles.

semc_sdram_config_t

typedef struct _semc_sdram_config semc_sdram_config_t

SEMC SDRAM configuration structure.

1. The memory size in the configuration is in the unit of KB. So memsize_kbytes should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. Take refer to BR0~BR3 register in RM for details.
2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are similar to prescalePeriod_N16Cycle.

Enumeration Type Documentation

anonymous enum

anonymous enum

SEMC status, _semc_status.

Enumerator
kStatus_SEMC_InvalidDeviceType	Invalid device type.
kStatus_SEMC_IpCommandExecutionError	IP command execution error.
kStatus_SEMC_AxiCommandExecutionError	AXI command execution error.
kStatus_SEMC_InvalidMemorySize	Invalid memory sie.
kStatus_SEMC_InvalidIpcmdDataSize	Invalid IP command data size.
kStatus_SEMC_InvalidAddressPortWidth	Invalid address port width.
kStatus_SEMC_InvalidDataPortWidth	Invalid data port width.
kStatus_SEMC_InvalidSwPinmuxSelection	Invalid SW pinmux selection.
kStatus_SEMC_InvalidBurstLength	Invalid burst length
kStatus_SEMC_InvalidColumnAddressBitWidth	Invalid column address bit width.
kStatus_SEMC_InvalidBaseAddress	Invalid base address.
kStatus_SEMC_InvalidTimerSetting	Invalid timer setting.

_semc_addr_mode

enum _semc_addr_mode

SEMC address mode.

Enumerator
kSEMC_AddrDataMux	SEMC address/data mux mode.
kSEMC_AdvAddrdataMux	Advanced address/data mux mode.
kSEMC_AddrDataNonMux	Address/data non-mux mode.

_semc_adv_level_control

enum _semc_adv_level_control

SEMC ADV signal level control.

Enumerator
kSEMC_AdvHigh	Adv is high during address hold state.
kSEMC_AdvLow	Adv is low during address hold state.

_semc_adv_polarity

enum _semc_adv_polarity

SEMC ADV signal active polarity.

Enumerator
kSEMC_AdvActiveLow	Adv active low.
kSEMC_AdvActiveHigh	Adv active high.

_semc_caslatency

enum _semc_caslatency

CAS latency.

Enumerator
kSEMC_LatencyOne	Latency 1.
kSEMC_LatencyTwo	Latency 2.
kSEMC_LatencyThree	Latency 3.

_semc_dbi_burst_len

enum _semc_dbi_burst_len

SEMC dbi burst length.

Enumerator
kSEMC_Dbi_BurstLen1	Burst length 1
kSEMC_Dbi_BurstLen2	Burst length 2
kSEMC_Dbi_Dbi_BurstLen4	Burst length 4
kSEMC_Dbi_BurstLen8	Burst length 8
kSEMC_Dbi_BurstLen16	Burst length 16
kSEMC_Dbi_BurstLen32	Burst length 32
kSEMC_Dbi_BurstLen64	Burst length 64

_semc_dbi_column_bit_num

enum _semc_dbi_column_bit_num

SEMC dbi column address bit number.

Enumerator
kSEMC_Dbi_Colum_12bit	12 bit.
kSEMC_Dbi_Colum_11bit	11 bit.
kSEMC_Dbi_Colum_10bit	10 bit.
kSEMC_Dbi_Colum_9bit	9 bit.
kSEMC_Dbi_Colum_8bit	8 bit.
kSEMC_Dbi_Colum_7bit	7 bit.
kSEMC_Dbi_Colum_6bit	6 bit.
kSEMC_Dbi_Colum_5bit	5 bit.
kSEMC_Dbi_Colum_4bit	4 bit.
kSEMC_Dbi_Colum_3bit	3 bit.
kSEMC_Dbi_Colum_2bit	2 bit.

_semc_dqs_mode

enum _semc_dqs_mode

SEMC DQS read strobe mode.

Enumerator
kSEMC_Loopbackinternal	Dummy read strobe loopbacked internally.
kSEMC_Loopbackdqspad	Dummy read strobe loopbacked from DQS pad.

_semc_interrupt_enable

enum _semc_interrupt_enable

SEMC interrupts .

Enumerator
kSEMC_IPCmdDoneInterrupt	Ip command done interrupt.
kSEMC_IPCmdErrInterrupt	Ip command error interrupt.
kSEMC_AXICmdErrInterrupt	AXI command error interrupt.
kSEMC_AXIBusErrInterrupt	AXI bus error interrupt.

_semc_iomux_nora27_pin

enum _semc_iomux_nora27_pin

SEMC NOR/PSRAM Address bit 27 A27.

Enumerator
kSEMC_MORA27_NONE	No NOR/SRAM A27 pin.
kSEMC_NORA27_MUXCSX3	MUX CSX3 Pin.
kSEMC_NORA27_MUXRDY	MUX RDY pin.

_semc_iomux_pin

enum _semc_iomux_pin

SEMC IOMUXC.

Enumerator
kSEMC_MUXA8	MUX A8 pin.
kSEMC_MUXCSX0	MUX CSX0 pin
kSEMC_MUXCSX1	MUX CSX1 Pin.
kSEMC_MUXCSX2	MUX CSX2 Pin.
kSEMC_MUXCSX3	MUX CSX3 Pin.
kSEMC_MUXRDY	MUX RDY pin.

_semc_ipcmd_datasize

enum _semc_ipcmd_datasize

SEMC IP command data size in bytes.

Enumerator
kSEMC_IPcmdDataSize_1bytes	The IP command data size 1 byte.
kSEMC_IPcmdDataSize_2bytes	The IP command data size 2 byte.
kSEMC_IPcmdDataSize_3bytes	The IP command data size 3 byte.
kSEMC_IPcmdDataSize_4bytes	The IP command data size 4 byte.

_semc_ipcmd_nand_addrmode

enum _semc_ipcmd_nand_addrmode

SEMC IP command for NAND: address mode.

Enumerator
kSEMC_NANDAM_ColumnRow	Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2).
kSEMC_NANDAM_ColumnCA0	Address mode: column address only(1 Byte-CA0).
kSEMC_NANDAM_ColumnCA0CA1	Address mode: column address only(2 Byte-CA0/CA1).
kSEMC_NANDAM_RawRA0	Address mode: row address only(1 Byte-RA0).
kSEMC_NANDAM_RawRA0RA1	Address mode: row address only(2 Byte-RA0/RA1).
kSEMC_NANDAM_RawRA0RA1RA2	Address mode: row address only(3 Byte-RA0).

_semc_ipcmd_nand_cmdmode

enum _semc_ipcmd_nand_cmdmode

SEMC IP command for NAND： command mode.

Enumerator
kSEMC_NANDCM_Command	command.
kSEMC_NANDCM_CommandHold	Command hold.
kSEMC_NANDCM_CommandAddress	Command address.
kSEMC_NANDCM_CommandAddressHold	Command address hold.
kSEMC_NANDCM_CommandAddressRead	Command address read.
kSEMC_NANDCM_CommandAddressWrite	Command address write.
kSEMC_NANDCM_CommandRead	Command read.
kSEMC_NANDCM_CommandWrite	Command write.
kSEMC_NANDCM_Read	Read.
kSEMC_NANDCM_Write	Write.

_semc_ipcmd_nor_dbi

enum _semc_ipcmd_nor_dbi

SEMC IP command for NOR.

Enumerator
kSEMC_NORDBICM_Read	NOR read.
kSEMC_NORDBICM_Write	NOR write.

_semc_ipcmd_sdram

enum _semc_ipcmd_sdram

SEMC IP command for SDARM.

Enumerator
kSEMC_SDRAMCM_Read	SDRAM memory read.
kSEMC_SDRAMCM_Write	SDRAM memory write.
kSEMC_SDRAMCM_Modeset	SDRAM MODE SET.
kSEMC_SDRAMCM_Active	SDRAM active.
kSEMC_SDRAMCM_AutoRefresh	SDRAM auto-refresh.
kSEMC_SDRAMCM_SelfRefresh	SDRAM self-refresh.
kSEMC_SDRAMCM_Precharge	SDRAM precharge.
kSEMC_SDRAMCM_Prechargeall	SDRAM precharge all.

_semc_ipcmd_sram

enum _semc_ipcmd_sram

SEMC IP command for SRAM.

Enumerator
kSEMC_SRAMCM_ArrayRead	SRAM memory array read.
kSEMC_SRAMCM_ArrayWrite	SRAM memory array write.
kSEMC_SRAMCM_RegRead	SRAM memory register read.
kSEMC_SRAMCM_RegWrite	SRAM memory register write.

_semc_mem_type

enum _semc_mem_type

SEMC memory device type.

Enumerator
kSEMC_MemType_SDRAM	SDRAM
kSEMC_MemType_SRAM	SRAM
kSEMC_MemType_NOR	NOR
kSEMC_MemType_NAND	NAND
kSEMC_MemType_8080

_semc_nand_access_type

enum _semc_nand_access_type

SEMC NAND device type.

Enumerator
kSEMC_NAND_ACCESS_BY_AXI	Access to NAND flash by AXI bus.
kSEMC_NAND_ACCESS_BY_IPCMD	Access to NAND flash by IP bus.

_semc_nand_address_option

enum _semc_nand_address_option

SEMC NAND address option.

Enumerator
kSEMC_NandAddrOption_5byte_CA2RA3	CA0+CA1+RA0+RA1+RA2
kSEMC_NandAddrOption_4byte_CA2RA2	CA0+CA1+RA0+RA1
kSEMC_NandAddrOption_3byte_CA2RA1	CA0+CA1+RA0
kSEMC_NandAddrOption_4byte_CA1RA3	CA0+RA0+RA1+RA2
kSEMC_NandAddrOption_3byte_CA1RA2	CA0+RA0+RA1
kSEMC_NandAddrOption_2byte_CA1RA1	CA0+RA0

_semc_nand_burst_len

enum _semc_nand_burst_len

SEMC nand burst length.

Enumerator
kSEMC_Nand_BurstLen1	Burst length 1
kSEMC_Nand_BurstLen2	Burst length 2
kSEMC_Nand_BurstLen4	Burst length 4
kSEMC_Nand_BurstLen8	Burst length 8
kSEMC_Nand_BurstLen16	Burst length 16
kSEMC_Nand_BurstLen32	Burst length 32
kSEMC_Nand_BurstLen64	Burst length 64

_semc_nand_column_bit_num

enum _semc_nand_column_bit_num

SEMC nand column address bit number.

Enumerator
kSEMC_NandColum_16bit	16 bit.
kSEMC_NandColum_15bit	15 bit.
kSEMC_NandColum_14bit	14 bit.
kSEMC_NandColum_13bit	13 bit.
kSEMC_NandColum_12bit	12 bit.
kSEMC_NandColum_11bit	11 bit.
kSEMC_NandColum_10bit	10 bit.
kSEMC_NandColum_9bit	9 bit.

_semc_norsram_burst_len

enum _semc_norsram_burst_len

SEMC nor/sram burst length.

Enumerator
kSEMC_Nor_BurstLen1	Burst length 1
kSEMC_Nor_BurstLen2	Burst length 2
kSEMC_Nor_BurstLen4	Burst length 4
kSEMC_Nor_BurstLen8	Burst length 8
kSEMC_Nor_BurstLen16	Burst length 16
kSEMC_Nor_BurstLen32	Burst length 32
kSEMC_Nor_BurstLen64	Burst length 64

_semc_norsram_column_bit_num

enum _semc_norsram_column_bit_num

SEMC nor/sram column address bit number.

Enumerator
kSEMC_NorColum_12bit	12 bit.
kSEMC_NorColum_11bit	11 bit.
kSEMC_NorColum_10bit	10 bit.
kSEMC_NorColum_9bit	9 bit.
kSEMC_NorColum_8bit	8 bit.
kSEMC_NorColum_7bit	7 bit.
kSEMC_NorColum_6bit	6 bit.
kSEMC_NorColum_5bit	5 bit.
kSEMC_NorColum_4bit	4 bit.
kSEMC_NorColum_3bit	3 bit.
kSEMC_NorColum_2bit	2 bit.

_semc_port_size

enum _semc_port_size

SEMC port size.

Enumerator
kSEMC_PortSize8Bit	8-Bit port size.
kSEMC_PortSize16Bit	16-Bit port size.

_semc_rdy_polarity

enum _semc_rdy_polarity

SEMC RDY signal active polarity.

Enumerator
kSEMC_RdyActiveLow	Adv active low.
kSEMC_RdyActivehigh	Adv active low.

_semc_refresh_time

enum _semc_refresh_time

SEMC auto-refresh timing.

Enumerator
kSEMC_RefreshThreeClocks	The refresh timing with three bus clocks.
kSEMC_RefreshSixClocks	The refresh timing with six bus clocks.
kSEMC_RefreshNineClocks	The refresh timing with nine bus clocks.

_semc_sdram_burst_len

enum _semc_sdram_burst_len

SEMC sdram burst length.

Enumerator
kSEMC_Sdram_BurstLen1	According to ERR050577, Auto-refresh command may possibly fail to be triggered during long time back-to-back write (or read) when SDRAM controller's burst length is greater than 1. Burst length 1
kSEMC_Sdram_BurstLen2	Burst length 2
kSEMC_Sdram_BurstLen4	Burst length 4
kSEMC_Sdram_BurstLen8	Burst length 8

_semc_sdram_column_bit_num

enum _semc_sdram_column_bit_num

SEMC sdram column address bit number.

Enumerator
kSEMC_SdramColunm_12bit	12 bit.
kSEMC_SdramColunm_11bit	11 bit.
kSEMC_SdramColunm_10bit	10 bit.
kSEMC_SdramColunm_9bit	9 bit.

_semc_sdram_cs

enum _semc_sdram_cs

SEMC SDRAM Chip selection .

Enumerator
kSEMC_SDRAM_CS0	SEMC SDRAM CS0.
kSEMC_SDRAM_CS1	SEMC SDRAM CS1.
kSEMC_SDRAM_CS2	SEMC SDRAM CS2.
kSEMC_SDRAM_CS3	SEMC SDRAM CS3.

_semc_sram_cs

enum _semc_sram_cs

SEMC SRAM Chip selection .

Enumerator
kSEMC_SRAM_CS0	SEMC SRAM CS0.

_semc_sync_mode

enum _semc_sync_mode

SEMC sync mode.

Enumerator
kSEMC_AsyncMode	Async mode.
kSEMC_SyncMode	Sync mode.

_semc_waitready_polarity

enum _semc_waitready_polarity

SEMC WAIT/RDY polarity.

Enumerator
kSEMC_LowActive	Low active.
kSEMC_HighActive	High active.

Function Documentation

SEMC_ConfigureDBI()

status_t SEMC_ConfigureDBI	(	SEMC_Type *	base,
		semc_dbi_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Configures DBI controller in SEMC.

Parameters

base	SEMC peripheral base address.
config	The dbi configuration.
clkSrc_Hz	The SEMC clock frequency.

brief Configures DBI controller in SEMC.

param base SEMC peripheral base address. param config The dbi configuration. param clkSrc_Hz The SEMC clock frequency.

SEMC_ConfigureNAND()

status_t SEMC_ConfigureNAND	(	SEMC_Type *	base,
		semc_nand_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Configures NAND controller in SEMC.

Parameters

base	SEMC peripheral base address.
config	The nand configuration.
clkSrc_Hz	The SEMC clock frequency.

brief Configures NAND controller in SEMC.

param base SEMC peripheral base address. param config The nand configuration. param clkSrc_Hz The SEMC clock frequency.

SEMC_ConfigureNOR()

status_t SEMC_ConfigureNOR	(	SEMC_Type *	base,
		semc_nor_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Configures NOR controller in SEMC.

Parameters

base	SEMC peripheral base address.
config	The nor configuration.
clkSrc_Hz	The SEMC clock frequency.

brief Configures NOR controller in SEMC.

param base SEMC peripheral base address. param config The nor configuration. param clkSrc_Hz The SEMC clock frequency.

SEMC_ConfigureSDRAM()

status_t SEMC_ConfigureSDRAM	(	SEMC_Type *	base,
		semc_sdram_cs_t	cs,
		semc_sdram_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Configures SDRAM controller in SEMC.

Parameters

base	SEMC peripheral base address.
cs	The chip selection.
config	The sdram configuration.
clkSrc_Hz	The SEMC clock frequency.

brief Configures SDRAM controller in SEMC.

param base SEMC peripheral base address. param cs The chip selection. param config The sdram configuration. param clkSrc_Hz The SEMC clock frequency.

SEMC_ConfigureSRAM()

status_t SEMC_ConfigureSRAM	(	SEMC_Type *	base,
		semc_sram_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Configures SRAM controller in SEMC.

Deprecated:

Do not use this function. It has been superceded by SEMC_ConfigureSRAMWithChipSelection.

Parameters

base	SEMC peripheral base address.
config	The sram configuration.
clkSrc_Hz	The SEMC clock frequency.

brief Configures SRAM controller in SEMC, which can be used only for specific chip selection CS0.

param base SEMC peripheral base address. param config The sram configuration. param clkSrc_Hz The SEMC clock frequency.

SEMC_ConfigureSRAMWithChipSelection()

status_t SEMC_ConfigureSRAMWithChipSelection	(	SEMC_Type *	base,
		semc_sram_cs_t	cs,
		semc_sram_config_t *	config,
		uint32_t	clkSrc_Hz
	)

Configures SRAM controller in SEMC.

Parameters

base	SEMC peripheral base address.
cs	The chip selection.
config	The sram configuration.
clkSrc_Hz	The SEMC clock frequency.

brief Configures SRAM controller in SEMC, which can be used up to four chip selections CS0/CS1/CS2/CS3..

param base SEMC peripheral base address. param cs The chip selection. param config The sram configuration. param clkSrc_Hz The SEMC clock frequency.

SEMC_Deinit()

void SEMC_Deinit

(

SEMC_Type *

base

)

Deinitializes the SEMC module and gates the clock.

This function gates the SEMC clock. As a result, the SEMC module doesn't work after calling this function, for some IDE, calling this API may cause the next downloading operation failed. so, please call this API cautiously. Additional, users can using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control operation in drivers.

Parameters

base	SEMC peripheral base address.

brief Deinitializes the SEMC module and gates the clock. This function gates the SEMC clock. As a result, the SEMC module doesn't work after calling this function.

param base SEMC peripheral base address.

SEMC_GetDefaultConfig()

void SEMC_GetDefaultConfig

(

semc_config_t *

config

)

Gets the SEMC default basic configuration structure.

The purpose of this API is to get the default SEMC configure structure for SEMC_Init(). User may use the initialized structure unchanged in SEMC_Init(), or modify some fields of the structure before calling SEMC_Init(). Example:

semc_config_t config;
SEMC_GetDefaultConfig(&config);

Parameters

config

The SEMC configuration structure pointer.

brief Gets the SEMC default basic configuration structure.

The purpose of this API is to get the default SEMC configure structure for SEMC_Init(). User may use the initialized structure unchanged in SEMC_Init(), or modify some fields of the structure before calling SEMC_Init(). Example: code semc_config_t config; SEMC_GetDefaultConfig(&config); endcode param config The SEMC configuration structure pointer.

SEMC_Init()

void SEMC_Init	(	SEMC_Type *	base,
		semc_config_t *	configure
	)

Initializes SEMC. This function ungates the SEMC clock and initializes SEMC. This function must be called before calling any other SEMC driver functions.

Parameters

base	SEMC peripheral base address.
configure	The SEMC configuration structure pointer.

brief Initializes SEMC. This function ungates the SEMC clock and initializes SEMC. This function must be called before calling any other SEMC driver functions.

param base SEMC peripheral base address. param configure The SEMC configuration structure pointer.

SEMC_IPCommandNandRead()

status_t SEMC_IPCommandNandRead	(	SEMC_Type *	base,
		uint32_t	address,
		uint8_t *	data,
		uint32_t	size_bytes
	)

SEMC NAND device memory read through IP command.

Parameters

base	SEMC peripheral base address.
address	SEMC NAND device address.
data	Data pointer for data read out.
size_bytes	Data length.

brief SEMC NAND device memory read through IP command.

param base SEMC peripheral base address. param address SEMC NAND device address. param data Data pointer for data read out. param size_bytes Data length.

SEMC_IPCommandNandWrite()

status_t SEMC_IPCommandNandWrite	(	SEMC_Type *	base,
		uint32_t	address,
		uint8_t *	data,
		uint32_t	size_bytes
	)

SEMC NAND device memory write through IP command.

Parameters

base	SEMC peripheral base address.
address	SEMC NAND device address.
data	Data for write access.
size_bytes	Data length.

brief SEMC NAND device memory write through IP command.

param base SEMC peripheral base address. param address SEMC NAND device address. param data Data for write access. param size_bytes Data length.

SEMC_IPCommandNorRead()

status_t SEMC_IPCommandNorRead	(	SEMC_Type *	base,
		uint32_t	address,
		uint8_t *	data,
		uint32_t	size_bytes
	)

SEMC NOR device memory read through IP command.

Parameters

base	SEMC peripheral base address.
address	SEMC NOR device address.
data	Data pointer for data read out.
size_bytes	Data length.

brief SEMC NOR device memory read through IP command.

param base SEMC peripheral base address. param address SEMC NOR device address. param data Data pointer for data read out. param size_bytes Data length.

SEMC_IPCommandNorWrite()

status_t SEMC_IPCommandNorWrite	(	SEMC_Type *	base,
		uint32_t	address,
		uint8_t *	data,
		uint32_t	size_bytes
	)

SEMC NOR device memory write through IP command.

Parameters

base	SEMC peripheral base address.
address	SEMC NOR device address.
data	Data for write access.
size_bytes	Data length.

brief SEMC NOR device memory write through IP command.

param base SEMC peripheral base address. param address SEMC NOR device address. param data Data for write access. param size_bytes Data length.

SEMC_SendIPCommand()

status_t SEMC_SendIPCommand	(	SEMC_Type *	base,
		semc_mem_type_t	memType,
		uint32_t	address,
		uint32_t	command,
		uint32_t	write,
		uint32_t *	read
	)

SEMC IP command access.

Parameters

base	SEMC peripheral base address.
memType	SEMC memory type. refer to "semc_mem_type_t"
address	SEMC device address.
command	SEMC IP command. For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". For SRAM device, take refer to "semc_ipcmd_sram_t". For SDRAM device, take refer to "semc_ipcmd_sdram_t".
write	Data for write access.
read	Data pointer for read data out.

brief SEMC IP command access.

param base SEMC peripheral base address. param memType SEMC memory type. refer to "semc_mem_type_t" param address SEMC device address. param command SEMC IP command. For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". For SRAM device, take refer to "semc_ipcmd_sram_t". For SDRAM device, take refer to "semc_ipcmd_sdram_t". param write Data for write access. param read Data pointer for read data out.

Variable Documentation

addr27 [1/2]

semc_iomux_nora27_pin _semc_nor_config::addr27

The Addr bit 27 pin mux setting.

addr27 [2/2]

semc_iomux_nora27_pin _semc_sram_config::addr27

The Addr bit 27 pin mux setting.

address [1/4]

uint32_t _semc_sdram_config::address

The base address.

address [2/4]

uint32_t _semc_nor_config::address

The base address.

address [3/4]

uint32_t _semc_sram_config::address

The base address.

address [4/4]

uint32_t _semc_dbi_config::address

The base address.

addrMode [1/2]

semc_addr_mode_t _semc_nor_config::addrMode

Address mode.

addrMode [2/2]

semc_addr_mode_t _semc_sram_config::addrMode

Address mode.

addrPortWidth [1/2]

uint8_t _semc_nor_config::addrPortWidth

The address port width.

addrPortWidth [2/2]

uint8_t _semc_sram_config::addrPortWidth

The address port width.

advActivePolarity [1/2]

semc_adv_polarity_t _semc_nor_config::advActivePolarity

ADV# polarity.

advActivePolarity [2/2]

semc_adv_polarity_t _semc_sram_config::advActivePolarity

ADV# polarity 1: active high, 0: active low.

aging [1/2]

uint32_t _semc_queuea_weight_struct::aging

weight of aging for queue 0.

aging [2/2]

uint32_t _semc_queueb_weight_struct::aging

weight of aging for queue 1.

arrayAddrOption

semc_nand_address_option_t _semc_nand_config::arrayAddrOption

Address option.

axiAddress

uint32_t _semc_nand_config::axiAddress

The base address for AXI nand.

axiMemsize_kbytes

uint32_t _semc_nand_config::axiMemsize_kbytes

The memory size in unit of kbytes for AXI nand.

bankRotation

uint32_t _semc_queueb_weight_struct::bankRotation

weight of bank rotation for queue 1 only .

burstLen [1/5]

sem_sdram_burst_len_t _semc_sdram_config::burstLen

Burst length.

burstLen [2/5]

sem_nand_burst_len_t _semc_nand_config::burstLen

Burst length.

burstLen [3/5]

sem_norsram_burst_len_t _semc_nor_config::burstLen

Burst length.

burstLen [4/5]

sem_norsram_burst_len_t _semc_sram_config::burstLen

Burst length.

burstLen [5/5]

sem_dbi_burst_len_t _semc_dbi_config::burstLen

Burst length.

busTimeoutCycles

uint8_t _semc_config_t::busTimeoutCycles

Bus timeout cycles.

casLatency

semc_caslatency_t _semc_sdram_config::casLatency

CAS latency.

cePinMux [1/3]

semc_iomux_pin _semc_nand_config::cePinMux

The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting.

cePinMux [2/3]

semc_iomux_pin _semc_nor_config::cePinMux

The CE# pin mux setting.

cePinMux [3/3]

semc_iomux_pin _semc_sram_config::cePinMux

The CE# pin mux setting.

cmdTimeoutCycles

uint8_t _semc_config_t::cmdTimeoutCycles

Command execution timeout cycles.

columnAddrBitNum [1/4]

semc_sdram_column_bit_num_t _semc_sdram_config::columnAddrBitNum

Column address bit number.

columnAddrBitNum [2/4]

semc_nand_column_bit_num_t _semc_nand_config::columnAddrBitNum

Column address bit number.

columnAddrBitNum [3/4]

semc_norsram_column_bit_num_t _semc_nor_config::columnAddrBitNum

Column address bit number.

columnAddrBitNum [4/4]

semc_dbi_column_bit_num_t _semc_dbi_config::columnAddrBitNum

Column address bit number.

csxPinMux [1/2]

semc_iomux_pin _semc_sdram_config::csxPinMux

CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting.

csxPinMux [2/2]

semc_iomux_pin _semc_dbi_config::csxPinMux

The CE# pin mux.

dqsMode

semc_dqs_mode_t _semc_config_t::dqsMode

Dummy read strobe mode: use enum in "semc_dqs_mode_t".

edoModeEnabled

bool _semc_nand_config::edoModeEnabled

EDO mode enabled.

ipgAddress

uint32_t _semc_nand_config::ipgAddress

The base address for IPG nand .

ipgMemsize_kbytes

uint32_t _semc_nand_config::ipgMemsize_kbytes

The memory size in unit of kbytes for IPG nand.

memsize_kbytes [1/4]

uint32_t _semc_sdram_config::memsize_kbytes

The memory size in unit of kbytes.

memsize_kbytes [2/4]

uint32_t _semc_nor_config::memsize_kbytes

The memory size in unit of kbytes.

memsize_kbytes [3/4]

uint32_t _semc_sram_config::memsize_kbytes

The memory size in unit of kbytes.

memsize_kbytes [4/4]

uint32_t _semc_dbi_config::memsize_kbytes

The memory size in unit of 4kbytes.

portSize [1/5]

smec_port_size_t _semc_sdram_config::portSize

Port size.

portSize [2/5]

smec_port_size_t _semc_nand_config::portSize

Port size.

portSize [3/5]

smec_port_size_t _semc_nor_config::portSize

Port size.

portSize [4/5]

smec_port_size_t _semc_sram_config::portSize

Port size.

portSize [5/5]

smec_port_size_t _semc_dbi_config::portSize

Port size.

qos [1/2]

uint32_t _semc_queuea_weight_struct::qos

weight of qos for queue 0 .

qos [2/2]

uint32_t _semc_queueb_weight_struct::qos

weight of qos for queue 1.

queueaConfig

semc_queuea_weight_struct_t _semc_queuea_weight::queueaConfig

Structure configuration for queueA.

queueaEnable

bool _semc_axi_queueweight::queueaEnable

Enable queue a.

queueaValue

uint32_t _semc_queuea_weight::queueaValue

Configuration value for queueA which could directly write to the reg.

queueaWeight

semc_queuea_weight_t _semc_axi_queueweight::queueaWeight

Weight settings for queue a.

queuebConfig

semc_queueb_weight_struct_t _semc_queueb_weight::queuebConfig

Structure configuration for queueB.

queuebEnable

bool _semc_axi_queueweight::queuebEnable

Enable queue b.

queuebValue

uint32_t _semc_queueb_weight::queuebValue

Configuration value for queueB which could directly write to the reg.

queuebWeight

semc_queueb_weight_t _semc_axi_queueweight::queuebWeight

Weight settings for queue b.

queueWeight

semc_axi_queueweight_t _semc_config_t::queueWeight

AXI queue weight.

rdyactivePolarity [1/2]

semc_rdy_polarity_t _semc_nand_config::rdyactivePolarity

Wait ready polarity.

rdyactivePolarity [2/2]

semc_rdy_polarity_t _semc_nor_config::rdyactivePolarity

Wait ready polarity.

refreshBurstLen

uint8_t _semc_sdram_config::refreshBurstLen

Refresh burst length.

refreshPeriod_nsPerRow

uint32_t _semc_sdram_config::refreshPeriod_nsPerRow

Refresh timer period like 64ms * 1000000/8192 .

refreshUrgThreshold

uint32_t _semc_sdram_config::refreshUrgThreshold

Refresh urgent threshold.

slaveHitNoswitch

uint32_t _semc_queuea_weight_struct::slaveHitNoswitch

weight of read/write no switch for queue 0 .

slaveHitSwith [1/2]

uint32_t _semc_queuea_weight_struct::slaveHitSwith

weight of read/write switch for queue 0.

slaveHitSwith [2/2]

uint32_t _semc_queueb_weight_struct::slaveHitSwith

weight of read/write switch for queue 1.

tAct2Act_Ns

uint8_t _semc_sdram_config::tAct2Act_Ns

Active to active wait time in unit of nanosecond.

tAct2Prechage_Ns

uint8_t _semc_sdram_config::tAct2Prechage_Ns

Active to precharge in unit of nanosecond.

tAct2ReadWrite_Ns

uint8_t _semc_sdram_config::tAct2ReadWrite_Ns

Act to read/write wait time in unit of nanosecond.

tAddr2WriteHold_Ns [1/2]

uint8_t _semc_nor_config::tAddr2WriteHold_Ns

Address to write data hold time for async mode.

tAddr2WriteHold_Ns [2/2]

uint8_t _semc_sram_config::tAddr2WriteHold_Ns

Address to write data hold time for async mode.

tAddrHold_Ns [1/2]

uint8_t _semc_nor_config::tAddrHold_Ns

The address hold time.

tAddrHold_Ns [2/2]

uint8_t _semc_sram_config::tAddrHold_Ns

The address hold time.

tAddrSetup_Ns [1/2]

uint8_t _semc_nor_config::tAddrSetup_Ns

The address setup time.

tAddrSetup_Ns [2/2]

uint8_t _semc_sram_config::tAddrSetup_Ns

The address setup time.

tAle2WriteStart_Ns

uint8_t _semc_nand_timing_config::tAle2WriteStart_Ns

ALE to write start wait time: tADL.

tCeHold_Ns [1/3]

uint8_t _semc_nand_timing_config::tCeHold_Ns

CE hold time: tCH.

tCeHold_Ns [2/3]

uint8_t _semc_nor_config::tCeHold_Ns

The CE hold time.

tCeHold_Ns [3/3]

uint8_t _semc_sram_config::tCeHold_Ns

The CE hold time.

tCeInterval_Ns [1/3]

uint8_t _semc_nand_timing_config::tCeInterval_Ns

CE interval time:tCEITV.

tCeInterval_Ns [2/3]

uint8_t _semc_nor_config::tCeInterval_Ns

CE interval minimum time.

tCeInterval_Ns [3/3]

uint8_t _semc_sram_config::tCeInterval_Ns

CE interval minimum time.

tCeSetup_Ns [1/3]

uint8_t _semc_nand_timing_config::tCeSetup_Ns

CE setup time: tCS.

tCeSetup_Ns [2/3]

uint8_t _semc_nor_config::tCeSetup_Ns

The CE setup time.

tCeSetup_Ns [3/3]

uint8_t _semc_sram_config::tCeSetup_Ns

The CE setup time.

tCkeOff_Ns

uint8_t _semc_sdram_config::tCkeOff_Ns

CKE off minimum time in unit of nanosecond.

tCsxHold_Ns

uint8_t _semc_dbi_config::tCsxHold_Ns

The CSX hold time.

tCsxInterval_Ns

uint8_t _semc_dbi_config::tCsxInterval_Ns

Write data setup time.

tCsxSetup_Ns

uint8_t _semc_dbi_config::tCsxSetup_Ns

The CSX setup time.

tIdleTimeout_Ns

uint32_t _semc_sdram_config::tIdleTimeout_Ns

Idle timeout in unit of prescale time period.

timingConfig

semc_nand_timing_config_t* _semc_nand_config::timingConfig

SEMC nand timing configuration.

tPrecharge2Act_Ns

uint8_t _semc_sdram_config::tPrecharge2Act_Ns

Precharge to active wait time in unit of nanosecond.

tPrescalePeriod_Ns

uint32_t _semc_sdram_config::tPrescalePeriod_Ns

Prescaler timer period should not be larger than 256 * 16 * clock cycle.

tRdxHigh_Ns

uint8_t _semc_dbi_config::tRdxHigh_Ns

RDX high time.

tRdxLow_Ns

uint8_t _semc_dbi_config::tRdxLow_Ns

RDX low time.

tReady2Relow_Ns

uint8_t _semc_nand_timing_config::tReady2Relow_Ns

Ready to RE# low min wait time: tRR.

tRefresh2Refresh_Ns

uint8_t _semc_sdram_config::tRefresh2Refresh_Ns

Refresh to refresh wait time in unit of nanosecond.

tRefreshRecovery_Ns

uint8_t _semc_sdram_config::tRefreshRecovery_Ns

Refresh recovery time in unit of nanosecond.

tRehigh2Welow_Ns

uint8_t _semc_nand_timing_config::tRehigh2Welow_Ns

RE# high to WE# low wait time: tRHW.

tReHigh_Ns [1/3]

uint8_t _semc_nand_timing_config::tReHigh_Ns

RE high time: tREH.

tReHigh_Ns [2/3]

uint8_t _semc_nor_config::tReHigh_Ns

RE high time for async mode.

tReHigh_Ns [3/3]

uint8_t _semc_sram_config::tReHigh_Ns

RE high time for async mode.

tReLow_Ns [1/3]

uint8_t _semc_nand_timing_config::tReLow_Ns

RE low time: tRP.

tReLow_Ns [2/3]

uint8_t _semc_nor_config::tReLow_Ns

RE low time for async mode.

tReLow_Ns [3/3]

uint8_t _semc_sram_config::tReLow_Ns

RE low time for async mode.

tSelfRefRecovery_Ns

uint8_t _semc_sdram_config::tSelfRefRecovery_Ns

Self refresh recovery time in unit of nanosecond.

tTurnAround_Ns [1/3]

uint8_t _semc_nand_timing_config::tTurnAround_Ns

Turnaround time for async mode: tTA.

tTurnAround_Ns [2/3]

uint8_t _semc_nor_config::tTurnAround_Ns

Turnaround time for async mode.

tTurnAround_Ns [3/3]

uint8_t _semc_sram_config::tTurnAround_Ns

Turnaround time for async mode.

tWehigh2Busy_Ns

uint8_t _semc_nand_timing_config::tWehigh2Busy_Ns

WE# high to busy wait time: tWB.

tWehigh2Relow_Ns

uint8_t _semc_nand_timing_config::tWehigh2Relow_Ns

WE# high to RE# wait time: tWHR.

tWeHigh_Ns [1/3]

uint8_t _semc_nand_timing_config::tWeHigh_Ns

WE high time: tWH.

tWeHigh_Ns [2/3]

uint8_t _semc_nor_config::tWeHigh_Ns

WE high time for async mode.

tWeHigh_Ns [3/3]

uint8_t _semc_sram_config::tWeHigh_Ns

WE high time for async mode.

tWeLow_Ns [1/3]

uint8_t _semc_nand_timing_config::tWeLow_Ns

WE low time: tWP.

tWeLow_Ns [2/3]

uint8_t _semc_nor_config::tWeLow_Ns

WE low time for async mode.

tWeLow_Ns [3/3]

uint8_t _semc_sram_config::tWeLow_Ns

WE low time for async mode.

tWexHigh_Ns

uint8_t _semc_dbi_config::tWexHigh_Ns

WEX high time.

tWexLow_Ns

uint8_t _semc_dbi_config::tWexLow_Ns

WEX low time.

tWriteRecovery_Ns

uint8_t _semc_sdram_config::tWriteRecovery_Ns

write recovery time in unit of nanosecond.

weightPagehit

uint32_t _semc_queueb_weight_struct::weightPagehit

weight of page hit for queue 1 only .