RTEMS 6.1-rc6
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Data Structures | |
struct | _csi2rx_config |
CSI2RX configuration. More... | |
Variables | |
uint8_t | _csi2rx_config::laneNum |
uint8_t | _csi2rx_config::tHsSettle_EscClk |
Driver version | |
enum | _csi2rx_data_lane { kCSI2RX_DataLane0 = (1U << 0U) , kCSI2RX_DataLane1 = (1U << 1U) , kCSI2RX_DataLane2 = (1U << 2U) , kCSI2RX_DataLane3 = (1U << 3U) } |
CSI2RX data lanes. More... | |
enum | _csi2rx_payload { kCSI2RX_PayloadGroup0Null = (1U << 0U) , kCSI2RX_PayloadGroup0Blank = (1U << 1U) , kCSI2RX_PayloadGroup0Embedded = (1U << 2U) , kCSI2RX_PayloadGroup0YUV420_8Bit = (1U << 10U) , kCSI2RX_PayloadGroup0YUV422_8Bit = (1U << 14U) , kCSI2RX_PayloadGroup0YUV422_10Bit = (1U << 15U) , kCSI2RX_PayloadGroup0RGB444 = (1U << 16U) , kCSI2RX_PayloadGroup0RGB555 = (1U << 17U) , kCSI2RX_PayloadGroup0RGB565 = (1U << 18U) , kCSI2RX_PayloadGroup0RGB666 = (1U << 19U) , kCSI2RX_PayloadGroup0RGB888 = (1U << 20U) , kCSI2RX_PayloadGroup0Raw6 = (1U << 24U) , kCSI2RX_PayloadGroup0Raw7 = (1U << 25U) , kCSI2RX_PayloadGroup0Raw8 = (1U << 26U) , kCSI2RX_PayloadGroup0Raw10 = (1U << 27U) , kCSI2RX_PayloadGroup0Raw12 = (1U << 28U) , kCSI2RX_PayloadGroup0Raw14 = (1U << 29U) , kCSI2RX_PayloadGroup1UserDefined1 = (1U << 0U) , kCSI2RX_PayloadGroup1UserDefined2 = (1U << 1U) , kCSI2RX_PayloadGroup1UserDefined3 = (1U << 2U) , kCSI2RX_PayloadGroup1UserDefined4 = (1U << 3U) , kCSI2RX_PayloadGroup1UserDefined5 = (1U << 4U) , kCSI2RX_PayloadGroup1UserDefined6 = (1U << 5U) , kCSI2RX_PayloadGroup1UserDefined7 = (1U << 6U) , kCSI2RX_PayloadGroup1UserDefined8 = (1U << 7U) } |
CSI2RX payload type. More... | |
enum | _csi2rx_bit_error { kCSI2RX_BitErrorEccTwoBit = (1U << 0U) , kCSI2RX_BitErrorEccOneBit = (1U << 1U) } |
MIPI CSI2RX bit errors. More... | |
enum | _csi2rx_ppi_error { kCSI2RX_PpiErrorSotHs , kCSI2RX_PpiErrorSotSyncHs , kCSI2RX_PpiErrorEsc , kCSI2RX_PpiErrorSyncEsc , kCSI2RX_PpiErrorControl } |
MIPI CSI2RX PPI error types. More... | |
enum | _csi2rx_interrupt { kCSI2RX_InterruptCrcError = (1U << 0U) , kCSI2RX_InterruptEccOneBitError = (1U << 1U) , kCSI2RX_InterruptEccTwoBitError = (1U << 2U) , kCSI2RX_InterruptUlpsStatusChange = (1U << 3U) , kCSI2RX_InterruptErrorSotHs = (1U << 4U) , kCSI2RX_InterruptErrorSotSyncHs = (1U << 5U) , kCSI2RX_InterruptErrorEsc = (1U << 6U) , kCSI2RX_InterruptErrorSyncEsc = (1U << 7U) , kCSI2RX_InterruptErrorControl = (1U << 8U) } |
MIPI CSI2RX interrupt. | |
enum | _csi2rx_ulps_status { kCSI2RX_ClockLaneUlps = (1U << 0U) , kCSI2RX_DataLane0Ulps = (1U << 1U) , kCSI2RX_DataLane1Ulps = (1U << 2U) , kCSI2RX_DataLane2Ulps = (1U << 3U) , kCSI2RX_DataLane3Ulps = (1U << 4U) , kCSI2RX_ClockLaneMark = (1U << 5U) , kCSI2RX_DataLane0Mark = (1U << 6U) , kCSI2RX_DataLane1Mark = (1U << 7U) , kCSI2RX_DataLane2Mark = (1U << 8U) , kCSI2RX_DataLane3Mark = (1U << 9U) } |
MIPI CSI2RX D-PHY ULPS state. More... | |
typedef struct _csi2rx_config | csi2rx_config_t |
CSI2RX configuration. | |
typedef enum _csi2rx_ppi_error | csi2rx_ppi_error_t |
MIPI CSI2RX PPI error types. | |
void | CSI2RX_Init (MIPI_CSI2RX_Type *base, const csi2rx_config_t *config) |
Enables and configures the CSI2RX peripheral module. | |
void | CSI2RX_Deinit (MIPI_CSI2RX_Type *base) |
Disables the CSI2RX peripheral module. | |
#define | FSL_CSI2RX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) |
CSI2RX driver version. | |
#define | CSI2RX_REG_CFG_NUM_LANES(base) (base)->CSI2RX_CFG_NUM_LANES |
#define | CSI2RX_REG_CFG_DISABLE_DATA_LANES(base) (base)->CSI2RX_CFG_DISABLE_DATA_LANES |
#define | CSI2RX_REG_BIT_ERR(base) (base)->CSI2RX_BIT_ERR |
#define | CSI2RX_REG_IRQ_STATUS(base) (base)->CSI2RX_IRQ_STATUS |
#define | CSI2RX_REG_IRQ_MASK(base) (base)->CSI2RX_IRQ_MASK |
#define | CSI2RX_REG_ULPS_STATUS(base) (base)->CSI2RX_ULPS_STATUS |
#define | CSI2RX_REG_PPI_ERRSOT_HS(base) (base)->CSI2RX_PPI_ERRSOT_HS |
#define | CSI2RX_REG_PPI_ERRSOTSYNC_HS(base) (base)->CSI2RX_PPI_ERRSOTSYNC_HS |
#define | CSI2RX_REG_PPI_ERRESC(base) (base)->CSI2RX_PPI_ERRESC |
#define | CSI2RX_REG_PPI_ERRSYNCESC(base) (base)->CSI2RX_PPI_ERRSYNCESC |
#define | CSI2RX_REG_PPI_ERRCONTROL(base) (base)->CSI2RX_PPI_ERRCONTROL |
#define | CSI2RX_REG_CFG_DISABLE_PAYLOAD_0(base) (base)->CSI2RX_CFG_DISABLE_PAYLOAD_0 |
#define | CSI2RX_REG_CFG_DISABLE_PAYLOAD_1(base) (base)->CSI2RX_CFG_DISABLE_PAYLOAD_1 |
#define | CSI2RX_REG_CFG_IGNORE_VC(base) (base)->CSI2RX_CFG_IGNORE_VC |
#define | CSI2RX_REG_CFG_VID_VC(base) (base)->CSI2RX_CFG_VID_VC |
#define | CSI2RX_REG_CFG_VID_P_FIFO_SEND_LEVEL(base) (base)->CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL |
#define | CSI2RX_REG_CFG_VID_VSYNC(base) (base)->CSI2RX_CFG_VID_VSYNC |
#define | CSI2RX_REG_CFG_VID_HSYNC_FP(base) (base)->CSI2RX_CFG_VID_HSYNC_FP |
#define | CSI2RX_REG_CFG_VID_HSYNC(base) (base)->CSI2RX_CFG_VID_HSYNC |
#define | CSI2RX_REG_CFG_VID_HSYNC_BP(base) (base)->CSI2RX_CFG_VID_HSYNC_BP |
#define | MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK |
#define | MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK |
enum _csi2rx_bit_error |
enum _csi2rx_data_lane |
enum _csi2rx_payload |
CSI2RX payload type.
enum _csi2rx_ppi_error |
MIPI CSI2RX PPI error types.
enum _csi2rx_ulps_status |
MIPI CSI2RX D-PHY ULPS state.
void CSI2RX_Deinit | ( | MIPI_CSI2RX_Type * | base | ) |
Disables the CSI2RX peripheral module.
base | CSI2RX peripheral address. |
brief Disables the CSI2RX peripheral module.
param base CSI2RX peripheral address.
void CSI2RX_Init | ( | MIPI_CSI2RX_Type * | base, |
const csi2rx_config_t * | config | ||
) |
Enables and configures the CSI2RX peripheral module.
base | CSI2RX peripheral address. |
config | CSI2RX module configuration structure. |
brief Enables and configures the CSI2RX peripheral module.
param base CSI2RX peripheral address. param config CSI2RX module configuration structure.
uint8_t _csi2rx_config::laneNum |
Number of active lanes used for receiving data.
uint8_t _csi2rx_config::tHsSettle_EscClk |
Number of rx_clk_esc clock periods for T_HS_SETTLE. The T_HS_SETTLE should be in the range of 85ns + 6UI to 145ns + 10UI.