RTEMS 6.1-rc6
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WCR - Watchdog Control Register | |
#define | WDOG_WCR_WDZST_MASK (0x1U) |
#define | WDOG_WCR_WDZST_SHIFT (0U) |
#define | WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) |
#define | WDOG_WCR_WDBG_MASK (0x2U) |
#define | WDOG_WCR_WDBG_SHIFT (1U) |
#define | WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) |
#define | WDOG_WCR_WDE_MASK (0x4U) |
#define | WDOG_WCR_WDE_SHIFT (2U) |
#define | WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) |
#define | WDOG_WCR_WDT_MASK (0x8U) |
#define | WDOG_WCR_WDT_SHIFT (3U) |
#define | WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) |
#define | WDOG_WCR_SRS_MASK (0x10U) |
#define | WDOG_WCR_SRS_SHIFT (4U) |
#define | WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) |
#define | WDOG_WCR_WDA_MASK (0x20U) |
#define | WDOG_WCR_WDA_SHIFT (5U) |
#define | WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) |
#define | WDOG_WCR_SRE_MASK (0x40U) |
#define | WDOG_WCR_SRE_SHIFT (6U) |
#define | WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) |
#define | WDOG_WCR_WDW_MASK (0x80U) |
#define | WDOG_WCR_WDW_SHIFT (7U) |
#define | WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) |
#define | WDOG_WCR_WT_MASK (0xFF00U) |
#define | WDOG_WCR_WT_SHIFT (8U) |
#define | WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) |
WSR - Watchdog Service Register | |
#define | WDOG_WSR_WSR_MASK (0xFFFFU) |
#define | WDOG_WSR_WSR_SHIFT (0U) |
#define | WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) |
WRSR - Watchdog Reset Status Register | |
#define | WDOG_WRSR_SFTW_MASK (0x1U) |
#define | WDOG_WRSR_SFTW_SHIFT (0U) |
#define | WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) |
#define | WDOG_WRSR_TOUT_MASK (0x2U) |
#define | WDOG_WRSR_TOUT_SHIFT (1U) |
#define | WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) |
#define | WDOG_WRSR_POR_MASK (0x10U) |
#define | WDOG_WRSR_POR_SHIFT (4U) |
#define | WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) |
WICR - Watchdog Interrupt Control Register | |
#define | WDOG_WICR_WICT_MASK (0xFFU) |
#define | WDOG_WICR_WICT_SHIFT (0U) |
#define | WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) |
#define | WDOG_WICR_WTIS_MASK (0x4000U) |
#define | WDOG_WICR_WTIS_SHIFT (14U) |
#define | WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) |
#define | WDOG_WICR_WIE_MASK (0x8000U) |
#define | WDOG_WICR_WIE_SHIFT (15U) |
#define | WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) |
WMCR - Watchdog Miscellaneous Control Register | |
#define | WDOG_WMCR_PDE_MASK (0x1U) |
#define | WDOG_WMCR_PDE_SHIFT (0U) |
#define | WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) |
WCR - Watchdog Control Register | |
#define | WDOG_WCR_WDZST_MASK (0x1U) |
#define | WDOG_WCR_WDZST_SHIFT (0U) |
#define | WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) |
#define | WDOG_WCR_WDBG_MASK (0x2U) |
#define | WDOG_WCR_WDBG_SHIFT (1U) |
#define | WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) |
#define | WDOG_WCR_WDE_MASK (0x4U) |
#define | WDOG_WCR_WDE_SHIFT (2U) |
#define | WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) |
#define | WDOG_WCR_WDT_MASK (0x8U) |
#define | WDOG_WCR_WDT_SHIFT (3U) |
#define | WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) |
#define | WDOG_WCR_SRS_MASK (0x10U) |
#define | WDOG_WCR_SRS_SHIFT (4U) |
#define | WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) |
#define | WDOG_WCR_WDA_MASK (0x20U) |
#define | WDOG_WCR_WDA_SHIFT (5U) |
#define | WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) |
#define | WDOG_WCR_SRE_MASK (0x40U) |
#define | WDOG_WCR_SRE_SHIFT (6U) |
#define | WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) |
#define | WDOG_WCR_WDW_MASK (0x80U) |
#define | WDOG_WCR_WDW_SHIFT (7U) |
#define | WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) |
#define | WDOG_WCR_WT_MASK (0xFF00U) |
#define | WDOG_WCR_WT_SHIFT (8U) |
#define | WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) |
WSR - Watchdog Service Register | |
#define | WDOG_WSR_WSR_MASK (0xFFFFU) |
#define | WDOG_WSR_WSR_SHIFT (0U) |
#define | WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) |
WRSR - Watchdog Reset Status Register | |
#define | WDOG_WRSR_SFTW_MASK (0x1U) |
#define | WDOG_WRSR_SFTW_SHIFT (0U) |
#define | WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) |
#define | WDOG_WRSR_TOUT_MASK (0x2U) |
#define | WDOG_WRSR_TOUT_SHIFT (1U) |
#define | WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) |
#define | WDOG_WRSR_POR_MASK (0x10U) |
#define | WDOG_WRSR_POR_SHIFT (4U) |
#define | WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) |
WICR - Watchdog Interrupt Control Register | |
#define | WDOG_WICR_WICT_MASK (0xFFU) |
#define | WDOG_WICR_WICT_SHIFT (0U) |
#define | WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) |
#define | WDOG_WICR_WTIS_MASK (0x4000U) |
#define | WDOG_WICR_WTIS_SHIFT (14U) |
#define | WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) |
#define | WDOG_WICR_WIE_MASK (0x8000U) |
#define | WDOG_WICR_WIE_SHIFT (15U) |
#define | WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) |
WMCR - Watchdog Miscellaneous Control Register | |
#define | WDOG_WMCR_PDE_MASK (0x1U) |
#define | WDOG_WMCR_PDE_SHIFT (0U) |
#define | WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) |
WCR - Watchdog Control Register | |
#define | WDOG_WCR_WDZST_MASK (0x1U) |
#define | WDOG_WCR_WDZST_SHIFT (0U) |
#define | WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) |
#define | WDOG_WCR_WDBG_MASK (0x2U) |
#define | WDOG_WCR_WDBG_SHIFT (1U) |
#define | WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) |
#define | WDOG_WCR_WDE_MASK (0x4U) |
#define | WDOG_WCR_WDE_SHIFT (2U) |
#define | WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) |
#define | WDOG_WCR_WDT_MASK (0x8U) |
#define | WDOG_WCR_WDT_SHIFT (3U) |
#define | WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) |
#define | WDOG_WCR_SRS_MASK (0x10U) |
#define | WDOG_WCR_SRS_SHIFT (4U) |
#define | WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) |
#define | WDOG_WCR_WDA_MASK (0x20U) |
#define | WDOG_WCR_WDA_SHIFT (5U) |
#define | WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) |
#define | WDOG_WCR_SRE_MASK (0x40U) |
#define | WDOG_WCR_SRE_SHIFT (6U) |
#define | WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) |
#define | WDOG_WCR_WDW_MASK (0x80U) |
#define | WDOG_WCR_WDW_SHIFT (7U) |
#define | WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) |
#define | WDOG_WCR_WT_MASK (0xFF00U) |
#define | WDOG_WCR_WT_SHIFT (8U) |
#define | WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) |
WSR - Watchdog Service Register | |
#define | WDOG_WSR_WSR_MASK (0xFFFFU) |
#define | WDOG_WSR_WSR_SHIFT (0U) |
#define | WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) |
WRSR - Watchdog Reset Status Register | |
#define | WDOG_WRSR_SFTW_MASK (0x1U) |
#define | WDOG_WRSR_SFTW_SHIFT (0U) |
#define | WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) |
#define | WDOG_WRSR_TOUT_MASK (0x2U) |
#define | WDOG_WRSR_TOUT_SHIFT (1U) |
#define | WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) |
#define | WDOG_WRSR_POR_MASK (0x10U) |
#define | WDOG_WRSR_POR_SHIFT (4U) |
#define | WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) |
WICR - Watchdog Interrupt Control Register | |
#define | WDOG_WICR_WICT_MASK (0xFFU) |
#define | WDOG_WICR_WICT_SHIFT (0U) |
#define | WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) |
#define | WDOG_WICR_WTIS_MASK (0x4000U) |
#define | WDOG_WICR_WTIS_SHIFT (14U) |
#define | WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) |
#define | WDOG_WICR_WIE_MASK (0x8000U) |
#define | WDOG_WICR_WIE_SHIFT (15U) |
#define | WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) |
WMCR - Watchdog Miscellaneous Control Register | |
#define | WDOG_WMCR_PDE_MASK (0x1U) |
#define | WDOG_WMCR_PDE_SHIFT (0U) |
#define | WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) |
#define WDOG_WCR_SRE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) |
SRE - software reset extension, an option way to generate software reset 0b0..using original way to generate software reset (default) 0b1..using new way to generate software reset.
#define WDOG_WCR_SRE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) |
SRE - Software Reset Extension, an optional way to generate software reset 0b0..using original way to generate software reset (default) 0b1..using new way to generate software reset.
#define WDOG_WCR_SRE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) |
SRE - Software Reset Extension, an optional way to generate software reset 0b0..using original way to generate software reset (default) 0b1..using new way to generate software reset.
#define WDOG_WCR_SRS | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) |
SRS - SRS 0b0..Assert system reset signal. 0b1..No effect on the system (Default).
#define WDOG_WCR_SRS | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) |
SRS - SRS 0b0..Assert system reset signal. 0b1..No effect on the system (Default).
#define WDOG_WCR_SRS | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) |
SRS - SRS 0b0..Assert system reset signal. 0b1..No effect on the system (Default).
#define WDOG_WCR_WDA | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) |
WDA - WDA 0b0..Assert WDOG_B output. 0b1..No effect on system (Default).
#define WDOG_WCR_WDA | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) |
WDA - WDA 0b0..Assert WDOG_B output. 0b1..No effect on system (Default).
#define WDOG_WCR_WDA | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) |
WDA - WDA 0b0..Assert WDOG_B output. 0b1..No effect on system (Default).
#define WDOG_WCR_WDBG | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) |
WDBG - WDBG 0b0..Continue WDOG timer operation (Default). 0b1..Suspend the watchdog timer.
#define WDOG_WCR_WDBG | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) |
WDBG - WDBG 0b0..Continue WDOG timer operation (Default). 0b1..Suspend the watchdog timer.
#define WDOG_WCR_WDBG | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) |
WDBG - WDBG 0b0..Continue WDOG timer operation (Default). 0b1..Suspend the watchdog timer.
#define WDOG_WCR_WDE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) |
WDE - WDE 0b0..Disable the Watchdog (Default). 0b1..Enable the Watchdog.
#define WDOG_WCR_WDE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) |
WDE - WDE 0b0..Disable the Watchdog (Default). 0b1..Enable the Watchdog.
#define WDOG_WCR_WDE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) |
WDE - WDE 0b0..Disable the Watchdog (Default). 0b1..Enable the Watchdog.
#define WDOG_WCR_WDT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) |
WDT - WDT 0b0..No effect on WDOG_B (Default). 0b1..Assert WDOG_B upon a Watchdog Time-out event.
#define WDOG_WCR_WDT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) |
WDT - WDT 0b0..No effect on WDOG_B (Default). 0b1..Assert WDOG_B upon a Watchdog Time-out event.
#define WDOG_WCR_WDT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) |
WDT - WDT 0b0..No effect on WDOG_B (Default). 0b1..Assert WDOG_B upon a Watchdog Time-out event.
#define WDOG_WCR_WDW | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) |
WDW - WDW 0b0..Continue WDOG timer operation (Default). 0b1..Suspend WDOG timer operation.
#define WDOG_WCR_WDW | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) |
WDW - WDW 0b0..Continue WDOG timer operation (Default). 0b1..Suspend WDOG timer operation.
#define WDOG_WCR_WDW | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) |
WDW - WDW 0b0..Continue WDOG timer operation (Default). 0b1..Suspend WDOG timer operation.
#define WDOG_WCR_WDZST | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) |
WDZST - WDZST 0b0..Continue timer operation (Default). 0b1..Suspend the watchdog timer.
#define WDOG_WCR_WDZST | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) |
WDZST - WDZST 0b0..Continue timer operation (Default). 0b1..Suspend the watchdog timer.
#define WDOG_WCR_WDZST | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) |
WDZST - WDZST 0b0..Continue timer operation (Default). 0b1..Suspend the watchdog timer.
#define WDOG_WCR_WT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) |
WT - WT 0b00000000..- 0.5 Seconds (Default). 0b00000001..- 1.0 Seconds. 0b00000010..- 1.5 Seconds. 0b00000011..- 2.0 Seconds. 0b11111111..- 128 Seconds.
#define WDOG_WCR_WT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) |
WT - WT 0b00000000..- 0.5 Seconds (Default). 0b00000001..- 1.0 Seconds. 0b00000010..- 1.5 Seconds. 0b00000011..- 2.0 Seconds. 0b11111111..- 128 Seconds.
#define WDOG_WCR_WT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) |
WT - WT 0b00000000..- 0.5 Seconds (Default). 0b00000001..- 1.0 Seconds. 0b00000010..- 1.5 Seconds. 0b00000011..- 2.0 Seconds. 0b11111111..- 128 Seconds.
#define WDOG_WICR_WICT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) |
WICT - WICT 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
#define WDOG_WICR_WICT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) |
WICT - WICT 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
#define WDOG_WICR_WICT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) |
WICT - WICT 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
#define WDOG_WICR_WIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) |
WIE - WIE 0b0..Disable Interrupt (Default). 0b1..Enable Interrupt.
#define WDOG_WICR_WIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) |
WIE - WIE 0b0..Disable Interrupt (Default). 0b1..Enable Interrupt.
#define WDOG_WICR_WIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) |
WIE - WIE 0b0..Disable Interrupt (Default). 0b1..Enable Interrupt.
#define WDOG_WICR_WTIS | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) |
WTIS - WTIS 0b0..No interrupt has occurred (Default). 0b1..Interrupt has occurred
#define WDOG_WICR_WTIS | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) |
WTIS - WTIS 0b0..No interrupt has occurred (Default). 0b1..Interrupt has occurred
#define WDOG_WICR_WTIS | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) |
WTIS - WTIS 0b0..No interrupt has occurred (Default). 0b1..Interrupt has occurred
#define WDOG_WMCR_PDE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) |
PDE - PDE 0b0..Power Down Counter of WDOG is disabled. 0b1..Power Down Counter of WDOG is enabled (Default).
#define WDOG_WMCR_PDE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) |
PDE - PDE 0b0..Power Down Counter of WDOG is disabled. 0b1..Power Down Counter of WDOG is enabled (Default).
#define WDOG_WMCR_PDE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) |
PDE - PDE 0b0..Power Down Counter of WDOG is disabled. 0b1..Power Down Counter of WDOG is enabled (Default).
#define WDOG_WRSR_POR | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) |
POR - POR 0b0..Reset is not the result of a power on reset. 0b1..Reset is the result of a power on reset.
#define WDOG_WRSR_POR | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) |
POR - POR 0b0..Reset is not the result of a power on reset. 0b1..Reset is the result of a power on reset.
#define WDOG_WRSR_POR | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) |
POR - POR 0b0..Reset is not the result of a power on reset. 0b1..Reset is the result of a power on reset.
#define WDOG_WRSR_SFTW | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) |
SFTW - SFTW 0b0..Reset is not the result of a software reset. 0b1..Reset is the result of a software reset.
#define WDOG_WRSR_SFTW | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) |
SFTW - SFTW 0b0..Reset is not the result of a software reset. 0b1..Reset is the result of a software reset.
#define WDOG_WRSR_SFTW | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) |
SFTW - SFTW 0b0..Reset is not the result of a software reset. 0b1..Reset is the result of a software reset.
#define WDOG_WRSR_TOUT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) |
TOUT - TOUT 0b0..Reset is not the result of a WDOG timeout. 0b1..Reset is the result of a WDOG timeout.
#define WDOG_WRSR_TOUT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) |
TOUT - TOUT 0b0..Reset is not the result of a WDOG timeout. 0b1..Reset is the result of a WDOG timeout.
#define WDOG_WRSR_TOUT | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) |
TOUT - TOUT 0b0..Reset is not the result of a WDOG timeout. 0b1..Reset is the result of a WDOG timeout.
#define WDOG_WSR_WSR | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) |
WSR - WSR 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
#define WDOG_WSR_WSR | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) |
WSR - WSR 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
#define WDOG_WSR_WSR | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) |
WSR - WSR 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).