USBNC Register Masks

USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK   (0x80U)
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT   (7U)
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK   (0x100U)
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT   (8U)
#define	USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)
#define	USBNC_USB_OTGn_CTRL_PWR_POL_MASK   (0x200U)
#define	USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT   (9U)
#define	USBNC_USB_OTGn_CTRL_PWR_POL(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)
#define	USBNC_USB_OTGn_CTRL_WIE_MASK   (0x400U)
#define	USBNC_USB_OTGn_CTRL_WIE_SHIFT   (10U)
#define	USBNC_USB_OTGn_CTRL_WIE(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)
#define	USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK   (0x4000U)
#define	USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT   (14U)
#define	USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)
#define	USBNC_USB_OTGn_CTRL_WKUP_SW_MASK   (0x8000U)
#define	USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT   (15U)
#define	USBNC_USB_OTGn_CTRL_WKUP_SW(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)
#define	USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK   (0x10000U)
#define	USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT   (16U)
#define	USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)
#define	USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK   (0x20000U)
#define	USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT   (17U)
#define	USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)
#define	USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK   (0x20000000U)
#define	USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT   (29U)
#define	USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)
#define	USBNC_USB_OTGn_CTRL_WIR_MASK   (0x80000000U)
#define	USBNC_USB_OTGn_CTRL_WIR_SHIFT   (31U)
#define	USBNC_USB_OTGn_CTRL_WIR(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)

USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register
#define	USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK   (0x80000000U)
#define	USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT   (31U)
#define	USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)

CTRL1 - USB OTG Control 1 Register
#define	USBNC_CTRL1_OVER_CUR_DIS_MASK   (0x80U)
#define	USBNC_CTRL1_OVER_CUR_DIS_SHIFT   (7U)
#define	USBNC_CTRL1_OVER_CUR_DIS(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)
#define	USBNC_CTRL1_OVER_CUR_POL_MASK   (0x100U)
#define	USBNC_CTRL1_OVER_CUR_POL_SHIFT   (8U)
#define	USBNC_CTRL1_OVER_CUR_POL(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)
#define	USBNC_CTRL1_PWR_POL_MASK   (0x200U)
#define	USBNC_CTRL1_PWR_POL_SHIFT   (9U)
#define	USBNC_CTRL1_PWR_POL(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)
#define	USBNC_CTRL1_WIE_MASK   (0x400U)
#define	USBNC_CTRL1_WIE_SHIFT   (10U)
#define	USBNC_CTRL1_WIE(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)
#define	USBNC_CTRL1_WKUP_SW_EN_MASK   (0x4000U)
#define	USBNC_CTRL1_WKUP_SW_EN_SHIFT   (14U)
#define	USBNC_CTRL1_WKUP_SW_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)
#define	USBNC_CTRL1_WKUP_SW_MASK   (0x8000U)
#define	USBNC_CTRL1_WKUP_SW_SHIFT   (15U)
#define	USBNC_CTRL1_WKUP_SW(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)
#define	USBNC_CTRL1_WKUP_ID_EN_MASK   (0x10000U)
#define	USBNC_CTRL1_WKUP_ID_EN_SHIFT   (16U)
#define	USBNC_CTRL1_WKUP_ID_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)
#define	USBNC_CTRL1_WKUP_VBUS_EN_MASK   (0x20000U)
#define	USBNC_CTRL1_WKUP_VBUS_EN_SHIFT   (17U)
#define	USBNC_CTRL1_WKUP_VBUS_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)
#define	USBNC_CTRL1_WKUP_DPDM_EN_MASK   (0x20000000U)
#define	USBNC_CTRL1_WKUP_DPDM_EN_SHIFT   (29U)
#define	USBNC_CTRL1_WKUP_DPDM_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)
#define	USBNC_CTRL1_WIR_MASK   (0x80000000U)
#define	USBNC_CTRL1_WIR_SHIFT   (31U)
#define	USBNC_CTRL1_WIR(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)

CTRL2 - USB OTG Control 2 Register
#define	USBNC_CTRL2_VBUS_SOURCE_SEL_MASK   (0x3U)
#define	USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT   (0U)
#define	USBNC_CTRL2_VBUS_SOURCE_SEL(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)
#define	USBNC_CTRL2_AUTURESUME_EN_MASK   (0x4U)
#define	USBNC_CTRL2_AUTURESUME_EN_SHIFT   (2U)
#define	USBNC_CTRL2_AUTURESUME_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)
#define	USBNC_CTRL2_LOWSPEED_EN_MASK   (0x8U)
#define	USBNC_CTRL2_LOWSPEED_EN_SHIFT   (3U)
#define	USBNC_CTRL2_LOWSPEED_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)
#define	USBNC_CTRL2_UTMI_CLK_VLD_MASK   (0x80000000U)
#define	USBNC_CTRL2_UTMI_CLK_VLD_SHIFT   (31U)
#define	USBNC_CTRL2_UTMI_CLK_VLD(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)

HSIC_CTRL - USB Host HSIC Control Register
#define	USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK   (0x800U)
#define	USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT   (11U)
#define	USBNC_HSIC_CTRL_HSIC_CLK_ON(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK)
#define	USBNC_HSIC_CTRL_HSIC_EN_MASK   (0x1000U)
#define	USBNC_HSIC_CTRL_HSIC_EN_SHIFT   (12U)
#define	USBNC_HSIC_CTRL_HSIC_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK)
#define	USBNC_HSIC_CTRL_CLK_VLD_MASK   (0x80000000U)
#define	USBNC_HSIC_CTRL_CLK_VLD_SHIFT   (31U)
#define	USBNC_HSIC_CTRL_CLK_VLD(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK)

CTRL1 - USB OTG Control 1 Register
#define	USBNC_CTRL1_OVER_CUR_DIS_MASK   (0x80U)
#define	USBNC_CTRL1_OVER_CUR_DIS_SHIFT   (7U)
#define	USBNC_CTRL1_OVER_CUR_DIS(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)
#define	USBNC_CTRL1_OVER_CUR_POL_MASK   (0x100U)
#define	USBNC_CTRL1_OVER_CUR_POL_SHIFT   (8U)
#define	USBNC_CTRL1_OVER_CUR_POL(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)
#define	USBNC_CTRL1_PWR_POL_MASK   (0x200U)
#define	USBNC_CTRL1_PWR_POL_SHIFT   (9U)
#define	USBNC_CTRL1_PWR_POL(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)
#define	USBNC_CTRL1_WIE_MASK   (0x400U)
#define	USBNC_CTRL1_WIE_SHIFT   (10U)
#define	USBNC_CTRL1_WIE(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)
#define	USBNC_CTRL1_WKUP_SW_EN_MASK   (0x4000U)
#define	USBNC_CTRL1_WKUP_SW_EN_SHIFT   (14U)
#define	USBNC_CTRL1_WKUP_SW_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)
#define	USBNC_CTRL1_WKUP_SW_MASK   (0x8000U)
#define	USBNC_CTRL1_WKUP_SW_SHIFT   (15U)
#define	USBNC_CTRL1_WKUP_SW(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)
#define	USBNC_CTRL1_WKUP_ID_EN_MASK   (0x10000U)
#define	USBNC_CTRL1_WKUP_ID_EN_SHIFT   (16U)
#define	USBNC_CTRL1_WKUP_ID_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)
#define	USBNC_CTRL1_WKUP_VBUS_EN_MASK   (0x20000U)
#define	USBNC_CTRL1_WKUP_VBUS_EN_SHIFT   (17U)
#define	USBNC_CTRL1_WKUP_VBUS_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)
#define	USBNC_CTRL1_WKUP_DPDM_EN_MASK   (0x20000000U)
#define	USBNC_CTRL1_WKUP_DPDM_EN_SHIFT   (29U)
#define	USBNC_CTRL1_WKUP_DPDM_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)
#define	USBNC_CTRL1_WIR_MASK   (0x80000000U)
#define	USBNC_CTRL1_WIR_SHIFT   (31U)
#define	USBNC_CTRL1_WIR(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)

CTRL2 - USB OTG Control 2 Register
#define	USBNC_CTRL2_VBUS_SOURCE_SEL_MASK   (0x3U)
#define	USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT   (0U)
#define	USBNC_CTRL2_VBUS_SOURCE_SEL(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)
#define	USBNC_CTRL2_AUTURESUME_EN_MASK   (0x4U)
#define	USBNC_CTRL2_AUTURESUME_EN_SHIFT   (2U)
#define	USBNC_CTRL2_AUTURESUME_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)
#define	USBNC_CTRL2_LOWSPEED_EN_MASK   (0x8U)
#define	USBNC_CTRL2_LOWSPEED_EN_SHIFT   (3U)
#define	USBNC_CTRL2_LOWSPEED_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)
#define	USBNC_CTRL2_UTMI_CLK_VLD_MASK   (0x80000000U)
#define	USBNC_CTRL2_UTMI_CLK_VLD_SHIFT   (31U)
#define	USBNC_CTRL2_UTMI_CLK_VLD(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)

HSIC_CTRL - USB Host HSIC Control Register
#define	USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK   (0x800U)
#define	USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT   (11U)
#define	USBNC_HSIC_CTRL_HSIC_CLK_ON(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK)
#define	USBNC_HSIC_CTRL_HSIC_EN_MASK   (0x1000U)
#define	USBNC_HSIC_CTRL_HSIC_EN_SHIFT   (12U)
#define	USBNC_HSIC_CTRL_HSIC_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK)
#define	USBNC_HSIC_CTRL_CLK_VLD_MASK   (0x80000000U)
#define	USBNC_HSIC_CTRL_CLK_VLD_SHIFT   (31U)
#define	USBNC_HSIC_CTRL_CLK_VLD(x)   (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK)

Detailed Description

Macro Definition Documentation

USBNC_CTRL1_OVER_CUR_DIS [1/2]

#define USBNC_CTRL1_OVER_CUR_DIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)

OVER_CUR_DIS - OVER_CUR_DIS 0b1..Disables overcurrent detection 0b0..Enables overcurrent detection

USBNC_CTRL1_OVER_CUR_DIS [2/2]

#define USBNC_CTRL1_OVER_CUR_DIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)

OVER_CUR_DIS - OVER_CUR_DIS 0b1..Disables overcurrent detection 0b0..Enables overcurrent detection

USBNC_CTRL1_OVER_CUR_POL [1/2]

#define USBNC_CTRL1_OVER_CUR_POL

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)

OVER_CUR_POL - OVER_CUR_POL 0b1..Low active (low on this signal represents an overcurrent condition) 0b0..High active (high on this signal represents an overcurrent condition)

USBNC_CTRL1_OVER_CUR_POL [2/2]

#define USBNC_CTRL1_OVER_CUR_POL

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)

OVER_CUR_POL - OVER_CUR_POL 0b1..Low active (low on this signal represents an overcurrent condition) 0b0..High active (high on this signal represents an overcurrent condition)

USBNC_CTRL1_PWR_POL [1/2]

#define USBNC_CTRL1_PWR_POL

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)

PWR_POL - PWR_POL 0b1..PMIC Power Pin is High active. 0b0..PMIC Power Pin is Low active.

USBNC_CTRL1_PWR_POL [2/2]

#define USBNC_CTRL1_PWR_POL

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)

PWR_POL - PWR_POL 0b1..PMIC Power Pin is High active. 0b0..PMIC Power Pin is Low active.

USBNC_CTRL1_WIE [1/2]

#define USBNC_CTRL1_WIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)

WIE - WIE 0b1..Interrupt Enabled 0b0..Interrupt Disabled

USBNC_CTRL1_WIE [2/2]

#define USBNC_CTRL1_WIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)

WIE - WIE 0b1..Interrupt Enabled 0b0..Interrupt Disabled

USBNC_CTRL1_WIR [1/2]

#define USBNC_CTRL1_WIR

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)

WIR - WIR 0b1..Wake-up Interrupt Request received 0b0..No wake-up interrupt request received

USBNC_CTRL1_WIR [2/2]

#define USBNC_CTRL1_WIR

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)

WIR - WIR 0b1..Wake-up Interrupt Request received 0b0..No wake-up interrupt request received

USBNC_CTRL1_WKUP_DPDM_EN [1/2]

#define USBNC_CTRL1_WKUP_DPDM_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)

WKUP_DPDM_EN - Wake-up on DPDM change enable 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. 0b0..DPDM changes wake-up to be disabled only when VBUS is 0.

USBNC_CTRL1_WKUP_DPDM_EN [2/2]

#define USBNC_CTRL1_WKUP_DPDM_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)

WKUP_DPDM_EN - Wake-up on DPDM change enable 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. 0b0..DPDM changes wake-up to be disabled only when VBUS is 0.

USBNC_CTRL1_WKUP_ID_EN [1/2]

#define USBNC_CTRL1_WKUP_ID_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)

WKUP_ID_EN - WKUP_ID_EN 0b1..Enable 0b0..Disable

USBNC_CTRL1_WKUP_ID_EN [2/2]

#define USBNC_CTRL1_WKUP_ID_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)

WKUP_ID_EN - WKUP_ID_EN 0b1..Enable 0b0..Disable

USBNC_CTRL1_WKUP_SW [1/2]

#define USBNC_CTRL1_WKUP_SW

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)

WKUP_SW - WKUP_SW 0b1..Force wake-up 0b0..Inactive

USBNC_CTRL1_WKUP_SW [2/2]

#define USBNC_CTRL1_WKUP_SW

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)

WKUP_SW - WKUP_SW 0b1..Force wake-up 0b0..Inactive

USBNC_CTRL1_WKUP_SW_EN [1/2]

#define USBNC_CTRL1_WKUP_SW_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)

WKUP_SW_EN - WKUP_SW_EN 0b1..Enable 0b0..Disable

USBNC_CTRL1_WKUP_SW_EN [2/2]

#define USBNC_CTRL1_WKUP_SW_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)

WKUP_SW_EN - WKUP_SW_EN 0b1..Enable 0b0..Disable

USBNC_CTRL1_WKUP_VBUS_EN [1/2]

#define USBNC_CTRL1_WKUP_VBUS_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)

WKUP_VBUS_EN - WKUP_VBUS_EN 0b1..Enable 0b0..Disable

USBNC_CTRL1_WKUP_VBUS_EN [2/2]

#define USBNC_CTRL1_WKUP_VBUS_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)

WKUP_VBUS_EN - WKUP_VBUS_EN 0b1..Enable 0b0..Disable

USBNC_CTRL2_AUTURESUME_EN [1/2]

#define USBNC_CTRL2_AUTURESUME_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)

AUTURESUME_EN - Auto Resume Enable 0b0..Default

USBNC_CTRL2_AUTURESUME_EN [2/2]

#define USBNC_CTRL2_AUTURESUME_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)

AUTURESUME_EN - Auto Resume Enable 0b0..Default

USBNC_CTRL2_LOWSPEED_EN [1/2]

#define USBNC_CTRL2_LOWSPEED_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)

LOWSPEED_EN - LOWSPEED_EN 0b0..Default

USBNC_CTRL2_LOWSPEED_EN [2/2]

#define USBNC_CTRL2_LOWSPEED_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)

LOWSPEED_EN - LOWSPEED_EN 0b0..Default

USBNC_CTRL2_UTMI_CLK_VLD [1/2]

#define USBNC_CTRL2_UTMI_CLK_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)

UTMI_CLK_VLD - UTMI_CLK_VLD 0b0..Default

USBNC_CTRL2_UTMI_CLK_VLD [2/2]

#define USBNC_CTRL2_UTMI_CLK_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)

UTMI_CLK_VLD - UTMI_CLK_VLD 0b0..Default

USBNC_CTRL2_VBUS_SOURCE_SEL [1/2]

#define USBNC_CTRL2_VBUS_SOURCE_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)

VBUS_SOURCE_SEL - VBUS_SOURCE_SEL 0b00..vbus_valid 0b01..sess_valid 0b10..sess_valid 0b11..sess_valid

USBNC_CTRL2_VBUS_SOURCE_SEL [2/2]

#define USBNC_CTRL2_VBUS_SOURCE_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)

VBUS_SOURCE_SEL - VBUS_SOURCE_SEL 0b00..vbus_valid 0b01..sess_valid 0b10..sess_valid 0b11..sess_valid

USBNC_HSIC_CTRL_CLK_VLD [1/2]

#define USBNC_HSIC_CTRL_CLK_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK)

CLK_VLD - CLK_VLD 0b1..Valid 0b0..Invalid

USBNC_HSIC_CTRL_CLK_VLD [2/2]

#define USBNC_HSIC_CTRL_CLK_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK)

CLK_VLD - CLK_VLD 0b1..Valid 0b0..Invalid

USBNC_HSIC_CTRL_HSIC_CLK_ON [1/2]

#define USBNC_HSIC_CTRL_HSIC_CLK_ON

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK)

HSIC_CLK_ON - HSIC_CLK_ON 0b1..Active 0b0..Inactive

USBNC_HSIC_CTRL_HSIC_CLK_ON [2/2]

#define USBNC_HSIC_CTRL_HSIC_CLK_ON

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK)

HSIC_CLK_ON - HSIC_CLK_ON 0b1..Active 0b0..Inactive

USBNC_HSIC_CTRL_HSIC_EN [1/2]

#define USBNC_HSIC_CTRL_HSIC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK)

HSIC_EN - HSIC_EN 0b1..Enabled 0b0..Disabled

USBNC_HSIC_CTRL_HSIC_EN [2/2]

#define USBNC_HSIC_CTRL_HSIC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK)

HSIC_EN - HSIC_EN 0b1..Enabled 0b0..Disabled

USBNC_USB_OTGn_CTRL_OVER_CUR_DIS

#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)

OVER_CUR_DIS 0b1..Disables overcurrent detection 0b0..Enables overcurrent detection

USBNC_USB_OTGn_CTRL_OVER_CUR_POL

#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)

OVER_CUR_POL 0b1..Low active (low on this signal represents an overcurrent condition) 0b0..High active (high on this signal represents an overcurrent condition)

USBNC_USB_OTGn_CTRL_PWR_POL

#define USBNC_USB_OTGn_CTRL_PWR_POL

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)

PWR_POL 0b1..PMIC Power Pin is High active. 0b0..PMIC Power Pin is Low active.

USBNC_USB_OTGn_CTRL_WIE

#define USBNC_USB_OTGn_CTRL_WIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)

WIE 0b1..Interrupt Enabled 0b0..Interrupt Disabled

USBNC_USB_OTGn_CTRL_WIR

#define USBNC_USB_OTGn_CTRL_WIR

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)

WIR 0b1..Wake-up Interrupt Request received 0b0..No wake-up interrupt request received

USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN

#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)

WKUP_DPDM_EN 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. 0b0..DPDM changes wake-up to be disabled only when VBUS is 0.

USBNC_USB_OTGn_CTRL_WKUP_ID_EN

#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)

WKUP_ID_EN 0b1..Enable 0b0..Disable

USBNC_USB_OTGn_CTRL_WKUP_SW

#define USBNC_USB_OTGn_CTRL_WKUP_SW

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)

WKUP_SW 0b1..Force wake-up 0b0..Inactive

USBNC_USB_OTGn_CTRL_WKUP_SW_EN

#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)

WKUP_SW_EN 0b1..Enable 0b0..Disable

USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN

#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)

WKUP_VBUS_EN 0b1..Enable 0b0..Disable

USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD

#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)

UTMI_CLK_VLD 0b1..Valid 0b0..Invalid