Macros
#define	TRNG_ENT_COUNT (16U)

MCTL - Miscellaneous Control Register
#define	TRNG_MCTL_SAMP_MODE_MASK (0x3U)

#define	TRNG_MCTL_SAMP_MODE_SHIFT (0U)

#define	TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)

#define	TRNG_MCTL_OSC_DIV_MASK (0xCU)

#define	TRNG_MCTL_OSC_DIV_SHIFT (2U)

#define	TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)

#define	TRNG_MCTL_UNUSED4_MASK (0x10U)

#define	TRNG_MCTL_UNUSED4_SHIFT (4U)

#define	TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)

#define	TRNG_MCTL_UNUSED5_MASK (0x20U)

#define	TRNG_MCTL_UNUSED5_SHIFT (5U)

#define	TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)

#define	TRNG_MCTL_RST_DEF_MASK (0x40U)

#define	TRNG_MCTL_RST_DEF_SHIFT (6U)

#define	TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)

#define	TRNG_MCTL_FOR_SCLK_MASK (0x80U)

#define	TRNG_MCTL_FOR_SCLK_SHIFT (7U)

#define	TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)

#define	TRNG_MCTL_FCT_FAIL_MASK (0x100U)

#define	TRNG_MCTL_FCT_FAIL_SHIFT (8U)

#define	TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)

#define	TRNG_MCTL_FCT_VAL_MASK (0x200U)

#define	TRNG_MCTL_FCT_VAL_SHIFT (9U)

#define	TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)

#define	TRNG_MCTL_ENT_VAL_MASK (0x400U)

#define	TRNG_MCTL_ENT_VAL_SHIFT (10U)

#define	TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)

#define	TRNG_MCTL_TST_OUT_MASK (0x800U)

#define	TRNG_MCTL_TST_OUT_SHIFT (11U)

#define	TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)

#define	TRNG_MCTL_ERR_MASK (0x1000U)

#define	TRNG_MCTL_ERR_SHIFT (12U)

#define	TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)

#define	TRNG_MCTL_TSTOP_OK_MASK (0x2000U)

#define	TRNG_MCTL_TSTOP_OK_SHIFT (13U)

#define	TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)

#define	TRNG_MCTL_LRUN_CONT_MASK (0x4000U)

#define	TRNG_MCTL_LRUN_CONT_SHIFT (14U)

#define	TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)

#define	TRNG_MCTL_PRGM_MASK (0x10000U)

#define	TRNG_MCTL_PRGM_SHIFT (16U)

#define	TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)

SCMISC - Statistical Check Miscellaneous Register
#define	TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)

#define	TRNG_SCMISC_LRUN_MAX_SHIFT (0U)

#define	TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)

#define	TRNG_SCMISC_RTY_CT_MASK (0xF0000U)

#define	TRNG_SCMISC_RTY_CT_SHIFT (16U)

#define	TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)

PKRRNG - Poker Range Register
#define	TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)

#define	TRNG_PKRRNG_PKR_RNG_SHIFT (0U)

#define	TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)

PKRMAX - Poker Maximum Limit Register
#define	TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)

#define	TRNG_PKRMAX_PKR_MAX_SHIFT (0U)

#define	TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)

PKRSQ - Poker Square Calculation Result Register
#define	TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)

#define	TRNG_PKRSQ_PKR_SQ_SHIFT (0U)

#define	TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)

SDCTL - Seed Control Register
#define	TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)

#define	TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)

#define	TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)

#define	TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)

#define	TRNG_SDCTL_ENT_DLY_SHIFT (16U)

#define	TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)

SBLIM - Sparse Bit Limit Register
#define	TRNG_SBLIM_SB_LIM_MASK (0x3FFU)

#define	TRNG_SBLIM_SB_LIM_SHIFT (0U)

#define	TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)

TOTSAM - Total Samples Register
#define	TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)

#define	TRNG_TOTSAM_TOT_SAM_SHIFT (0U)

#define	TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)

FRQMIN - Frequency Count Minimum Limit Register
#define	TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)

#define	TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)

#define	TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)

FRQCNT - Frequency Count Register
#define	TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)

#define	TRNG_FRQCNT_FRQ_CT_SHIFT (0U)

#define	TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)

FRQMAX - Frequency Count Maximum Limit Register
#define	TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)

#define	TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)

#define	TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)

SCMC - Statistical Check Monobit Count Register
#define	TRNG_SCMC_MONO_CT_MASK (0xFFFFU)

#define	TRNG_SCMC_MONO_CT_SHIFT (0U)

#define	TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)

SCML - Statistical Check Monobit Limit Register
#define	TRNG_SCML_MONO_MAX_MASK (0xFFFFU)

#define	TRNG_SCML_MONO_MAX_SHIFT (0U)

#define	TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)

#define	TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)

#define	TRNG_SCML_MONO_RNG_SHIFT (16U)

#define	TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)

SCR1C - Statistical Check Run Length 1 Count Register
#define	TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)

#define	TRNG_SCR1C_R1_0_CT_SHIFT (0U)

#define	TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)

#define	TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)

#define	TRNG_SCR1C_R1_1_CT_SHIFT (16U)

#define	TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)

SCR1L - Statistical Check Run Length 1 Limit Register
#define	TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)

#define	TRNG_SCR1L_RUN1_MAX_SHIFT (0U)

#define	TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)

#define	TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)

#define	TRNG_SCR1L_RUN1_RNG_SHIFT (16U)

#define	TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)

SCR2C - Statistical Check Run Length 2 Count Register
#define	TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)

#define	TRNG_SCR2C_R2_0_CT_SHIFT (0U)

#define	TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)

#define	TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)

#define	TRNG_SCR2C_R2_1_CT_SHIFT (16U)

#define	TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)

SCR2L - Statistical Check Run Length 2 Limit Register
#define	TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)

#define	TRNG_SCR2L_RUN2_MAX_SHIFT (0U)

#define	TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)

#define	TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)

#define	TRNG_SCR2L_RUN2_RNG_SHIFT (16U)

#define	TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)

SCR3C - Statistical Check Run Length 3 Count Register
#define	TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)

#define	TRNG_SCR3C_R3_0_CT_SHIFT (0U)

#define	TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)

#define	TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)

#define	TRNG_SCR3C_R3_1_CT_SHIFT (16U)

#define	TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)

SCR3L - Statistical Check Run Length 3 Limit Register
#define	TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)

#define	TRNG_SCR3L_RUN3_MAX_SHIFT (0U)

#define	TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)

#define	TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)

#define	TRNG_SCR3L_RUN3_RNG_SHIFT (16U)

#define	TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)

SCR4C - Statistical Check Run Length 4 Count Register
#define	TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)

#define	TRNG_SCR4C_R4_0_CT_SHIFT (0U)

#define	TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)

#define	TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)

#define	TRNG_SCR4C_R4_1_CT_SHIFT (16U)

#define	TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)

SCR4L - Statistical Check Run Length 4 Limit Register
#define	TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)

#define	TRNG_SCR4L_RUN4_MAX_SHIFT (0U)

#define	TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)

#define	TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)

#define	TRNG_SCR4L_RUN4_RNG_SHIFT (16U)

#define	TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)

SCR5C - Statistical Check Run Length 5 Count Register
#define	TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)

#define	TRNG_SCR5C_R5_0_CT_SHIFT (0U)

#define	TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)

#define	TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)

#define	TRNG_SCR5C_R5_1_CT_SHIFT (16U)

#define	TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)

SCR5L - Statistical Check Run Length 5 Limit Register
#define	TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)

#define	TRNG_SCR5L_RUN5_MAX_SHIFT (0U)

#define	TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)

#define	TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)

#define	TRNG_SCR5L_RUN5_RNG_SHIFT (16U)

#define	TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)

SCR6PC - Statistical Check Run Length 6+ Count Register
#define	TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)

#define	TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)

#define	TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)

#define	TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)

#define	TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)

#define	TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)

SCR6PL - Statistical Check Run Length 6+ Limit Register
#define	TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)

#define	TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)

#define	TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)

#define	TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)

#define	TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)

#define	TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)

STATUS - Status Register
#define	TRNG_STATUS_TF1BR0_MASK (0x1U)

#define	TRNG_STATUS_TF1BR0_SHIFT (0U)

#define	TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)

#define	TRNG_STATUS_TF1BR1_MASK (0x2U)

#define	TRNG_STATUS_TF1BR1_SHIFT (1U)

#define	TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)

#define	TRNG_STATUS_TF2BR0_MASK (0x4U)

#define	TRNG_STATUS_TF2BR0_SHIFT (2U)

#define	TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)

#define	TRNG_STATUS_TF2BR1_MASK (0x8U)

#define	TRNG_STATUS_TF2BR1_SHIFT (3U)

#define	TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)

#define	TRNG_STATUS_TF3BR0_MASK (0x10U)

#define	TRNG_STATUS_TF3BR0_SHIFT (4U)

#define	TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)

#define	TRNG_STATUS_TF3BR1_MASK (0x20U)

#define	TRNG_STATUS_TF3BR1_SHIFT (5U)

#define	TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)

#define	TRNG_STATUS_TF4BR0_MASK (0x40U)

#define	TRNG_STATUS_TF4BR0_SHIFT (6U)

#define	TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)

#define	TRNG_STATUS_TF4BR1_MASK (0x80U)

#define	TRNG_STATUS_TF4BR1_SHIFT (7U)

#define	TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)

#define	TRNG_STATUS_TF5BR0_MASK (0x100U)

#define	TRNG_STATUS_TF5BR0_SHIFT (8U)

#define	TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)

#define	TRNG_STATUS_TF5BR1_MASK (0x200U)

#define	TRNG_STATUS_TF5BR1_SHIFT (9U)

#define	TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)

#define	TRNG_STATUS_TF6PBR0_MASK (0x400U)

#define	TRNG_STATUS_TF6PBR0_SHIFT (10U)

#define	TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)

#define	TRNG_STATUS_TF6PBR1_MASK (0x800U)

#define	TRNG_STATUS_TF6PBR1_SHIFT (11U)

#define	TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)

#define	TRNG_STATUS_TFSB_MASK (0x1000U)

#define	TRNG_STATUS_TFSB_SHIFT (12U)

#define	TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)

#define	TRNG_STATUS_TFLR_MASK (0x2000U)

#define	TRNG_STATUS_TFLR_SHIFT (13U)

#define	TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)

#define	TRNG_STATUS_TFP_MASK (0x4000U)

#define	TRNG_STATUS_TFP_SHIFT (14U)

#define	TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)

#define	TRNG_STATUS_TFMB_MASK (0x8000U)

#define	TRNG_STATUS_TFMB_SHIFT (15U)

#define	TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)

#define	TRNG_STATUS_RETRY_CT_MASK (0xF0000U)

#define	TRNG_STATUS_RETRY_CT_SHIFT (16U)

#define	TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)

ENT - Entropy Read Register
#define	TRNG_ENT_ENT_MASK (0xFFFFFFFFU)

#define	TRNG_ENT_ENT_SHIFT (0U)

#define	TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)

PKRCNT10 - Statistical Check Poker Count 1 and 0 Register
#define	TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)

#define	TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)

#define	TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)

#define	TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)

#define	TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)

#define	TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)

PKRCNT32 - Statistical Check Poker Count 3 and 2 Register
#define	TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)

#define	TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)

#define	TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)

#define	TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)

#define	TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)

#define	TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)

PKRCNT54 - Statistical Check Poker Count 5 and 4 Register
#define	TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)

#define	TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)

#define	TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)

#define	TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)

#define	TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)

#define	TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)

PKRCNT76 - Statistical Check Poker Count 7 and 6 Register
#define	TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)

#define	TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)

#define	TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)

#define	TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)

#define	TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)

#define	TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)

PKRCNT98 - Statistical Check Poker Count 9 and 8 Register
#define	TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)

#define	TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)

#define	TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)

#define	TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)

#define	TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)

#define	TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)

PKRCNTBA - Statistical Check Poker Count B and A Register
#define	TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)

#define	TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)

#define	TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)

#define	TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)

#define	TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)

#define	TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)

PKRCNTDC - Statistical Check Poker Count D and C Register
#define	TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)

#define	TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)

#define	TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)

#define	TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)

#define	TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)

#define	TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)

PKRCNTFE - Statistical Check Poker Count F and E Register
#define	TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)

#define	TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)

#define	TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)

#define	TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)

#define	TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)

#define	TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)

SEC_CFG - Security Configuration Register
#define	TRNG_SEC_CFG_SH0_MASK (0x1U)

#define	TRNG_SEC_CFG_SH0_SHIFT (0U)

#define	TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)

#define	TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)

#define	TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)

#define	TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)

#define	TRNG_SEC_CFG_SK_VAL_MASK (0x4U)

#define	TRNG_SEC_CFG_SK_VAL_SHIFT (2U)

#define	TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)

INT_CTRL - Interrupt Control Register
#define	TRNG_INT_CTRL_HW_ERR_MASK (0x1U)

#define	TRNG_INT_CTRL_HW_ERR_SHIFT (0U)

#define	TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)

#define	TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)

#define	TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)

#define	TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)

#define	TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)

#define	TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)

#define	TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)

#define	TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)

#define	TRNG_INT_CTRL_UNUSED_SHIFT (3U)

#define	TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)

INT_MASK - Mask Register
#define	TRNG_INT_MASK_HW_ERR_MASK (0x1U)

#define	TRNG_INT_MASK_HW_ERR_SHIFT (0U)

#define	TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)

#define	TRNG_INT_MASK_ENT_VAL_MASK (0x2U)

#define	TRNG_INT_MASK_ENT_VAL_SHIFT (1U)

#define	TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)

#define	TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)

#define	TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)

#define	TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)

INT_STATUS - Interrupt Status Register
#define	TRNG_INT_STATUS_HW_ERR_MASK (0x1U)

#define	TRNG_INT_STATUS_HW_ERR_SHIFT (0U)

#define	TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)

#define	TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)

#define	TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)

#define	TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)

#define	TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)

#define	TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)

#define	TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)

VID1 - Version ID Register (MS)
#define	TRNG_VID1_MIN_REV_MASK (0xFFU)

#define	TRNG_VID1_MIN_REV_SHIFT (0U)

#define	TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)

#define	TRNG_VID1_MAJ_REV_MASK (0xFF00U)

#define	TRNG_VID1_MAJ_REV_SHIFT (8U)

#define	TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)

#define	TRNG_VID1_IP_ID_MASK (0xFFFF0000U)

#define	TRNG_VID1_IP_ID_SHIFT (16U)

#define	TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)

VID2 - Version ID Register (LS)
#define	TRNG_VID2_CONFIG_OPT_MASK (0xFFU)

#define	TRNG_VID2_CONFIG_OPT_SHIFT (0U)

#define	TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)

#define	TRNG_VID2_ECO_REV_MASK (0xFF00U)

#define	TRNG_VID2_ECO_REV_SHIFT (8U)

#define	TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)

#define	TRNG_VID2_INTG_OPT_MASK (0xFF0000U)

#define	TRNG_VID2_INTG_OPT_SHIFT (16U)

#define	TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)

#define	TRNG_VID2_ERA_MASK (0xFF000000U)

#define	TRNG_VID2_ERA_SHIFT (24U)

#define	TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)

Detailed Description

Macro Definition Documentation

◆ TRNG_INT_CTRL_ENT_VAL

#define TRNG_INT_CTRL_ENT_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)

ENT_VAL 0b0..Same behavior as bit 0 above. 0b1..Same behavior as bit 0 above.

◆ TRNG_INT_CTRL_FRQ_CT_FAIL

#define TRNG_INT_CTRL_FRQ_CT_FAIL ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)

FRQ_CT_FAIL 0b0..Same behavior as bit 0 above. 0b1..Same behavior as bit 0 above.

◆ TRNG_INT_CTRL_HW_ERR

#define TRNG_INT_CTRL_HW_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)

HW_ERR 0b0..Corresponding bit of INT_STATUS cleared. 0b1..Corresponding bit of INT_STATUS active.

◆ TRNG_INT_MASK_ENT_VAL

#define TRNG_INT_MASK_ENT_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)

ENT_VAL 0b0..Same behavior as bit 0 above. 0b1..Same behavior as bit 0 above.

◆ TRNG_INT_MASK_FRQ_CT_FAIL

#define TRNG_INT_MASK_FRQ_CT_FAIL ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)

FRQ_CT_FAIL 0b0..Same behavior as bit 0 above. 0b1..Same behavior as bit 0 above.

◆ TRNG_INT_MASK_HW_ERR

#define TRNG_INT_MASK_HW_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)

HW_ERR 0b0..Corresponding interrupt of INT_STATUS is masked. 0b1..Corresponding bit of INT_STATUS is active.

◆ TRNG_INT_STATUS_ENT_VAL

#define TRNG_INT_STATUS_ENT_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)

ENT_VAL 0b0..Busy generation entropy. Any value read is invalid. 0b1..TRNG can be stopped and entropy is valid if read.

◆ TRNG_INT_STATUS_FRQ_CT_FAIL

#define TRNG_INT_STATUS_FRQ_CT_FAIL ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)

FRQ_CT_FAIL 0b0..No hardware nor self test frequency errors. 0b1..The frequency counter has detected a failure.

◆ TRNG_INT_STATUS_HW_ERR

#define TRNG_INT_STATUS_HW_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)

HW_ERR 0b0..no error 0b1..error detected.

◆ TRNG_MCTL_OSC_DIV

#define TRNG_MCTL_OSC_DIV ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)

OSC_DIV 0b00..use ring oscillator with no divide 0b01..use ring oscillator divided-by-2 0b10..use ring oscillator divided-by-4 0b11..use ring oscillator divided-by-8

◆ TRNG_MCTL_SAMP_MODE

#define TRNG_MCTL_SAMP_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)

SAMP_MODE 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker 0b01..use raw data into both Entropy shifter and Statistical Checker 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker 0b11..undefined/reserved.

◆ TRNG_PKRMAX_PKR_MAX

#define TRNG_PKRMAX_PKR_MAX ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)

PKR_MAX - Poker Maximum Limit.

◆ TRNG_PKRSQ_PKR_SQ

#define TRNG_PKRSQ_PKR_SQ ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)

PKR_SQ - Poker Square Calculation Result.

◆ TRNG_SEC_CFG_NO_PRGM

#define TRNG_SEC_CFG_NO_PRGM ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)

NO_PRGM 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming.

◆ TRNG_SEC_CFG_SH0

#define TRNG_SEC_CFG_SH0 ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)

SH0 0b0..See DRNG version. 0b1..See DRNG version.

◆ TRNG_SEC_CFG_SK_VAL

#define TRNG_SEC_CFG_SK_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)

SK_VAL 0b0..See DRNG version. 0b1..See DRNG version.

◆ TRNG_VID1_IP_ID

#define TRNG_VID1_IP_ID ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)

IP_ID 0b0000000000110000..ID for TRNG.

◆ TRNG_VID1_MAJ_REV

#define TRNG_VID1_MAJ_REV ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)

MAJ_REV 0b00000001..Major revision number for TRNG.

◆ TRNG_VID1_MIN_REV

#define TRNG_VID1_MIN_REV ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)

MIN_REV 0b00000000..Minor revision number for TRNG.

◆ TRNG_VID2_CONFIG_OPT

#define TRNG_VID2_CONFIG_OPT ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)

CONFIG_OPT 0b00000000..TRNG_CONFIG_OPT for TRNG.

◆ TRNG_VID2_ECO_REV

#define TRNG_VID2_ECO_REV ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)

ECO_REV 0b00000000..TRNG_ECO_REV for TRNG.

◆ TRNG_VID2_ERA

#define TRNG_VID2_ERA ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)

ERA 0b00000000..COMPILE_OPT for TRNG.

◆ TRNG_VID2_INTG_OPT

#define TRNG_VID2_INTG_OPT ( x ) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)

INTG_OPT 0b00000000..INTG_OPT for TRNG.

Macros

MCTL - Miscellaneous Control Register

SCMISC - Statistical Check Miscellaneous Register

PKRRNG - Poker Range Register

PKRMAX - Poker Maximum Limit Register

PKRSQ - Poker Square Calculation Result Register

SDCTL - Seed Control Register

SBLIM - Sparse Bit Limit Register

TOTSAM - Total Samples Register

FRQMIN - Frequency Count Minimum Limit Register

FRQCNT - Frequency Count Register

FRQMAX - Frequency Count Maximum Limit Register

SCMC - Statistical Check Monobit Count Register

SCML - Statistical Check Monobit Limit Register

SCR1C - Statistical Check Run Length 1 Count Register

SCR1L - Statistical Check Run Length 1 Limit Register

SCR2C - Statistical Check Run Length 2 Count Register

SCR2L - Statistical Check Run Length 2 Limit Register

SCR3C - Statistical Check Run Length 3 Count Register

SCR3L - Statistical Check Run Length 3 Limit Register

SCR4C - Statistical Check Run Length 4 Count Register

SCR4L - Statistical Check Run Length 4 Limit Register

SCR5C - Statistical Check Run Length 5 Count Register

SCR5L - Statistical Check Run Length 5 Limit Register

SCR6PC - Statistical Check Run Length 6+ Count Register

SCR6PL - Statistical Check Run Length 6+ Limit Register

STATUS - Status Register

ENT - Entropy Read Register

PKRCNT10 - Statistical Check Poker Count 1 and 0 Register

PKRCNT32 - Statistical Check Poker Count 3 and 2 Register

PKRCNT54 - Statistical Check Poker Count 5 and 4 Register

PKRCNT76 - Statistical Check Poker Count 7 and 6 Register

PKRCNT98 - Statistical Check Poker Count 9 and 8 Register

PKRCNTBA - Statistical Check Poker Count B and A Register

PKRCNTDC - Statistical Check Poker Count D and C Register

PKRCNTFE - Statistical Check Poker Count F and E Register

SEC_CFG - Security Configuration Register

INT_CTRL - Interrupt Control Register

INT_MASK - Mask Register

INT_STATUS - Interrupt Status Register

VID1 - Version ID Register (MS)

VID2 - Version ID Register (LS)