RTEMS 6.1-rc6
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CTRL0 - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_V_SEL_SHIFT)) & TMPSNS_CTRL0_V_SEL_MASK) |
#define | TMPSNS_CTRL0_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_IBIAS_TRIM_MASK) |
CTRL0_SET - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_SET_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_SET_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SET_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_SET_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_SET_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_SET_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_V_SEL_SHIFT)) & TMPSNS_CTRL0_SET_V_SEL_MASK) |
#define | TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_SET_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK) |
CTRL0_CLR - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_CLR_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_CLR_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_CLR_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_CLR_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_V_SEL_SHIFT)) & TMPSNS_CTRL0_CLR_V_SEL_MASK) |
#define | TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_CLR_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK) |
CTRL0_TOG - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_TOG_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_TOG_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_TOG_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_TOG_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_V_SEL_SHIFT)) & TMPSNS_CTRL0_TOG_V_SEL_MASK) |
#define | TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_TOG_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK) |
CTRL1 - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK) |
#define | TMPSNS_CTRL1_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK) |
#define | TMPSNS_CTRL1_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK) |
#define | TMPSNS_CTRL1_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RFU_SHIFT)) & TMPSNS_CTRL1_RFU_MASK) |
#define | TMPSNS_CTRL1_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_PWD_FULL_MASK) |
CTRL1_SET - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_SET_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_SET_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_SET_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK) |
#define | TMPSNS_CTRL1_SET_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_SET_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_SET_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_SET_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_SET_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_SET_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_SET_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_SET_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_SET_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK) |
#define | TMPSNS_CTRL1_SET_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_SET_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_SET_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK) |
#define | TMPSNS_CTRL1_SET_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_SET_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_SET_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RFU_SHIFT)) & TMPSNS_CTRL1_SET_RFU_MASK) |
#define | TMPSNS_CTRL1_SET_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_SET_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_SET_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_SET_PWD_FULL_MASK) |
CTRL1_CLR - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_CLR_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_CLR_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_CLR_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK) |
#define | TMPSNS_CTRL1_CLR_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_CLR_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_CLR_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_CLR_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_CLR_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_CLR_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK) |
#define | TMPSNS_CTRL1_CLR_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_CLR_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_CLR_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK) |
#define | TMPSNS_CTRL1_CLR_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_CLR_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_CLR_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RFU_SHIFT)) & TMPSNS_CTRL1_CLR_RFU_MASK) |
#define | TMPSNS_CTRL1_CLR_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_CLR_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_FULL_MASK) |
CTRL1_TOG - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_TOG_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_TOG_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_TOG_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK) |
#define | TMPSNS_CTRL1_TOG_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_TOG_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_TOG_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_TOG_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_TOG_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_TOG_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK) |
#define | TMPSNS_CTRL1_TOG_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_TOG_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_TOG_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK) |
#define | TMPSNS_CTRL1_TOG_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_TOG_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_TOG_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RFU_SHIFT)) & TMPSNS_CTRL1_TOG_RFU_MASK) |
#define | TMPSNS_CTRL1_TOG_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_TOG_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_FULL_MASK) |
RANGE0 - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK) |
RANGE0_SET - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_SET_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_SET_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK) |
RANGE0_CLR - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_CLR_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK) |
RANGE0_TOG - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_TOG_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK) |
RANGE1 - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK) |
RANGE1_SET - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_SET_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK) |
RANGE1_CLR - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK) |
RANGE1_TOG - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK) |
STATUS0 - Temperature Sensor Status Register 0 | |
#define | TMPSNS_STATUS0_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_STATUS0_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_STATUS0_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK) |
#define | TMPSNS_STATUS0_FINISH_MASK (0x10000U) |
#define | TMPSNS_STATUS0_FINISH_SHIFT (16U) |
#define | TMPSNS_STATUS0_FINISH(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK) |
#define | TMPSNS_STATUS0_LOW_TEMP_MASK (0x20000U) |
#define | TMPSNS_STATUS0_LOW_TEMP_SHIFT (17U) |
#define | TMPSNS_STATUS0_LOW_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK) |
#define | TMPSNS_STATUS0_HIGH_TEMP_MASK (0x40000U) |
#define | TMPSNS_STATUS0_HIGH_TEMP_SHIFT (18U) |
#define | TMPSNS_STATUS0_HIGH_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK) |
#define | TMPSNS_STATUS0_PANIC_TEMP_MASK (0x80000U) |
#define | TMPSNS_STATUS0_PANIC_TEMP_SHIFT (19U) |
#define | TMPSNS_STATUS0_PANIC_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_PANIC_TEMP_SHIFT)) & TMPSNS_STATUS0_PANIC_TEMP_MASK) |
CTRL0 - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_V_SEL_SHIFT)) & TMPSNS_CTRL0_V_SEL_MASK) |
#define | TMPSNS_CTRL0_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_IBIAS_TRIM_MASK) |
CTRL0_SET - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_SET_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_SET_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SET_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_SET_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_SET_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_SET_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_V_SEL_SHIFT)) & TMPSNS_CTRL0_SET_V_SEL_MASK) |
#define | TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_SET_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK) |
CTRL0_CLR - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_CLR_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_CLR_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_CLR_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_CLR_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_V_SEL_SHIFT)) & TMPSNS_CTRL0_CLR_V_SEL_MASK) |
#define | TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_CLR_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK) |
CTRL0_TOG - Temperature Sensor Control Register 0 | |
#define | TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK (0x3FU) |
#define | TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT (0U) |
#define | TMPSNS_CTRL0_TOG_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK) |
#define | TMPSNS_CTRL0_TOG_V_SEL_MASK (0x300U) |
#define | TMPSNS_CTRL0_TOG_V_SEL_SHIFT (8U) |
#define | TMPSNS_CTRL0_TOG_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_V_SEL_SHIFT)) & TMPSNS_CTRL0_TOG_V_SEL_MASK) |
#define | TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK (0xF000U) |
#define | TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT (12U) |
#define | TMPSNS_CTRL0_TOG_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK) |
CTRL1 - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK) |
#define | TMPSNS_CTRL1_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK) |
#define | TMPSNS_CTRL1_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK) |
#define | TMPSNS_CTRL1_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RFU_SHIFT)) & TMPSNS_CTRL1_RFU_MASK) |
#define | TMPSNS_CTRL1_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_PWD_FULL_MASK) |
CTRL1_SET - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_SET_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_SET_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_SET_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK) |
#define | TMPSNS_CTRL1_SET_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_SET_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_SET_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_SET_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_SET_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_SET_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_SET_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_SET_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_SET_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK) |
#define | TMPSNS_CTRL1_SET_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_SET_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_SET_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK) |
#define | TMPSNS_CTRL1_SET_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_SET_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_SET_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RFU_SHIFT)) & TMPSNS_CTRL1_SET_RFU_MASK) |
#define | TMPSNS_CTRL1_SET_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_SET_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_SET_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_SET_PWD_FULL_MASK) |
CTRL1_CLR - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_CLR_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_CLR_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_CLR_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK) |
#define | TMPSNS_CTRL1_CLR_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_CLR_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_CLR_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_CLR_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_CLR_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_CLR_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_CLR_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK) |
#define | TMPSNS_CTRL1_CLR_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_CLR_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_CLR_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK) |
#define | TMPSNS_CTRL1_CLR_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_CLR_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_CLR_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RFU_SHIFT)) & TMPSNS_CTRL1_CLR_RFU_MASK) |
#define | TMPSNS_CTRL1_CLR_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_CLR_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_FULL_MASK) |
CTRL1_TOG - Temperature Sensor Control Register 1 | |
#define | TMPSNS_CTRL1_TOG_FREQ_MASK (0xFFFFU) |
#define | TMPSNS_CTRL1_TOG_FREQ_SHIFT (0U) |
#define | TMPSNS_CTRL1_TOG_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK) |
#define | TMPSNS_CTRL1_TOG_FINISH_IE_MASK (0x10000U) |
#define | TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT (16U) |
#define | TMPSNS_CTRL1_TOG_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK (0x20000U) |
#define | TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT (17U) |
#define | TMPSNS_CTRL1_TOG_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK (0x40000U) |
#define | TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT (18U) |
#define | TMPSNS_CTRL1_TOG_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK (0x80000U) |
#define | TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT (19U) |
#define | TMPSNS_CTRL1_TOG_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK) |
#define | TMPSNS_CTRL1_TOG_START_MASK (0x400000U) |
#define | TMPSNS_CTRL1_TOG_START_SHIFT (22U) |
#define | TMPSNS_CTRL1_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK) |
#define | TMPSNS_CTRL1_TOG_PWD_MASK (0x800000U) |
#define | TMPSNS_CTRL1_TOG_PWD_SHIFT (23U) |
#define | TMPSNS_CTRL1_TOG_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK) |
#define | TMPSNS_CTRL1_TOG_RFU_MASK (0x7F000000U) |
#define | TMPSNS_CTRL1_TOG_RFU_SHIFT (24U) |
#define | TMPSNS_CTRL1_TOG_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RFU_SHIFT)) & TMPSNS_CTRL1_TOG_RFU_MASK) |
#define | TMPSNS_CTRL1_TOG_PWD_FULL_MASK (0x80000000U) |
#define | TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT (31U) |
#define | TMPSNS_CTRL1_TOG_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_FULL_MASK) |
RANGE0 - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK) |
RANGE0_SET - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_SET_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_SET_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK) |
RANGE0_CLR - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_CLR_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK) |
RANGE0_TOG - Temperature Sensor Range Register 0 | |
#define | TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE0_TOG_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK) |
#define | TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK (0xFFF0000U) |
#define | TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT (16U) |
#define | TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK) |
RANGE1 - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK) |
RANGE1_SET - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_SET_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK) |
RANGE1_CLR - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK) |
RANGE1_TOG - Temperature Sensor Range Register 1 | |
#define | TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK) |
STATUS0 - Temperature Sensor Status Register 0 | |
#define | TMPSNS_STATUS0_TEMP_VAL_MASK (0xFFFU) |
#define | TMPSNS_STATUS0_TEMP_VAL_SHIFT (0U) |
#define | TMPSNS_STATUS0_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK) |
#define | TMPSNS_STATUS0_FINISH_MASK (0x10000U) |
#define | TMPSNS_STATUS0_FINISH_SHIFT (16U) |
#define | TMPSNS_STATUS0_FINISH(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK) |
#define | TMPSNS_STATUS0_LOW_TEMP_MASK (0x20000U) |
#define | TMPSNS_STATUS0_LOW_TEMP_SHIFT (17U) |
#define | TMPSNS_STATUS0_LOW_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK) |
#define | TMPSNS_STATUS0_HIGH_TEMP_MASK (0x40000U) |
#define | TMPSNS_STATUS0_HIGH_TEMP_SHIFT (18U) |
#define | TMPSNS_STATUS0_HIGH_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK) |
#define | TMPSNS_STATUS0_PANIC_TEMP_MASK (0x80000U) |
#define | TMPSNS_STATUS0_PANIC_TEMP_SHIFT (19U) |
#define | TMPSNS_STATUS0_PANIC_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_PANIC_TEMP_SHIFT)) & TMPSNS_STATUS0_PANIC_TEMP_MASK) |
#define TMPSNS_CTRL0_CLR_IBIAS_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK) |
IBIAS_TRIM - Current bias trim value
#define TMPSNS_CTRL0_CLR_IBIAS_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK) |
IBIAS_TRIM - Current bias trim value
#define TMPSNS_CTRL0_CLR_SLOPE_CAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK) |
SLOPE_CAL - Ramp slope calibration control
#define TMPSNS_CTRL0_CLR_SLOPE_CAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK) |
SLOPE_CAL - Ramp slope calibration control
#define TMPSNS_CTRL0_CLR_V_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_V_SEL_SHIFT)) & TMPSNS_CTRL0_CLR_V_SEL_MASK) |
V_SEL - Voltage Select
#define TMPSNS_CTRL0_CLR_V_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_V_SEL_SHIFT)) & TMPSNS_CTRL0_CLR_V_SEL_MASK) |
V_SEL - Voltage Select
#define TMPSNS_CTRL0_IBIAS_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_IBIAS_TRIM_MASK) |
IBIAS_TRIM - Current bias trim value
#define TMPSNS_CTRL0_IBIAS_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_IBIAS_TRIM_MASK) |
IBIAS_TRIM - Current bias trim value
#define TMPSNS_CTRL0_SET_IBIAS_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK) |
IBIAS_TRIM - Current bias trim value
#define TMPSNS_CTRL0_SET_IBIAS_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK) |
IBIAS_TRIM - Current bias trim value
#define TMPSNS_CTRL0_SET_SLOPE_CAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SET_SLOPE_CAL_MASK) |
SLOPE_CAL - Ramp slope calibration control
#define TMPSNS_CTRL0_SET_SLOPE_CAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SET_SLOPE_CAL_MASK) |
SLOPE_CAL - Ramp slope calibration control
#define TMPSNS_CTRL0_SET_V_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_V_SEL_SHIFT)) & TMPSNS_CTRL0_SET_V_SEL_MASK) |
V_SEL - Voltage Select
#define TMPSNS_CTRL0_SET_V_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_V_SEL_SHIFT)) & TMPSNS_CTRL0_SET_V_SEL_MASK) |
V_SEL - Voltage Select
#define TMPSNS_CTRL0_SLOPE_CAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SLOPE_CAL_MASK) |
SLOPE_CAL - Ramp slope calibration control
#define TMPSNS_CTRL0_SLOPE_CAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SLOPE_CAL_MASK) |
SLOPE_CAL - Ramp slope calibration control
#define TMPSNS_CTRL0_TOG_IBIAS_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK) |
IBIAS_TRIM - Current bias trim value
#define TMPSNS_CTRL0_TOG_IBIAS_TRIM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK) |
IBIAS_TRIM - Current bias trim value
#define TMPSNS_CTRL0_TOG_SLOPE_CAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK) |
SLOPE_CAL - Ramp slope calibration control
#define TMPSNS_CTRL0_TOG_SLOPE_CAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK) |
SLOPE_CAL - Ramp slope calibration control
#define TMPSNS_CTRL0_TOG_V_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_V_SEL_SHIFT)) & TMPSNS_CTRL0_TOG_V_SEL_MASK) |
V_SEL - Voltage Select
#define TMPSNS_CTRL0_TOG_V_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_V_SEL_SHIFT)) & TMPSNS_CTRL0_TOG_V_SEL_MASK) |
V_SEL - Voltage Select
#define TMPSNS_CTRL0_V_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_V_SEL_SHIFT)) & TMPSNS_CTRL0_V_SEL_MASK) |
V_SEL - Voltage Select 0b00..Normal temperature measuring mode 0b01-0b10..Reserved
#define TMPSNS_CTRL0_V_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_V_SEL_SHIFT)) & TMPSNS_CTRL0_V_SEL_MASK) |
V_SEL - Voltage Select 0b00..Normal temperature measuring mode 0b01-0b10..Reserved
#define TMPSNS_CTRL1_CLR_FINISH_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK) |
FINISH_IE - Measurement finished interrupt enable
#define TMPSNS_CTRL1_CLR_FINISH_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK) |
FINISH_IE - Measurement finished interrupt enable
#define TMPSNS_CTRL1_CLR_FREQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK) |
FREQ - Temperature Measurement Frequency
#define TMPSNS_CTRL1_CLR_FREQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK) |
FREQ - Temperature Measurement Frequency
#define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK) |
HIGH_TEMP_IE - High temperature interrupt enable
#define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK) |
HIGH_TEMP_IE - High temperature interrupt enable
#define TMPSNS_CTRL1_CLR_LOW_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK) |
LOW_TEMP_IE - Low temperature interrupt enable
#define TMPSNS_CTRL1_CLR_LOW_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK) |
LOW_TEMP_IE - Low temperature interrupt enable
#define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK) |
PANIC_TEMP_IE - Panic temperature interrupt enable
#define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK) |
PANIC_TEMP_IE - Panic temperature interrupt enable
#define TMPSNS_CTRL1_CLR_PWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK) |
PWD - Temperature Sensor Power Down
#define TMPSNS_CTRL1_CLR_PWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK) |
PWD - Temperature Sensor Power Down
#define TMPSNS_CTRL1_CLR_PWD_FULL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_FULL_MASK) |
PWD_FULL - Temperature Sensor Full Power Down
#define TMPSNS_CTRL1_CLR_PWD_FULL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_FULL_MASK) |
PWD_FULL - Temperature Sensor Full Power Down
#define TMPSNS_CTRL1_CLR_RFU | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RFU_SHIFT)) & TMPSNS_CTRL1_CLR_RFU_MASK) |
RFU - Read/Writeable field. Reserved for future use
#define TMPSNS_CTRL1_CLR_RFU | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RFU_SHIFT)) & TMPSNS_CTRL1_CLR_RFU_MASK) |
RFU - Read/Writeable field. Reserved for future use
#define TMPSNS_CTRL1_CLR_START | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK) |
START - Start Temperature Measurement
#define TMPSNS_CTRL1_CLR_START | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK) |
START - Start Temperature Measurement
#define TMPSNS_CTRL1_FINISH_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK) |
FINISH_IE - Measurement finished interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define TMPSNS_CTRL1_FINISH_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK) |
FINISH_IE - Measurement finished interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define TMPSNS_CTRL1_FREQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK) |
FREQ - Temperature Measurement Frequency 0b0000000000000000..Single Reading Mode. New reading available every time CTRL1[START] bit is set to 1 from 0. 0b0000000000000001-0b1111111111111111..Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete.
#define TMPSNS_CTRL1_FREQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK) |
FREQ - Temperature Measurement Frequency 0b0000000000000000..Single Reading Mode. New reading available every time CTRL1[START] bit is set to 1 from 0. 0b0000000000000001-0b1111111111111111..Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete.
#define TMPSNS_CTRL1_HIGH_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK) |
HIGH_TEMP_IE - High temperature interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define TMPSNS_CTRL1_HIGH_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK) |
HIGH_TEMP_IE - High temperature interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define TMPSNS_CTRL1_LOW_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK) |
LOW_TEMP_IE - Low temperature interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define TMPSNS_CTRL1_LOW_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK) |
LOW_TEMP_IE - Low temperature interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define TMPSNS_CTRL1_PANIC_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK) |
PANIC_TEMP_IE - Panic temperature interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define TMPSNS_CTRL1_PANIC_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK) |
PANIC_TEMP_IE - Panic temperature interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define TMPSNS_CTRL1_PWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK) |
PWD - Temperature Sensor Power Down 0b0..Sensor is active 0b1..Sensor is powered down
#define TMPSNS_CTRL1_PWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK) |
PWD - Temperature Sensor Power Down 0b0..Sensor is active 0b1..Sensor is powered down
#define TMPSNS_CTRL1_PWD_FULL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_PWD_FULL_MASK) |
PWD_FULL - Temperature Sensor Full Power Down 0b0..Sensor is active 0b1..Sensor is powered down
#define TMPSNS_CTRL1_PWD_FULL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_PWD_FULL_MASK) |
PWD_FULL - Temperature Sensor Full Power Down 0b0..Sensor is active 0b1..Sensor is powered down
#define TMPSNS_CTRL1_RFU | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RFU_SHIFT)) & TMPSNS_CTRL1_RFU_MASK) |
RFU - Read/Writeable field. Reserved for future use
#define TMPSNS_CTRL1_RFU | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RFU_SHIFT)) & TMPSNS_CTRL1_RFU_MASK) |
RFU - Read/Writeable field. Reserved for future use
#define TMPSNS_CTRL1_SET_FINISH_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK) |
FINISH_IE - Measurement finished interrupt enable
#define TMPSNS_CTRL1_SET_FINISH_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK) |
FINISH_IE - Measurement finished interrupt enable
#define TMPSNS_CTRL1_SET_FREQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK) |
FREQ - Temperature Measurement Frequency
#define TMPSNS_CTRL1_SET_FREQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK) |
FREQ - Temperature Measurement Frequency
#define TMPSNS_CTRL1_SET_HIGH_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK) |
HIGH_TEMP_IE - High temperature interrupt enable
#define TMPSNS_CTRL1_SET_HIGH_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK) |
HIGH_TEMP_IE - High temperature interrupt enable
#define TMPSNS_CTRL1_SET_LOW_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK) |
LOW_TEMP_IE - Low temperature interrupt enable
#define TMPSNS_CTRL1_SET_LOW_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK) |
LOW_TEMP_IE - Low temperature interrupt enable
#define TMPSNS_CTRL1_SET_PANIC_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK) |
PANIC_TEMP_IE - Panic temperature interrupt enable
#define TMPSNS_CTRL1_SET_PANIC_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK) |
PANIC_TEMP_IE - Panic temperature interrupt enable
#define TMPSNS_CTRL1_SET_PWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK) |
PWD - Temperature Sensor Power Down
#define TMPSNS_CTRL1_SET_PWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK) |
PWD - Temperature Sensor Power Down
#define TMPSNS_CTRL1_SET_PWD_FULL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_SET_PWD_FULL_MASK) |
PWD_FULL - Temperature Sensor Full Power Down
#define TMPSNS_CTRL1_SET_PWD_FULL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_SET_PWD_FULL_MASK) |
PWD_FULL - Temperature Sensor Full Power Down
#define TMPSNS_CTRL1_SET_RFU | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RFU_SHIFT)) & TMPSNS_CTRL1_SET_RFU_MASK) |
RFU - Read/Writeable field. Reserved for future use
#define TMPSNS_CTRL1_SET_RFU | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RFU_SHIFT)) & TMPSNS_CTRL1_SET_RFU_MASK) |
RFU - Read/Writeable field. Reserved for future use
#define TMPSNS_CTRL1_SET_START | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK) |
START - Start Temperature Measurement
#define TMPSNS_CTRL1_SET_START | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK) |
START - Start Temperature Measurement
#define TMPSNS_CTRL1_START | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK) |
START - Start Temperature Measurement 0b0..No new temperature reading taken 0b1..Initiate a new temperature reading
#define TMPSNS_CTRL1_START | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK) |
START - Start Temperature Measurement 0b0..No new temperature reading taken 0b1..Initiate a new temperature reading
#define TMPSNS_CTRL1_TOG_FINISH_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK) |
FINISH_IE - Measurement finished interrupt enable
#define TMPSNS_CTRL1_TOG_FINISH_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK) |
FINISH_IE - Measurement finished interrupt enable
#define TMPSNS_CTRL1_TOG_FREQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK) |
FREQ - Temperature Measurement Frequency
#define TMPSNS_CTRL1_TOG_FREQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK) |
FREQ - Temperature Measurement Frequency
#define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK) |
HIGH_TEMP_IE - High temperature interrupt enable
#define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK) |
HIGH_TEMP_IE - High temperature interrupt enable
#define TMPSNS_CTRL1_TOG_LOW_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK) |
LOW_TEMP_IE - Low temperature interrupt enable
#define TMPSNS_CTRL1_TOG_LOW_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK) |
LOW_TEMP_IE - Low temperature interrupt enable
#define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK) |
PANIC_TEMP_IE - Panic temperature interrupt enable
#define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK) |
PANIC_TEMP_IE - Panic temperature interrupt enable
#define TMPSNS_CTRL1_TOG_PWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK) |
PWD - Temperature Sensor Power Down
#define TMPSNS_CTRL1_TOG_PWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK) |
PWD - Temperature Sensor Power Down
#define TMPSNS_CTRL1_TOG_PWD_FULL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_FULL_MASK) |
PWD_FULL - Temperature Sensor Full Power Down
#define TMPSNS_CTRL1_TOG_PWD_FULL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_FULL_MASK) |
PWD_FULL - Temperature Sensor Full Power Down
#define TMPSNS_CTRL1_TOG_RFU | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RFU_SHIFT)) & TMPSNS_CTRL1_TOG_RFU_MASK) |
RFU - Read/Writeable field. Reserved for future use
#define TMPSNS_CTRL1_TOG_RFU | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RFU_SHIFT)) & TMPSNS_CTRL1_TOG_RFU_MASK) |
RFU - Read/Writeable field. Reserved for future use
#define TMPSNS_CTRL1_TOG_START | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK) |
START - Start Temperature Measurement
#define TMPSNS_CTRL1_TOG_START | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK) |
START - Start Temperature Measurement
#define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK) |
HIGH_TEMP_VAL - High temperature threshold value
#define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK) |
HIGH_TEMP_VAL - High temperature threshold value
#define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK) |
LOW_TEMP_VAL - Low temperature threshold value
#define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK) |
LOW_TEMP_VAL - Low temperature threshold value
#define TMPSNS_RANGE0_HIGH_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK) |
HIGH_TEMP_VAL - High temperature threshold value
#define TMPSNS_RANGE0_HIGH_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK) |
HIGH_TEMP_VAL - High temperature threshold value
#define TMPSNS_RANGE0_LOW_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK) |
LOW_TEMP_VAL - Low temperature threshold value
#define TMPSNS_RANGE0_LOW_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK) |
LOW_TEMP_VAL - Low temperature threshold value
#define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK) |
HIGH_TEMP_VAL - High temperature threshold value
#define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK) |
HIGH_TEMP_VAL - High temperature threshold value
#define TMPSNS_RANGE0_SET_LOW_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK) |
LOW_TEMP_VAL - Low temperature threshold value
#define TMPSNS_RANGE0_SET_LOW_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK) |
LOW_TEMP_VAL - Low temperature threshold value
#define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK) |
HIGH_TEMP_VAL - High temperature threshold value
#define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK) |
HIGH_TEMP_VAL - High temperature threshold value
#define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK) |
LOW_TEMP_VAL - Low temperature threshold value
#define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK) |
LOW_TEMP_VAL - Low temperature threshold value
#define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK) |
PANIC_TEMP_VAL - Panic temperature threshold value
#define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK) |
PANIC_TEMP_VAL - Panic temperature threshold value
#define TMPSNS_RANGE1_PANIC_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK) |
PANIC_TEMP_VAL - Panic temperature threshold value
#define TMPSNS_RANGE1_PANIC_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK) |
PANIC_TEMP_VAL - Panic temperature threshold value
#define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK) |
PANIC_TEMP_VAL - Panic temperature threshold value
#define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK) |
PANIC_TEMP_VAL - Panic temperature threshold value
#define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK) |
PANIC_TEMP_VAL - Panic temperature threshold value
#define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK) |
PANIC_TEMP_VAL - Panic temperature threshold value
#define TMPSNS_STATUS0_FINISH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK) |
FINISH - Temperature measurement complete 0b0..Temperature sensor is busy (if CTRL1[START] = 1)or no new reading has been initiated (if CTRL1[START] = 0) 0b1..Temperature reading is complete and new temperature value available for reading
#define TMPSNS_STATUS0_FINISH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK) |
FINISH - Temperature measurement complete 0b0..Temperature sensor is busy (if CTRL1[START] = 1)or no new reading has been initiated (if CTRL1[START] = 0) 0b1..Temperature reading is complete and new temperature value available for reading
#define TMPSNS_STATUS0_HIGH_TEMP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK) |
HIGH_TEMP - High temperature alarm bit 0b0..No High temperature alert 0b1..High temperature alert
#define TMPSNS_STATUS0_HIGH_TEMP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK) |
HIGH_TEMP - High temperature alarm bit 0b0..No High temperature alert 0b1..High temperature alert
#define TMPSNS_STATUS0_LOW_TEMP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK) |
LOW_TEMP - Low temperature alarm bit 0b0..No Low temperature alert 0b1..Low temperature alert
#define TMPSNS_STATUS0_LOW_TEMP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK) |
LOW_TEMP - Low temperature alarm bit 0b0..No Low temperature alert 0b1..Low temperature alert
#define TMPSNS_STATUS0_PANIC_TEMP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_PANIC_TEMP_SHIFT)) & TMPSNS_STATUS0_PANIC_TEMP_MASK) |
PANIC_TEMP - Panic temperature alarm bit 0b0..No Panic temperature alert 0b1..Panic temperature alert
#define TMPSNS_STATUS0_PANIC_TEMP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_PANIC_TEMP_SHIFT)) & TMPSNS_STATUS0_PANIC_TEMP_MASK) |
PANIC_TEMP - Panic temperature alarm bit 0b0..No Panic temperature alert 0b1..Panic temperature alert
#define TMPSNS_STATUS0_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK) |
TEMP_VAL - Measured temperature value
#define TMPSNS_STATUS0_TEMP_VAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK) |
TEMP_VAL - Measured temperature value