TIM Break System

Macros
#define	TIM_BREAK_SYSTEM_ECC   SYSCFG_CFGR2_ECCL
#define	TIM_BREAK_SYSTEM_PVD   SYSCFG_CFGR2_PVDL
#define	TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL
#define	TIM_BREAK_SYSTEM_LOCKUP   SYSCFG_CFGR2_CLL

Detailed Description

Macro Definition Documentation

TIM_BREAK_SYSTEM_ECC

#define TIM_BREAK_SYSTEM_ECC   SYSCFG_CFGR2_ECCL

Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17

TIM_BREAK_SYSTEM_LOCKUP

#define TIM_BREAK_SYSTEM_LOCKUP   SYSCFG_CFGR2_CLL

Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17

TIM_BREAK_SYSTEM_PVD

#define TIM_BREAK_SYSTEM_PVD   SYSCFG_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface

TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR

#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL

Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17