Macros
#define	TIM_TIM1_ETR_GPIO 0x00000000U

#define	TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0

#define	TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1

#define	TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 \| TIM1_AF1_ETRSEL_0)

#define	TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2)

#define	TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 \| TIM1_AF1_ETRSEL_0)

#define	TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 \| TIM1_AF1_ETRSEL_1)

#define	TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 \| TIM1_AF1_ETRSEL_1 \| TIM1_AF1_ETRSEL_0)

#define	TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3

#define	TIM_TIM8_ETR_GPIO 0x00000000U

#define	TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0

#define	TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1

#define	TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 \| TIM8_AF1_ETRSEL_0)

#define	TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2)

#define	TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 \| TIM8_AF1_ETRSEL_0)

#define	TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 \| TIM8_AF1_ETRSEL_1)

#define	TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 \| TIM8_AF1_ETRSEL_1 \| TIM8_AF1_ETRSEL_0)

#define	TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3

#define	TIM_TIM2_ETR_GPIO 0x00000000U

#define	TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0)

#define	TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1)

#define	TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 \| TIM8_AF1_ETRSEL_0)

#define	TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2

#define	TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 \| TIM8_AF1_ETRSEL_0)

#define	TIM_TIM3_ETR_GPIO 0x00000000U

#define	TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0

#define	TIM_TIM5_ETR_GPIO 0x00000000U

#define	TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0

#define	TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1

#define	TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0

#define	TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1

#define	TIM_TIM23_ETR_GPIO 0x00000000U

#define	TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0)

#define	TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1)

#define	TIM_TIM24_ETR_GPIO 0x00000000U

#define	TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0

#define	TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1

#define	TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 \| TIM8_AF1_ETRSEL_0)

#define	TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2

Detailed Description

Macro Definition Documentation

◆ TIM_TIM1_ETR_ADC1_AWD1

#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

TIM1_ETR is connected to ADC1 AWD1

◆ TIM_TIM1_ETR_ADC1_AWD2

#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2)

TIM1_ETR is connected to ADC1 AWD2

◆ TIM_TIM1_ETR_ADC1_AWD3

#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)

TIM1_ETR is connected to ADC1 AWD3

◆ TIM_TIM1_ETR_ADC3_AWD1

#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)

TIM1_ETR is connected to ADC3 AWD1

◆ TIM_TIM1_ETR_ADC3_AWD2

#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)

TIM1_ETR is connected to ADC3 AWD2

◆ TIM_TIM1_ETR_ADC3_AWD3

#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3

TIM1_ETR is connected to ADC3 AWD3

◆ TIM_TIM1_ETR_COMP1

#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0

TIM1_ETR is connected to COMP1 OUT

◆ TIM_TIM1_ETR_COMP2

#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1

TIM1_ETR is connected to COMP2 OUT

◆ TIM_TIM1_ETR_GPIO

#define TIM_TIM1_ETR_GPIO 0x00000000U

TIM1_ETR is connected to GPIO

◆ TIM_TIM23_ETR_COMP1

#define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0)

TIM23_ETR is connected to COMP1 OUT

◆ TIM_TIM23_ETR_COMP2

#define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1)

TIM23_ETR is connected to COMP2 OUT

◆ TIM_TIM23_ETR_GPIO

#define TIM_TIM23_ETR_GPIO 0x00000000U

TIM23_ETR is connected to GPIO

◆ TIM_TIM24_ETR_GPIO

#define TIM_TIM24_ETR_GPIO 0x00000000U

TIM24_ETR is connected to GPIO

◆ TIM_TIM24_ETR_SAI1_FSA

#define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)

TIM24_ETR is connected to SAI1 FS_A

◆ TIM_TIM24_ETR_SAI1_FSB

#define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2

TIM24_ETR is connected to SAI1 FS_B

◆ TIM_TIM24_ETR_SAI4_FSA

#define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0

TIM24_ETR is connected to SAI4 FS_A

◆ TIM_TIM24_ETR_SAI4_FSB

#define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1

TIM24_ETR is connected to SAI4 FS_B

◆ TIM_TIM2_ETR_COMP1

#define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0)

TIM2_ETR is connected to COMP1 OUT

◆ TIM_TIM2_ETR_COMP2

#define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1)

TIM2_ETR is connected to COMP2 OUT

◆ TIM_TIM2_ETR_GPIO

#define TIM_TIM2_ETR_GPIO 0x00000000U

TIM2_ETR is connected to GPIO

◆ TIM_TIM2_ETR_RCC_LSE

#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)

TIM2_ETR is connected to RCC LSE

◆ TIM_TIM2_ETR_SAI1_FSA

#define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2

TIM2_ETR is connected to SAI1 FS_A

◆ TIM_TIM2_ETR_SAI1_FSB

#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)

TIM2_ETR is connected to SAI1 FS_B

◆ TIM_TIM3_ETR_COMP1

#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0

TIM3_ETR is connected to COMP1 OUT

◆ TIM_TIM3_ETR_GPIO

#define TIM_TIM3_ETR_GPIO 0x00000000U

TIM3_ETR is connected to GPIO

◆ TIM_TIM5_ETR_GPIO

#define TIM_TIM5_ETR_GPIO 0x00000000U

TIM5_ETR is connected to GPIO

◆ TIM_TIM5_ETR_SAI2_FSA

#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0

TIM5_ETR is connected to SAI2 FS_A

◆ TIM_TIM5_ETR_SAI2_FSB

#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1

TIM5_ETR is connected to SAI2 FS_B

◆ TIM_TIM5_ETR_SAI4_FSA

#define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0

TIM5_ETR is connected to SAI4 FS_A

◆ TIM_TIM5_ETR_SAI4_FSB

#define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1

TIM5_ETR is connected to SAI4 FS_B

◆ TIM_TIM8_ETR_ADC2_AWD1

#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)

TIM8_ETR is connected to ADC2 AWD1

◆ TIM_TIM8_ETR_ADC2_AWD2

#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2)

TIM8_ETR is connected to ADC2 AWD2

◆ TIM_TIM8_ETR_ADC2_AWD3

#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)

TIM8_ETR is connected to ADC2 AWD3

◆ TIM_TIM8_ETR_ADC3_AWD1

#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)

TIM8_ETR is connected to ADC3 AWD1

◆ TIM_TIM8_ETR_ADC3_AWD2

#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)

TIM8_ETR is connected to ADC3 AWD2

◆ TIM_TIM8_ETR_ADC3_AWD3

#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3

TIM8_ETR is connected to ADC3 AWD3

◆ TIM_TIM8_ETR_COMP1

#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0

TIM8_ETR is connected to COMP1 OUT

◆ TIM_TIM8_ETR_COMP2

#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1

TIM8_ETR is connected to COMP2 OUT

◆ TIM_TIM8_ETR_GPIO

#define TIM_TIM8_ETR_GPIO 0x00000000U

TIM8_ETR is connected to GPIO

Macros