RTEMS 6.1-rc6
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Macros | |
#define | __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML) |
SYSCFG Break AXIRAM double ECC lock. Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. | |
#define | __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML) |
SYSCFG Break ITCM double ECC lock. Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. | |
#define | __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML) |
SYSCFG Break DTCM double ECC lock. Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. | |
#define | __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L) |
SYSCFG Break SRAM1 double ECC lock. Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. | |
#define | __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L) |
SYSCFG Break SRAM2 double ECC lock. Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. | |
#define | __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L) |
SYSCFG Break SRAM3 double ECC lock. Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. | |
#define | __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L) |
SYSCFG Break SRAM4 double ECC lock. Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. | |
#define | __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML) |
SYSCFG Break Backup SRAM double ECC lock. Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. | |
#define | __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L) |
SYSCFG Break Cortex-M7 Lockup lock. Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input. | |
#define | __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL) |
SYSCFG Break FLASH double ECC lock. Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input. | |
#define | __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL) |
SYSCFG Break PVD lock. Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. | |
#define | __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) |
Fast-mode Plus driving capability enable/disable macros. | |
#define | __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) |
#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK | ( | ) | SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML) |
SYSCFG Break AXIRAM double ECC lock. Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK | ( | ) | SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML) |
SYSCFG Break Backup SRAM double ECC lock. Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK | ( | ) | SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L) |
SYSCFG Break Cortex-M7 Lockup lock. Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK | ( | ) | SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML) |
SYSCFG Break DTCM double ECC lock. Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK | ( | ) | SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL) |
SYSCFG Break FLASH double ECC lock. Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.
#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK | ( | ) | SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML) |
SYSCFG Break ITCM double ECC lock. Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
#define __HAL_SYSCFG_BREAK_PVD_LOCK | ( | ) | SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL) |
SYSCFG Break PVD lock. Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK | ( | ) | SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L) |
SYSCFG Break SRAM1 double ECC lock. Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK | ( | ) | SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L) |
SYSCFG Break SRAM2 double ECC lock. Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK | ( | ) | SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L) |
SYSCFG Break SRAM3 double ECC lock. Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK | ( | ) | SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L) |
SYSCFG Break SRAM4 double ECC lock. Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE | ( | __FASTMODEPLUS__ | ) |
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE | ( | __FASTMODEPLUS__ | ) |
Fast-mode Plus driving capability enable/disable macros.
__FASTMODEPLUS__ | This parameter can be a value of :
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