Macros
#define	SRC_GPR_COUNT (10U)

#define	SRC_GPR_COUNT (20U)

#define	SRC_GPR_COUNT (20U)

SCR - SRC Control Register
#define	SRC_SCR_MASK_WDOG_RST_MASK (0x780U)

#define	SRC_SCR_MASK_WDOG_RST_SHIFT (7U)

#define	SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)

#define	SRC_SCR_CORE0_RST_MASK (0x2000U)

#define	SRC_SCR_CORE0_RST_SHIFT (13U)

#define	SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)

#define	SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)

#define	SRC_SCR_CORE0_DBG_RST_SHIFT (17U)

#define	SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)

#define	SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)

#define	SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)

#define	SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)

#define	SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)

#define	SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)

#define	SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)

SBMR1 - SRC Boot Mode Register 1
#define	SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)

#define	SRC_SBMR1_BOOT_CFG1_SHIFT (0U)

#define	SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)

#define	SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)

#define	SRC_SBMR1_BOOT_CFG2_SHIFT (8U)

#define	SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)

#define	SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)

#define	SRC_SBMR1_BOOT_CFG3_SHIFT (16U)

#define	SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)

#define	SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)

#define	SRC_SBMR1_BOOT_CFG4_SHIFT (24U)

#define	SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)

SRSR - SRC Reset Status Register
#define	SRC_SRSR_IPP_RESET_B_MASK (0x1U)

#define	SRC_SRSR_IPP_RESET_B_SHIFT (0U)

#define	SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)

#define	SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)

#define	SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)

#define	SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)

#define	SRC_SRSR_CSU_RESET_B_MASK (0x4U)

#define	SRC_SRSR_CSU_RESET_B_SHIFT (2U)

#define	SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)

#define	SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)

#define	SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)

#define	SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)

#define	SRC_SRSR_WDOG_RST_B_MASK (0x10U)

#define	SRC_SRSR_WDOG_RST_B_SHIFT (4U)

#define	SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)

#define	SRC_SRSR_JTAG_RST_B_MASK (0x20U)

#define	SRC_SRSR_JTAG_RST_B_SHIFT (5U)

#define	SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)

#define	SRC_SRSR_JTAG_SW_RST_MASK (0x40U)

#define	SRC_SRSR_JTAG_SW_RST_SHIFT (6U)

#define	SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)

#define	SRC_SRSR_WDOG3_RST_B_MASK (0x80U)

#define	SRC_SRSR_WDOG3_RST_B_SHIFT (7U)

#define	SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)

#define	SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)

#define	SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)

#define	SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)

SBMR2 - SRC Boot Mode Register 2
#define	SRC_SBMR2_SEC_CONFIG_MASK (0x3U)

#define	SRC_SBMR2_SEC_CONFIG_SHIFT (0U)

#define	SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)

#define	SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)

#define	SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)

#define	SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)

#define	SRC_SBMR2_BMOD_MASK (0x3000000U)

#define	SRC_SBMR2_BMOD_SHIFT (24U)

#define	SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)

GPR - SRC General Purpose Register 1..SRC General Purpose Register 10
#define	SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)

#define	SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)

#define	SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)

#define	SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)

#define	SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)

#define	SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)

#define	SRC_GPR_PERSIST_REDUNDANT_BOOT_MASK (0xC000000U)

#define	SRC_GPR_PERSIST_REDUNDANT_BOOT_SHIFT (26U)

#define	SRC_GPR_PERSIST_REDUNDANT_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSIST_REDUNDANT_BOOT_SHIFT)) & SRC_GPR_PERSIST_REDUNDANT_BOOT_MASK)

#define	SRC_GPR_PERSIST_SECONDARY_BOOT_MASK (0x40000000U)

#define	SRC_GPR_PERSIST_SECONDARY_BOOT_SHIFT (30U)

#define	SRC_GPR_PERSIST_SECONDARY_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSIST_SECONDARY_BOOT_SHIFT)) & SRC_GPR_PERSIST_SECONDARY_BOOT_MASK)

SCR - SRC Control Register
#define	SRC_SCR_BT_RELEASE_M4_MASK (0x1U)

#define	SRC_SCR_BT_RELEASE_M4_SHIFT (0U)

#define	SRC_SCR_BT_RELEASE_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M4_SHIFT)) & SRC_SCR_BT_RELEASE_M4_MASK)

#define	SRC_SCR_BT_RELEASE_M7_MASK (0x2U)

#define	SRC_SCR_BT_RELEASE_M7_SHIFT (1U)

#define	SRC_SCR_BT_RELEASE_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M7_SHIFT)) & SRC_SCR_BT_RELEASE_M7_MASK)

SRMR - SRC Reset Mode Register
#define	SRC_SRMR_WDOG_RESET_MODE_MASK (0x3U)

#define	SRC_SRMR_WDOG_RESET_MODE_SHIFT (0U)

#define	SRC_SRMR_WDOG_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG_RESET_MODE_MASK)

#define	SRC_SRMR_WDOG3_RESET_MODE_MASK (0xCU)

#define	SRC_SRMR_WDOG3_RESET_MODE_SHIFT (2U)

#define	SRC_SRMR_WDOG3_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG3_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG3_RESET_MODE_MASK)

#define	SRC_SRMR_WDOG4_RESET_MODE_MASK (0x30U)

#define	SRC_SRMR_WDOG4_RESET_MODE_SHIFT (4U)

#define	SRC_SRMR_WDOG4_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG4_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG4_RESET_MODE_MASK)

#define	SRC_SRMR_M4LOCKUP_RESET_MODE_MASK (0xC0U)

#define	SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT (6U)

#define	SRC_SRMR_M4LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M4LOCKUP_RESET_MODE_MASK)

#define	SRC_SRMR_M7LOCKUP_RESET_MODE_MASK (0x300U)

#define	SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT (8U)

#define	SRC_SRMR_M7LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M7LOCKUP_RESET_MODE_MASK)

#define	SRC_SRMR_M4REQ_RESET_MODE_MASK (0xC00U)

#define	SRC_SRMR_M4REQ_RESET_MODE_SHIFT (10U)

#define	SRC_SRMR_M4REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M4REQ_RESET_MODE_MASK)

#define	SRC_SRMR_M7REQ_RESET_MODE_MASK (0x3000U)

#define	SRC_SRMR_M7REQ_RESET_MODE_SHIFT (12U)

#define	SRC_SRMR_M7REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M7REQ_RESET_MODE_MASK)

#define	SRC_SRMR_TEMPSENSE_RESET_MODE_MASK (0xC000U)

#define	SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT (14U)

#define	SRC_SRMR_TEMPSENSE_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_SRMR_TEMPSENSE_RESET_MODE_MASK)

#define	SRC_SRMR_CSU_RESET_MODE_MASK (0x30000U)

#define	SRC_SRMR_CSU_RESET_MODE_SHIFT (16U)

#define	SRC_SRMR_CSU_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_CSU_RESET_MODE_SHIFT)) & SRC_SRMR_CSU_RESET_MODE_MASK)

#define	SRC_SRMR_JTAGSW_RESET_MODE_MASK (0xC0000U)

#define	SRC_SRMR_JTAGSW_RESET_MODE_SHIFT (18U)

#define	SRC_SRMR_JTAGSW_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_JTAGSW_RESET_MODE_SHIFT)) & SRC_SRMR_JTAGSW_RESET_MODE_MASK)

#define	SRC_SRMR_OVERVOLT_RESET_MODE_MASK (0x300000U)

#define	SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT (20U)

#define	SRC_SRMR_OVERVOLT_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT)) & SRC_SRMR_OVERVOLT_RESET_MODE_MASK)

SBMR1 - SRC Boot Mode Register 1
#define	SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)

#define	SRC_SBMR1_BOOT_CFG1_SHIFT (0U)

#define	SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)

#define	SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)

#define	SRC_SBMR1_BOOT_CFG2_SHIFT (8U)

#define	SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)

#define	SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)

#define	SRC_SBMR1_BOOT_CFG3_SHIFT (16U)

#define	SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)

#define	SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)

#define	SRC_SBMR1_BOOT_CFG4_SHIFT (24U)

#define	SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)

SBMR2 - SRC Boot Mode Register 2
#define	SRC_SBMR2_SEC_CONFIG_MASK (0x3U)

#define	SRC_SBMR2_SEC_CONFIG_SHIFT (0U)

#define	SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)

#define	SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)

#define	SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)

#define	SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)

#define	SRC_SBMR2_BMOD_MASK (0x3000000U)

#define	SRC_SBMR2_BMOD_SHIFT (24U)

#define	SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)

SRSR - SRC Reset Status Register
#define	SRC_SRSR_IPP_RESET_B_M7_MASK (0x1U)

#define	SRC_SRSR_IPP_RESET_B_M7_SHIFT (0U)

#define	SRC_SRSR_IPP_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_RESET_B_M7_MASK)

#define	SRC_SRSR_M7_REQUEST_M7_MASK (0x2U)

#define	SRC_SRSR_M7_REQUEST_M7_SHIFT (1U)

#define	SRC_SRSR_M7_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M7_SHIFT)) & SRC_SRSR_M7_REQUEST_M7_MASK)

#define	SRC_SRSR_M7_LOCKUP_M7_MASK (0x4U)

#define	SRC_SRSR_M7_LOCKUP_M7_SHIFT (2U)

#define	SRC_SRSR_M7_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M7_SHIFT)) & SRC_SRSR_M7_LOCKUP_M7_MASK)

#define	SRC_SRSR_CSU_RESET_B_M7_MASK (0x8U)

#define	SRC_SRSR_CSU_RESET_B_M7_SHIFT (3U)

#define	SRC_SRSR_CSU_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M7_SHIFT)) & SRC_SRSR_CSU_RESET_B_M7_MASK)

#define	SRC_SRSR_IPP_USER_RESET_B_M7_MASK (0x10U)

#define	SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT (4U)

#define	SRC_SRSR_IPP_USER_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M7_MASK)

#define	SRC_SRSR_WDOG_RST_B_M7_MASK (0x20U)

#define	SRC_SRSR_WDOG_RST_B_M7_SHIFT (5U)

#define	SRC_SRSR_WDOG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG_RST_B_M7_MASK)

#define	SRC_SRSR_JTAG_RST_B_M7_MASK (0x40U)

#define	SRC_SRSR_JTAG_RST_B_M7_SHIFT (6U)

#define	SRC_SRSR_JTAG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M7_SHIFT)) & SRC_SRSR_JTAG_RST_B_M7_MASK)

#define	SRC_SRSR_JTAG_SW_RST_M7_MASK (0x80U)

#define	SRC_SRSR_JTAG_SW_RST_M7_SHIFT (7U)

#define	SRC_SRSR_JTAG_SW_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M7_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M7_MASK)

#define	SRC_SRSR_WDOG3_RST_B_M7_MASK (0x100U)

#define	SRC_SRSR_WDOG3_RST_B_M7_SHIFT (8U)

#define	SRC_SRSR_WDOG3_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M7_MASK)

#define	SRC_SRSR_WDOG4_RST_B_M7_MASK (0x200U)

#define	SRC_SRSR_WDOG4_RST_B_M7_SHIFT (9U)

#define	SRC_SRSR_WDOG4_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M7_MASK)

#define	SRC_SRSR_TEMPSENSE_RST_B_M7_MASK (0x400U)

#define	SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT (10U)

#define	SRC_SRSR_TEMPSENSE_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M7_MASK)

#define	SRC_SRSR_M4_REQUEST_M7_MASK (0x800U)

#define	SRC_SRSR_M4_REQUEST_M7_SHIFT (11U)

#define	SRC_SRSR_M4_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M7_SHIFT)) & SRC_SRSR_M4_REQUEST_M7_MASK)

#define	SRC_SRSR_M4_LOCKUP_M7_MASK (0x1000U)

#define	SRC_SRSR_M4_LOCKUP_M7_SHIFT (12U)

#define	SRC_SRSR_M4_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M7_SHIFT)) & SRC_SRSR_M4_LOCKUP_M7_MASK)

#define	SRC_SRSR_OVERVOLT_RST_M7_MASK (0x2000U)

#define	SRC_SRSR_OVERVOLT_RST_M7_SHIFT (13U)

#define	SRC_SRSR_OVERVOLT_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M7_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M7_MASK)

#define	SRC_SRSR_CDOG_RST_M7_MASK (0x4000U)

#define	SRC_SRSR_CDOG_RST_M7_SHIFT (14U)

#define	SRC_SRSR_CDOG_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M7_SHIFT)) & SRC_SRSR_CDOG_RST_M7_MASK)

#define	SRC_SRSR_IPP_RESET_B_M4_MASK (0x10000U)

#define	SRC_SRSR_IPP_RESET_B_M4_SHIFT (16U)

#define	SRC_SRSR_IPP_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_RESET_B_M4_MASK)

#define	SRC_SRSR_M4_REQUEST_M4_MASK (0x20000U)

#define	SRC_SRSR_M4_REQUEST_M4_SHIFT (17U)

#define	SRC_SRSR_M4_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M4_SHIFT)) & SRC_SRSR_M4_REQUEST_M4_MASK)

#define	SRC_SRSR_M4_LOCKUP_M4_MASK (0x40000U)

#define	SRC_SRSR_M4_LOCKUP_M4_SHIFT (18U)

#define	SRC_SRSR_M4_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M4_SHIFT)) & SRC_SRSR_M4_LOCKUP_M4_MASK)

#define	SRC_SRSR_CSU_RESET_B_M4_MASK (0x80000U)

#define	SRC_SRSR_CSU_RESET_B_M4_SHIFT (19U)

#define	SRC_SRSR_CSU_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M4_SHIFT)) & SRC_SRSR_CSU_RESET_B_M4_MASK)

#define	SRC_SRSR_IPP_USER_RESET_B_M4_MASK (0x100000U)

#define	SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT (20U)

#define	SRC_SRSR_IPP_USER_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M4_MASK)

#define	SRC_SRSR_WDOG_RST_B_M4_MASK (0x200000U)

#define	SRC_SRSR_WDOG_RST_B_M4_SHIFT (21U)

#define	SRC_SRSR_WDOG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG_RST_B_M4_MASK)

#define	SRC_SRSR_JTAG_RST_B_M4_MASK (0x400000U)

#define	SRC_SRSR_JTAG_RST_B_M4_SHIFT (22U)

#define	SRC_SRSR_JTAG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M4_SHIFT)) & SRC_SRSR_JTAG_RST_B_M4_MASK)

#define	SRC_SRSR_JTAG_SW_RST_M4_MASK (0x800000U)

#define	SRC_SRSR_JTAG_SW_RST_M4_SHIFT (23U)

#define	SRC_SRSR_JTAG_SW_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M4_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M4_MASK)

#define	SRC_SRSR_WDOG3_RST_B_M4_MASK (0x1000000U)

#define	SRC_SRSR_WDOG3_RST_B_M4_SHIFT (24U)

#define	SRC_SRSR_WDOG3_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M4_MASK)

#define	SRC_SRSR_WDOG4_RST_B_M4_MASK (0x2000000U)

#define	SRC_SRSR_WDOG4_RST_B_M4_SHIFT (25U)

#define	SRC_SRSR_WDOG4_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M4_MASK)

#define	SRC_SRSR_TEMPSENSE_RST_B_M4_MASK (0x4000000U)

#define	SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT (26U)

#define	SRC_SRSR_TEMPSENSE_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M4_MASK)

#define	SRC_SRSR_M7_REQUEST_M4_MASK (0x8000000U)

#define	SRC_SRSR_M7_REQUEST_M4_SHIFT (27U)

#define	SRC_SRSR_M7_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M4_SHIFT)) & SRC_SRSR_M7_REQUEST_M4_MASK)

#define	SRC_SRSR_M7_LOCKUP_M4_MASK (0x10000000U)

#define	SRC_SRSR_M7_LOCKUP_M4_SHIFT (28U)

#define	SRC_SRSR_M7_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M4_SHIFT)) & SRC_SRSR_M7_LOCKUP_M4_MASK)

#define	SRC_SRSR_OVERVOLT_RST_M4_MASK (0x20000000U)

#define	SRC_SRSR_OVERVOLT_RST_M4_SHIFT (29U)

#define	SRC_SRSR_OVERVOLT_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M4_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M4_MASK)

#define	SRC_SRSR_CDOG_RST_M4_MASK (0x40000000U)

#define	SRC_SRSR_CDOG_RST_M4_SHIFT (30U)

#define	SRC_SRSR_CDOG_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M4_SHIFT)) & SRC_SRSR_CDOG_RST_M4_MASK)

GPR - SRC General Purpose Register
#define	SRC_GPR_GPR_MASK (0xFFFFFFFFU)

#define	SRC_GPR_GPR_SHIFT (0U)

#define	SRC_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_GPR_SHIFT)) & SRC_GPR_GPR_MASK)

AUTHEN_MEGA - Slice Authentication Register
#define	SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_MEGA_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_MEGA_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_MEGA_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_MEGA_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_MODE_MASK)

#define	SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_MEGA_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_MEGA_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_MEGA_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_MEGA_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT)) & SRC_AUTHEN_MEGA_WHITE_LIST_MASK)

#define	SRC_AUTHEN_MEGA_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_MEGA_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_LIST_MASK)

#define	SRC_AUTHEN_MEGA_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_MEGA_USER_SHIFT (24U)

#define	SRC_AUTHEN_MEGA_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_USER_SHIFT)) & SRC_AUTHEN_MEGA_USER_MASK)

#define	SRC_AUTHEN_MEGA_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_MEGA_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_MEGA_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_NONSECURE_SHIFT)) & SRC_AUTHEN_MEGA_NONSECURE_MASK)

#define	SRC_AUTHEN_MEGA_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_MEGA_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_SETTING_MASK)

CTRL_MEGA - Slice Control Register
#define	SRC_CTRL_MEGA_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_MEGA_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_MEGA_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_MEGA_SW_RESET_SHIFT)) & SRC_CTRL_MEGA_SW_RESET_MASK)

SETPOINT_MEGA - Slice Setpoint Config Register
#define	SRC_SETPOINT_MEGA_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_MEGA_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_MEGA_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT0_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT0_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_MEGA_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_MEGA_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT1_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT1_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_MEGA_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_MEGA_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT2_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT2_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_MEGA_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_MEGA_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT3_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT3_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_MEGA_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_MEGA_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT4_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT4_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_MEGA_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_MEGA_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT5_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT5_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_MEGA_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_MEGA_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT6_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT6_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_MEGA_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_MEGA_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT7_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT7_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_MEGA_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_MEGA_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT8_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT8_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_MEGA_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_MEGA_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT9_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT9_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_MEGA_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_MEGA_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT10_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT10_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_MEGA_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_MEGA_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT11_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT11_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_MEGA_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_MEGA_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT12_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT12_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_MEGA_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_MEGA_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT13_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT13_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_MEGA_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_MEGA_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT14_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT14_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_MEGA_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_MEGA_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT15_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT15_MASK)

DOMAIN_MEGA - Slice Domain Config Register
#define	SRC_DOMAIN_MEGA_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_MEGA_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_RUN_MASK)

#define	SRC_DOMAIN_MEGA_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_MEGA_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_MEGA_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_MEGA_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_STOP_MASK)

#define	SRC_DOMAIN_MEGA_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_MEGA_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_MEGA_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_MEGA_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_RUN_MASK)

#define	SRC_DOMAIN_MEGA_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_MEGA_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_MEGA_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_MEGA_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_STOP_MASK)

#define	SRC_DOMAIN_MEGA_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_MEGA_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_SUSP_MASK)

STAT_MEGA - Slice Status Register
#define	SRC_STAT_MEGA_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_MEGA_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_MEGA_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_UNDER_RST_SHIFT)) & SRC_STAT_MEGA_UNDER_RST_MASK)

#define	SRC_STAT_MEGA_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_MEGA_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_MEGA_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_HW_SHIFT)) & SRC_STAT_MEGA_RST_BY_HW_MASK)

#define	SRC_STAT_MEGA_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_MEGA_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_MEGA_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_SW_SHIFT)) & SRC_STAT_MEGA_RST_BY_SW_MASK)

AUTHEN_DISPLAY - Slice Authentication Register
#define	SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_DISPLAY_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_DISPLAY_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_DISPLAY_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK)

#define	SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_DISPLAY_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_DISPLAY_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_DISPLAY_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK)

#define	SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_DISPLAY_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK)

#define	SRC_AUTHEN_DISPLAY_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_DISPLAY_USER_SHIFT (24U)

#define	SRC_AUTHEN_DISPLAY_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_USER_SHIFT)) & SRC_AUTHEN_DISPLAY_USER_MASK)

#define	SRC_AUTHEN_DISPLAY_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_DISPLAY_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT)) & SRC_AUTHEN_DISPLAY_NONSECURE_MASK)

#define	SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_DISPLAY_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK)

CTRL_DISPLAY - Slice Control Register
#define	SRC_CTRL_DISPLAY_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_DISPLAY_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_DISPLAY_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_DISPLAY_SW_RESET_SHIFT)) & SRC_CTRL_DISPLAY_SW_RESET_MASK)

SETPOINT_DISPLAY - Slice Setpoint Config Register
#define	SRC_SETPOINT_DISPLAY_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT0_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT1_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT2_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT3_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT4_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT5_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT6_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT7_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT8_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT9_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT10_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT11_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT12_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT13_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT14_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT15_MASK)

DOMAIN_DISPLAY - Slice Domain Config Register
#define	SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_DISPLAY_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_DISPLAY_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_DISPLAY_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_DISPLAY_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_DISPLAY_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_DISPLAY_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_DISPLAY_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_DISPLAY_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK)

STAT_DISPLAY - Slice Status Register
#define	SRC_STAT_DISPLAY_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_DISPLAY_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_DISPLAY_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_UNDER_RST_SHIFT)) & SRC_STAT_DISPLAY_UNDER_RST_MASK)

#define	SRC_STAT_DISPLAY_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_DISPLAY_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_DISPLAY_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_HW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_HW_MASK)

#define	SRC_STAT_DISPLAY_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_DISPLAY_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_DISPLAY_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_SW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_SW_MASK)

AUTHEN_WAKEUP - Slice Authentication Register
#define	SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_WAKEUP_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_WAKEUP_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_WAKEUP_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK)

#define	SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_WAKEUP_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_WAKEUP_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_WAKEUP_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK)

#define	SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_WAKEUP_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK)

#define	SRC_AUTHEN_WAKEUP_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_WAKEUP_USER_SHIFT (24U)

#define	SRC_AUTHEN_WAKEUP_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_USER_SHIFT)) & SRC_AUTHEN_WAKEUP_USER_MASK)

#define	SRC_AUTHEN_WAKEUP_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_WAKEUP_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT)) & SRC_AUTHEN_WAKEUP_NONSECURE_MASK)

#define	SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_WAKEUP_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK)

CTRL_WAKEUP - Slice Control Register
#define	SRC_CTRL_WAKEUP_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_WAKEUP_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_WAKEUP_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_WAKEUP_SW_RESET_SHIFT)) & SRC_CTRL_WAKEUP_SW_RESET_MASK)

SETPOINT_WAKEUP - Slice Setpoint Config Register
#define	SRC_SETPOINT_WAKEUP_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT0_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT1_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT2_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT3_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT4_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT5_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT6_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT7_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT8_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT9_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT10_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT11_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT12_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT13_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT14_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT15_MASK)

DOMAIN_WAKEUP - Slice Domain Config Register
#define	SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_WAKEUP_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_WAKEUP_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_WAKEUP_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_WAKEUP_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_WAKEUP_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_WAKEUP_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_WAKEUP_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_WAKEUP_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK)

STAT_WAKEUP - Slice Status Register
#define	SRC_STAT_WAKEUP_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_WAKEUP_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_WAKEUP_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_UNDER_RST_SHIFT)) & SRC_STAT_WAKEUP_UNDER_RST_MASK)

#define	SRC_STAT_WAKEUP_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_WAKEUP_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_WAKEUP_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_HW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_HW_MASK)

#define	SRC_STAT_WAKEUP_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_WAKEUP_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_WAKEUP_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_SW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_SW_MASK)

AUTHEN_M4CORE - Slice Authentication Register
#define	SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_M4CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_M4CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_M4CORE_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_M4CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_MODE_MASK)

#define	SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_M4CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_M4CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_M4CORE_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_M4CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_WHITE_LIST_MASK)

#define	SRC_AUTHEN_M4CORE_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_M4CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_LIST_MASK)

#define	SRC_AUTHEN_M4CORE_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_M4CORE_USER_SHIFT (24U)

#define	SRC_AUTHEN_M4CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_USER_SHIFT)) & SRC_AUTHEN_M4CORE_USER_MASK)

#define	SRC_AUTHEN_M4CORE_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_M4CORE_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_M4CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M4CORE_NONSECURE_MASK)

#define	SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_M4CORE_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK)

CTRL_M4CORE - Slice Control Register
#define	SRC_CTRL_M4CORE_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_M4CORE_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_M4CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4CORE_SW_RESET_SHIFT)) & SRC_CTRL_M4CORE_SW_RESET_MASK)

SETPOINT_M4CORE - Slice Setpoint Config Register
#define	SRC_SETPOINT_M4CORE_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_M4CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT0_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_M4CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT1_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_M4CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT2_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_M4CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT3_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_M4CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT4_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_M4CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT5_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_M4CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT6_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_M4CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT7_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_M4CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT8_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_M4CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT9_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_M4CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT10_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_M4CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT11_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_M4CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT12_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_M4CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT13_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_M4CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT14_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_M4CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT15_MASK)

DOMAIN_M4CORE - Slice Domain Config Register
#define	SRC_DOMAIN_M4CORE_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_M4CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_RUN_MASK)

#define	SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_M4CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_M4CORE_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_M4CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_STOP_MASK)

#define	SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_M4CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_M4CORE_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_M4CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_RUN_MASK)

#define	SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_M4CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_M4CORE_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_M4CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_STOP_MASK)

#define	SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_M4CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK)

STAT_M4CORE - Slice Status Register
#define	SRC_STAT_M4CORE_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_M4CORE_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_M4CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_UNDER_RST_SHIFT)) & SRC_STAT_M4CORE_UNDER_RST_MASK)

#define	SRC_STAT_M4CORE_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_M4CORE_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_M4CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_HW_MASK)

#define	SRC_STAT_M4CORE_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_M4CORE_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_M4CORE_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_SW_MASK)

AUTHEN_M7CORE - Slice Authentication Register
#define	SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_M7CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_M7CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_M7CORE_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_M7CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_MODE_MASK)

#define	SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_M7CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_M7CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_M7CORE_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_M7CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_WHITE_LIST_MASK)

#define	SRC_AUTHEN_M7CORE_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_M7CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_LIST_MASK)

#define	SRC_AUTHEN_M7CORE_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_M7CORE_USER_SHIFT (24U)

#define	SRC_AUTHEN_M7CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_USER_SHIFT)) & SRC_AUTHEN_M7CORE_USER_MASK)

#define	SRC_AUTHEN_M7CORE_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_M7CORE_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_M7CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M7CORE_NONSECURE_MASK)

#define	SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_M7CORE_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK)

CTRL_M7CORE - Slice Control Register
#define	SRC_CTRL_M7CORE_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_M7CORE_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_M7CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7CORE_SW_RESET_SHIFT)) & SRC_CTRL_M7CORE_SW_RESET_MASK)

SETPOINT_M7CORE - Slice Setpoint Config Register
#define	SRC_SETPOINT_M7CORE_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_M7CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT0_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_M7CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT1_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_M7CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT2_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_M7CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT3_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_M7CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT4_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_M7CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT5_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_M7CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT6_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_M7CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT7_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_M7CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT8_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_M7CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT9_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_M7CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT10_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_M7CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT11_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_M7CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT12_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_M7CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT13_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_M7CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT14_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_M7CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT15_MASK)

DOMAIN_M7CORE - Slice Domain Config Register
#define	SRC_DOMAIN_M7CORE_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_M7CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_RUN_MASK)

#define	SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_M7CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_M7CORE_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_M7CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_STOP_MASK)

#define	SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_M7CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_M7CORE_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_M7CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_RUN_MASK)

#define	SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_M7CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_M7CORE_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_M7CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_STOP_MASK)

#define	SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_M7CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK)

STAT_M7CORE - Slice Status Register
#define	SRC_STAT_M7CORE_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_M7CORE_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_M7CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_UNDER_RST_SHIFT)) & SRC_STAT_M7CORE_UNDER_RST_MASK)

#define	SRC_STAT_M7CORE_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_M7CORE_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_M7CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_HW_MASK)

#define	SRC_STAT_M7CORE_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_M7CORE_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_M7CORE_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_SW_MASK)

AUTHEN_M4DEBUG - Slice Authentication Register
#define	SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_M4DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_M4DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK)

#define	SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_M4DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_M4DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK)

#define	SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK)

#define	SRC_AUTHEN_M4DEBUG_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_M4DEBUG_USER_SHIFT (24U)

#define	SRC_AUTHEN_M4DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_USER_SHIFT)) & SRC_AUTHEN_M4DEBUG_USER_MASK)

#define	SRC_AUTHEN_M4DEBUG_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_M4DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M4DEBUG_NONSECURE_MASK)

#define	SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK)

CTRL_M4DEBUG - Slice Control Register
#define	SRC_CTRL_M4DEBUG_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_M4DEBUG_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_M4DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M4DEBUG_SW_RESET_MASK)

SETPOINT_M4DEBUG - Slice Setpoint Config Register
#define	SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK)

DOMAIN_M4DEBUG - Slice Domain Config Register
#define	SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK)

STAT_M4DEBUG - Slice Status Register
#define	SRC_STAT_M4DEBUG_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_M4DEBUG_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_M4DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M4DEBUG_UNDER_RST_MASK)

#define	SRC_STAT_M4DEBUG_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_M4DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_HW_MASK)

#define	SRC_STAT_M4DEBUG_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_M4DEBUG_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_SW_MASK)

AUTHEN_M7DEBUG - Slice Authentication Register
#define	SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_M7DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_M7DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK)

#define	SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_M7DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_M7DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK)

#define	SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK)

#define	SRC_AUTHEN_M7DEBUG_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_M7DEBUG_USER_SHIFT (24U)

#define	SRC_AUTHEN_M7DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_USER_SHIFT)) & SRC_AUTHEN_M7DEBUG_USER_MASK)

#define	SRC_AUTHEN_M7DEBUG_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_M7DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M7DEBUG_NONSECURE_MASK)

#define	SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK)

CTRL_M7DEBUG - Slice Control Register
#define	SRC_CTRL_M7DEBUG_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_M7DEBUG_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_M7DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M7DEBUG_SW_RESET_MASK)

SETPOINT_M7DEBUG - Slice Setpoint Config Register
#define	SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK)

DOMAIN_M7DEBUG - Slice Domain Config Register
#define	SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK)

STAT_M7DEBUG - Slice Status Register
#define	SRC_STAT_M7DEBUG_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_M7DEBUG_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_M7DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M7DEBUG_UNDER_RST_MASK)

#define	SRC_STAT_M7DEBUG_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_M7DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_HW_MASK)

#define	SRC_STAT_M7DEBUG_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_M7DEBUG_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_SW_MASK)

AUTHEN_USBPHY1 - Slice Authentication Register
#define	SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_USBPHY1_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_USBPHY1_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_USBPHY1_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK)

#define	SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_USBPHY1_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_USBPHY1_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_USBPHY1_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK)

#define	SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_USBPHY1_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK)

#define	SRC_AUTHEN_USBPHY1_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_USBPHY1_USER_SHIFT (24U)

#define	SRC_AUTHEN_USBPHY1_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_USER_SHIFT)) & SRC_AUTHEN_USBPHY1_USER_MASK)

#define	SRC_AUTHEN_USBPHY1_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_USBPHY1_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY1_NONSECURE_MASK)

#define	SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_USBPHY1_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK)

CTRL_USBPHY1 - Slice Control Register
#define	SRC_CTRL_USBPHY1_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_USBPHY1_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_USBPHY1_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY1_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY1_SW_RESET_MASK)

SETPOINT_USBPHY1 - Slice Setpoint Config Register
#define	SRC_SETPOINT_USBPHY1_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT0_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT1_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT2_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT3_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT4_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT5_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT6_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT7_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT8_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT9_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT10_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT11_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT12_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT13_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT14_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT15_MASK)

DOMAIN_USBPHY1 - Slice Domain Config Register
#define	SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_USBPHY1_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_USBPHY1_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_USBPHY1_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_USBPHY1_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_USBPHY1_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_USBPHY1_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_USBPHY1_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_USBPHY1_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK)

STAT_USBPHY1 - Slice Status Register
#define	SRC_STAT_USBPHY1_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_USBPHY1_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_USBPHY1_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY1_UNDER_RST_MASK)

#define	SRC_STAT_USBPHY1_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_USBPHY1_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_USBPHY1_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_HW_MASK)

#define	SRC_STAT_USBPHY1_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_USBPHY1_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_USBPHY1_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_SW_MASK)

AUTHEN_USBPHY2 - Slice Authentication Register
#define	SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_USBPHY2_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_USBPHY2_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_USBPHY2_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK)

#define	SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_USBPHY2_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_USBPHY2_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_USBPHY2_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK)

#define	SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_USBPHY2_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK)

#define	SRC_AUTHEN_USBPHY2_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_USBPHY2_USER_SHIFT (24U)

#define	SRC_AUTHEN_USBPHY2_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_USER_SHIFT)) & SRC_AUTHEN_USBPHY2_USER_MASK)

#define	SRC_AUTHEN_USBPHY2_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_USBPHY2_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY2_NONSECURE_MASK)

#define	SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_USBPHY2_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK)

CTRL_USBPHY2 - Slice Control Register
#define	SRC_CTRL_USBPHY2_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_USBPHY2_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_USBPHY2_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY2_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY2_SW_RESET_MASK)

SETPOINT_USBPHY2 - Slice Setpoint Config Register
#define	SRC_SETPOINT_USBPHY2_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT0_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT1_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT2_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT3_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT4_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT5_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT6_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT7_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT8_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT9_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT10_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT11_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT12_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT13_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT14_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT15_MASK)

DOMAIN_USBPHY2 - Slice Domain Config Register
#define	SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_USBPHY2_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_USBPHY2_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_USBPHY2_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_USBPHY2_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_USBPHY2_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_USBPHY2_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_USBPHY2_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_USBPHY2_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK)

STAT_USBPHY2 - Slice Status Register
#define	SRC_STAT_USBPHY2_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_USBPHY2_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_USBPHY2_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY2_UNDER_RST_MASK)

#define	SRC_STAT_USBPHY2_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_USBPHY2_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_USBPHY2_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_HW_MASK)

#define	SRC_STAT_USBPHY2_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_USBPHY2_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_USBPHY2_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_SW_MASK)

SCR - SRC Control Register
#define	SRC_SCR_BT_RELEASE_M4_MASK (0x1U)

#define	SRC_SCR_BT_RELEASE_M4_SHIFT (0U)

#define	SRC_SCR_BT_RELEASE_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M4_SHIFT)) & SRC_SCR_BT_RELEASE_M4_MASK)

#define	SRC_SCR_BT_RELEASE_M7_MASK (0x2U)

#define	SRC_SCR_BT_RELEASE_M7_SHIFT (1U)

#define	SRC_SCR_BT_RELEASE_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M7_SHIFT)) & SRC_SCR_BT_RELEASE_M7_MASK)

SRMR - SRC Reset Mode Register
#define	SRC_SRMR_WDOG_RESET_MODE_MASK (0x3U)

#define	SRC_SRMR_WDOG_RESET_MODE_SHIFT (0U)

#define	SRC_SRMR_WDOG_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG_RESET_MODE_MASK)

#define	SRC_SRMR_WDOG3_RESET_MODE_MASK (0xCU)

#define	SRC_SRMR_WDOG3_RESET_MODE_SHIFT (2U)

#define	SRC_SRMR_WDOG3_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG3_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG3_RESET_MODE_MASK)

#define	SRC_SRMR_WDOG4_RESET_MODE_MASK (0x30U)

#define	SRC_SRMR_WDOG4_RESET_MODE_SHIFT (4U)

#define	SRC_SRMR_WDOG4_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG4_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG4_RESET_MODE_MASK)

#define	SRC_SRMR_M4LOCKUP_RESET_MODE_MASK (0xC0U)

#define	SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT (6U)

#define	SRC_SRMR_M4LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M4LOCKUP_RESET_MODE_MASK)

#define	SRC_SRMR_M7LOCKUP_RESET_MODE_MASK (0x300U)

#define	SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT (8U)

#define	SRC_SRMR_M7LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M7LOCKUP_RESET_MODE_MASK)

#define	SRC_SRMR_M4REQ_RESET_MODE_MASK (0xC00U)

#define	SRC_SRMR_M4REQ_RESET_MODE_SHIFT (10U)

#define	SRC_SRMR_M4REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M4REQ_RESET_MODE_MASK)

#define	SRC_SRMR_M7REQ_RESET_MODE_MASK (0x3000U)

#define	SRC_SRMR_M7REQ_RESET_MODE_SHIFT (12U)

#define	SRC_SRMR_M7REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M7REQ_RESET_MODE_MASK)

#define	SRC_SRMR_TEMPSENSE_RESET_MODE_MASK (0xC000U)

#define	SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT (14U)

#define	SRC_SRMR_TEMPSENSE_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_SRMR_TEMPSENSE_RESET_MODE_MASK)

#define	SRC_SRMR_CSU_RESET_MODE_MASK (0x30000U)

#define	SRC_SRMR_CSU_RESET_MODE_SHIFT (16U)

#define	SRC_SRMR_CSU_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_CSU_RESET_MODE_SHIFT)) & SRC_SRMR_CSU_RESET_MODE_MASK)

#define	SRC_SRMR_JTAGSW_RESET_MODE_MASK (0xC0000U)

#define	SRC_SRMR_JTAGSW_RESET_MODE_SHIFT (18U)

#define	SRC_SRMR_JTAGSW_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_JTAGSW_RESET_MODE_SHIFT)) & SRC_SRMR_JTAGSW_RESET_MODE_MASK)

#define	SRC_SRMR_OVERVOLT_RESET_MODE_MASK (0x300000U)

#define	SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT (20U)

#define	SRC_SRMR_OVERVOLT_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT)) & SRC_SRMR_OVERVOLT_RESET_MODE_MASK)

SBMR1 - SRC Boot Mode Register 1
#define	SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)

#define	SRC_SBMR1_BOOT_CFG1_SHIFT (0U)

#define	SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)

#define	SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)

#define	SRC_SBMR1_BOOT_CFG2_SHIFT (8U)

#define	SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)

#define	SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)

#define	SRC_SBMR1_BOOT_CFG3_SHIFT (16U)

#define	SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)

#define	SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)

#define	SRC_SBMR1_BOOT_CFG4_SHIFT (24U)

#define	SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)

SBMR2 - SRC Boot Mode Register 2
#define	SRC_SBMR2_SEC_CONFIG_MASK (0x3U)

#define	SRC_SBMR2_SEC_CONFIG_SHIFT (0U)

#define	SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)

#define	SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)

#define	SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)

#define	SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)

#define	SRC_SBMR2_BMOD_MASK (0x3000000U)

#define	SRC_SBMR2_BMOD_SHIFT (24U)

#define	SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)

SRSR - SRC Reset Status Register
#define	SRC_SRSR_IPP_RESET_B_M7_MASK (0x1U)

#define	SRC_SRSR_IPP_RESET_B_M7_SHIFT (0U)

#define	SRC_SRSR_IPP_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_RESET_B_M7_MASK)

#define	SRC_SRSR_M7_REQUEST_M7_MASK (0x2U)

#define	SRC_SRSR_M7_REQUEST_M7_SHIFT (1U)

#define	SRC_SRSR_M7_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M7_SHIFT)) & SRC_SRSR_M7_REQUEST_M7_MASK)

#define	SRC_SRSR_M7_LOCKUP_M7_MASK (0x4U)

#define	SRC_SRSR_M7_LOCKUP_M7_SHIFT (2U)

#define	SRC_SRSR_M7_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M7_SHIFT)) & SRC_SRSR_M7_LOCKUP_M7_MASK)

#define	SRC_SRSR_CSU_RESET_B_M7_MASK (0x8U)

#define	SRC_SRSR_CSU_RESET_B_M7_SHIFT (3U)

#define	SRC_SRSR_CSU_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M7_SHIFT)) & SRC_SRSR_CSU_RESET_B_M7_MASK)

#define	SRC_SRSR_IPP_USER_RESET_B_M7_MASK (0x10U)

#define	SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT (4U)

#define	SRC_SRSR_IPP_USER_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M7_MASK)

#define	SRC_SRSR_WDOG_RST_B_M7_MASK (0x20U)

#define	SRC_SRSR_WDOG_RST_B_M7_SHIFT (5U)

#define	SRC_SRSR_WDOG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG_RST_B_M7_MASK)

#define	SRC_SRSR_JTAG_RST_B_M7_MASK (0x40U)

#define	SRC_SRSR_JTAG_RST_B_M7_SHIFT (6U)

#define	SRC_SRSR_JTAG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M7_SHIFT)) & SRC_SRSR_JTAG_RST_B_M7_MASK)

#define	SRC_SRSR_JTAG_SW_RST_M7_MASK (0x80U)

#define	SRC_SRSR_JTAG_SW_RST_M7_SHIFT (7U)

#define	SRC_SRSR_JTAG_SW_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M7_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M7_MASK)

#define	SRC_SRSR_WDOG3_RST_B_M7_MASK (0x100U)

#define	SRC_SRSR_WDOG3_RST_B_M7_SHIFT (8U)

#define	SRC_SRSR_WDOG3_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M7_MASK)

#define	SRC_SRSR_WDOG4_RST_B_M7_MASK (0x200U)

#define	SRC_SRSR_WDOG4_RST_B_M7_SHIFT (9U)

#define	SRC_SRSR_WDOG4_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M7_MASK)

#define	SRC_SRSR_TEMPSENSE_RST_B_M7_MASK (0x400U)

#define	SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT (10U)

#define	SRC_SRSR_TEMPSENSE_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M7_MASK)

#define	SRC_SRSR_M4_REQUEST_M7_MASK (0x800U)

#define	SRC_SRSR_M4_REQUEST_M7_SHIFT (11U)

#define	SRC_SRSR_M4_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M7_SHIFT)) & SRC_SRSR_M4_REQUEST_M7_MASK)

#define	SRC_SRSR_M4_LOCKUP_M7_MASK (0x1000U)

#define	SRC_SRSR_M4_LOCKUP_M7_SHIFT (12U)

#define	SRC_SRSR_M4_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M7_SHIFT)) & SRC_SRSR_M4_LOCKUP_M7_MASK)

#define	SRC_SRSR_OVERVOLT_RST_M7_MASK (0x2000U)

#define	SRC_SRSR_OVERVOLT_RST_M7_SHIFT (13U)

#define	SRC_SRSR_OVERVOLT_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M7_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M7_MASK)

#define	SRC_SRSR_CDOG_RST_M7_MASK (0x4000U)

#define	SRC_SRSR_CDOG_RST_M7_SHIFT (14U)

#define	SRC_SRSR_CDOG_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M7_SHIFT)) & SRC_SRSR_CDOG_RST_M7_MASK)

#define	SRC_SRSR_IPP_RESET_B_M4_MASK (0x10000U)

#define	SRC_SRSR_IPP_RESET_B_M4_SHIFT (16U)

#define	SRC_SRSR_IPP_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_RESET_B_M4_MASK)

#define	SRC_SRSR_M4_REQUEST_M4_MASK (0x20000U)

#define	SRC_SRSR_M4_REQUEST_M4_SHIFT (17U)

#define	SRC_SRSR_M4_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M4_SHIFT)) & SRC_SRSR_M4_REQUEST_M4_MASK)

#define	SRC_SRSR_M4_LOCKUP_M4_MASK (0x40000U)

#define	SRC_SRSR_M4_LOCKUP_M4_SHIFT (18U)

#define	SRC_SRSR_M4_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M4_SHIFT)) & SRC_SRSR_M4_LOCKUP_M4_MASK)

#define	SRC_SRSR_CSU_RESET_B_M4_MASK (0x80000U)

#define	SRC_SRSR_CSU_RESET_B_M4_SHIFT (19U)

#define	SRC_SRSR_CSU_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M4_SHIFT)) & SRC_SRSR_CSU_RESET_B_M4_MASK)

#define	SRC_SRSR_IPP_USER_RESET_B_M4_MASK (0x100000U)

#define	SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT (20U)

#define	SRC_SRSR_IPP_USER_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M4_MASK)

#define	SRC_SRSR_WDOG_RST_B_M4_MASK (0x200000U)

#define	SRC_SRSR_WDOG_RST_B_M4_SHIFT (21U)

#define	SRC_SRSR_WDOG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG_RST_B_M4_MASK)

#define	SRC_SRSR_JTAG_RST_B_M4_MASK (0x400000U)

#define	SRC_SRSR_JTAG_RST_B_M4_SHIFT (22U)

#define	SRC_SRSR_JTAG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M4_SHIFT)) & SRC_SRSR_JTAG_RST_B_M4_MASK)

#define	SRC_SRSR_JTAG_SW_RST_M4_MASK (0x800000U)

#define	SRC_SRSR_JTAG_SW_RST_M4_SHIFT (23U)

#define	SRC_SRSR_JTAG_SW_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M4_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M4_MASK)

#define	SRC_SRSR_WDOG3_RST_B_M4_MASK (0x1000000U)

#define	SRC_SRSR_WDOG3_RST_B_M4_SHIFT (24U)

#define	SRC_SRSR_WDOG3_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M4_MASK)

#define	SRC_SRSR_WDOG4_RST_B_M4_MASK (0x2000000U)

#define	SRC_SRSR_WDOG4_RST_B_M4_SHIFT (25U)

#define	SRC_SRSR_WDOG4_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M4_MASK)

#define	SRC_SRSR_TEMPSENSE_RST_B_M4_MASK (0x4000000U)

#define	SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT (26U)

#define	SRC_SRSR_TEMPSENSE_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M4_MASK)

#define	SRC_SRSR_M7_REQUEST_M4_MASK (0x8000000U)

#define	SRC_SRSR_M7_REQUEST_M4_SHIFT (27U)

#define	SRC_SRSR_M7_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M4_SHIFT)) & SRC_SRSR_M7_REQUEST_M4_MASK)

#define	SRC_SRSR_M7_LOCKUP_M4_MASK (0x10000000U)

#define	SRC_SRSR_M7_LOCKUP_M4_SHIFT (28U)

#define	SRC_SRSR_M7_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M4_SHIFT)) & SRC_SRSR_M7_LOCKUP_M4_MASK)

#define	SRC_SRSR_OVERVOLT_RST_M4_MASK (0x20000000U)

#define	SRC_SRSR_OVERVOLT_RST_M4_SHIFT (29U)

#define	SRC_SRSR_OVERVOLT_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M4_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M4_MASK)

#define	SRC_SRSR_CDOG_RST_M4_MASK (0x40000000U)

#define	SRC_SRSR_CDOG_RST_M4_SHIFT (30U)

#define	SRC_SRSR_CDOG_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M4_SHIFT)) & SRC_SRSR_CDOG_RST_M4_MASK)

GPR - SRC General Purpose Register
#define	SRC_GPR_GPR_MASK (0xFFFFFFFFU)

#define	SRC_GPR_GPR_SHIFT (0U)

#define	SRC_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_GPR_SHIFT)) & SRC_GPR_GPR_MASK)

AUTHEN_MEGA - Slice Authentication Register
#define	SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_MEGA_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_MEGA_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_MEGA_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_MEGA_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_MODE_MASK)

#define	SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_MEGA_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_MEGA_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_MEGA_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_MEGA_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT)) & SRC_AUTHEN_MEGA_WHITE_LIST_MASK)

#define	SRC_AUTHEN_MEGA_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_MEGA_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_LIST_MASK)

#define	SRC_AUTHEN_MEGA_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_MEGA_USER_SHIFT (24U)

#define	SRC_AUTHEN_MEGA_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_USER_SHIFT)) & SRC_AUTHEN_MEGA_USER_MASK)

#define	SRC_AUTHEN_MEGA_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_MEGA_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_MEGA_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_NONSECURE_SHIFT)) & SRC_AUTHEN_MEGA_NONSECURE_MASK)

#define	SRC_AUTHEN_MEGA_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_MEGA_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_SETTING_MASK)

CTRL_MEGA - Slice Control Register
#define	SRC_CTRL_MEGA_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_MEGA_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_MEGA_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_MEGA_SW_RESET_SHIFT)) & SRC_CTRL_MEGA_SW_RESET_MASK)

SETPOINT_MEGA - Slice Setpoint Config Register
#define	SRC_SETPOINT_MEGA_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_MEGA_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_MEGA_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT0_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT0_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_MEGA_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_MEGA_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT1_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT1_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_MEGA_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_MEGA_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT2_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT2_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_MEGA_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_MEGA_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT3_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT3_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_MEGA_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_MEGA_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT4_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT4_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_MEGA_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_MEGA_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT5_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT5_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_MEGA_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_MEGA_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT6_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT6_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_MEGA_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_MEGA_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT7_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT7_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_MEGA_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_MEGA_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT8_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT8_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_MEGA_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_MEGA_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT9_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT9_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_MEGA_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_MEGA_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT10_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT10_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_MEGA_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_MEGA_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT11_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT11_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_MEGA_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_MEGA_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT12_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT12_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_MEGA_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_MEGA_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT13_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT13_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_MEGA_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_MEGA_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT14_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT14_MASK)

#define	SRC_SETPOINT_MEGA_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_MEGA_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_MEGA_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT15_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT15_MASK)

DOMAIN_MEGA - Slice Domain Config Register
#define	SRC_DOMAIN_MEGA_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_MEGA_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_RUN_MASK)

#define	SRC_DOMAIN_MEGA_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_MEGA_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_MEGA_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_MEGA_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_STOP_MASK)

#define	SRC_DOMAIN_MEGA_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_MEGA_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_MEGA_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_MEGA_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_RUN_MASK)

#define	SRC_DOMAIN_MEGA_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_MEGA_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_MEGA_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_MEGA_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_STOP_MASK)

#define	SRC_DOMAIN_MEGA_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_MEGA_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_SUSP_MASK)

STAT_MEGA - Slice Status Register
#define	SRC_STAT_MEGA_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_MEGA_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_MEGA_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_UNDER_RST_SHIFT)) & SRC_STAT_MEGA_UNDER_RST_MASK)

#define	SRC_STAT_MEGA_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_MEGA_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_MEGA_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_HW_SHIFT)) & SRC_STAT_MEGA_RST_BY_HW_MASK)

#define	SRC_STAT_MEGA_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_MEGA_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_MEGA_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_SW_SHIFT)) & SRC_STAT_MEGA_RST_BY_SW_MASK)

AUTHEN_DISPLAY - Slice Authentication Register
#define	SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_DISPLAY_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_DISPLAY_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_DISPLAY_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK)

#define	SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_DISPLAY_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_DISPLAY_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_DISPLAY_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK)

#define	SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_DISPLAY_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK)

#define	SRC_AUTHEN_DISPLAY_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_DISPLAY_USER_SHIFT (24U)

#define	SRC_AUTHEN_DISPLAY_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_USER_SHIFT)) & SRC_AUTHEN_DISPLAY_USER_MASK)

#define	SRC_AUTHEN_DISPLAY_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_DISPLAY_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT)) & SRC_AUTHEN_DISPLAY_NONSECURE_MASK)

#define	SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_DISPLAY_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK)

CTRL_DISPLAY - Slice Control Register
#define	SRC_CTRL_DISPLAY_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_DISPLAY_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_DISPLAY_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_DISPLAY_SW_RESET_SHIFT)) & SRC_CTRL_DISPLAY_SW_RESET_MASK)

SETPOINT_DISPLAY - Slice Setpoint Config Register
#define	SRC_SETPOINT_DISPLAY_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT0_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT1_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT2_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT3_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT4_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT5_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT6_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT7_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT8_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT9_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT10_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT11_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT12_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT13_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT14_MASK)

#define	SRC_SETPOINT_DISPLAY_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_DISPLAY_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT15_MASK)

DOMAIN_DISPLAY - Slice Domain Config Register
#define	SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_DISPLAY_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_DISPLAY_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_DISPLAY_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_DISPLAY_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_DISPLAY_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_DISPLAY_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_DISPLAY_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK)

#define	SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_DISPLAY_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK)

STAT_DISPLAY - Slice Status Register
#define	SRC_STAT_DISPLAY_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_DISPLAY_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_DISPLAY_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_UNDER_RST_SHIFT)) & SRC_STAT_DISPLAY_UNDER_RST_MASK)

#define	SRC_STAT_DISPLAY_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_DISPLAY_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_DISPLAY_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_HW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_HW_MASK)

#define	SRC_STAT_DISPLAY_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_DISPLAY_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_DISPLAY_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_SW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_SW_MASK)

AUTHEN_WAKEUP - Slice Authentication Register
#define	SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_WAKEUP_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_WAKEUP_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_WAKEUP_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK)

#define	SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_WAKEUP_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_WAKEUP_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_WAKEUP_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK)

#define	SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_WAKEUP_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK)

#define	SRC_AUTHEN_WAKEUP_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_WAKEUP_USER_SHIFT (24U)

#define	SRC_AUTHEN_WAKEUP_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_USER_SHIFT)) & SRC_AUTHEN_WAKEUP_USER_MASK)

#define	SRC_AUTHEN_WAKEUP_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_WAKEUP_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT)) & SRC_AUTHEN_WAKEUP_NONSECURE_MASK)

#define	SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_WAKEUP_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK)

CTRL_WAKEUP - Slice Control Register
#define	SRC_CTRL_WAKEUP_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_WAKEUP_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_WAKEUP_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_WAKEUP_SW_RESET_SHIFT)) & SRC_CTRL_WAKEUP_SW_RESET_MASK)

SETPOINT_WAKEUP - Slice Setpoint Config Register
#define	SRC_SETPOINT_WAKEUP_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT0_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT1_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT2_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT3_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT4_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT5_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT6_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT7_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT8_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT9_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT10_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT11_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT12_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT13_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT14_MASK)

#define	SRC_SETPOINT_WAKEUP_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_WAKEUP_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT15_MASK)

DOMAIN_WAKEUP - Slice Domain Config Register
#define	SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_WAKEUP_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_WAKEUP_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_WAKEUP_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_WAKEUP_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_WAKEUP_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_WAKEUP_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_WAKEUP_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK)

#define	SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_WAKEUP_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK)

STAT_WAKEUP - Slice Status Register
#define	SRC_STAT_WAKEUP_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_WAKEUP_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_WAKEUP_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_UNDER_RST_SHIFT)) & SRC_STAT_WAKEUP_UNDER_RST_MASK)

#define	SRC_STAT_WAKEUP_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_WAKEUP_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_WAKEUP_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_HW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_HW_MASK)

#define	SRC_STAT_WAKEUP_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_WAKEUP_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_WAKEUP_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_SW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_SW_MASK)

AUTHEN_M4CORE - Slice Authentication Register
#define	SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_M4CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_M4CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_M4CORE_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_M4CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_MODE_MASK)

#define	SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_M4CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_M4CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_M4CORE_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_M4CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_WHITE_LIST_MASK)

#define	SRC_AUTHEN_M4CORE_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_M4CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_LIST_MASK)

#define	SRC_AUTHEN_M4CORE_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_M4CORE_USER_SHIFT (24U)

#define	SRC_AUTHEN_M4CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_USER_SHIFT)) & SRC_AUTHEN_M4CORE_USER_MASK)

#define	SRC_AUTHEN_M4CORE_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_M4CORE_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_M4CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M4CORE_NONSECURE_MASK)

#define	SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_M4CORE_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK)

CTRL_M4CORE - Slice Control Register
#define	SRC_CTRL_M4CORE_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_M4CORE_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_M4CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4CORE_SW_RESET_SHIFT)) & SRC_CTRL_M4CORE_SW_RESET_MASK)

SETPOINT_M4CORE - Slice Setpoint Config Register
#define	SRC_SETPOINT_M4CORE_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_M4CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT0_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_M4CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT1_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_M4CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT2_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_M4CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT3_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_M4CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT4_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_M4CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT5_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_M4CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT6_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_M4CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT7_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_M4CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT8_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_M4CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT9_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_M4CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT10_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_M4CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT11_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_M4CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT12_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_M4CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT13_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_M4CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT14_MASK)

#define	SRC_SETPOINT_M4CORE_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_M4CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT15_MASK)

DOMAIN_M4CORE - Slice Domain Config Register
#define	SRC_DOMAIN_M4CORE_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_M4CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_RUN_MASK)

#define	SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_M4CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_M4CORE_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_M4CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_STOP_MASK)

#define	SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_M4CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_M4CORE_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_M4CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_RUN_MASK)

#define	SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_M4CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_M4CORE_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_M4CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_STOP_MASK)

#define	SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_M4CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK)

STAT_M4CORE - Slice Status Register
#define	SRC_STAT_M4CORE_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_M4CORE_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_M4CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_UNDER_RST_SHIFT)) & SRC_STAT_M4CORE_UNDER_RST_MASK)

#define	SRC_STAT_M4CORE_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_M4CORE_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_M4CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_HW_MASK)

#define	SRC_STAT_M4CORE_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_M4CORE_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_M4CORE_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_SW_MASK)

AUTHEN_M7CORE - Slice Authentication Register
#define	SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_M7CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_M7CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_M7CORE_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_M7CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_MODE_MASK)

#define	SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_M7CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_M7CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_M7CORE_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_M7CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_WHITE_LIST_MASK)

#define	SRC_AUTHEN_M7CORE_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_M7CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_LIST_MASK)

#define	SRC_AUTHEN_M7CORE_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_M7CORE_USER_SHIFT (24U)

#define	SRC_AUTHEN_M7CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_USER_SHIFT)) & SRC_AUTHEN_M7CORE_USER_MASK)

#define	SRC_AUTHEN_M7CORE_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_M7CORE_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_M7CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M7CORE_NONSECURE_MASK)

#define	SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_M7CORE_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK)

CTRL_M7CORE - Slice Control Register
#define	SRC_CTRL_M7CORE_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_M7CORE_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_M7CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7CORE_SW_RESET_SHIFT)) & SRC_CTRL_M7CORE_SW_RESET_MASK)

SETPOINT_M7CORE - Slice Setpoint Config Register
#define	SRC_SETPOINT_M7CORE_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_M7CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT0_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_M7CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT1_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_M7CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT2_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_M7CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT3_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_M7CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT4_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_M7CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT5_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_M7CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT6_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_M7CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT7_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_M7CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT8_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_M7CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT9_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_M7CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT10_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_M7CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT11_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_M7CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT12_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_M7CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT13_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_M7CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT14_MASK)

#define	SRC_SETPOINT_M7CORE_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_M7CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT15_MASK)

DOMAIN_M7CORE - Slice Domain Config Register
#define	SRC_DOMAIN_M7CORE_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_M7CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_RUN_MASK)

#define	SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_M7CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_M7CORE_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_M7CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_STOP_MASK)

#define	SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_M7CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_M7CORE_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_M7CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_RUN_MASK)

#define	SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_M7CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_M7CORE_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_M7CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_STOP_MASK)

#define	SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_M7CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK)

STAT_M7CORE - Slice Status Register
#define	SRC_STAT_M7CORE_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_M7CORE_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_M7CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_UNDER_RST_SHIFT)) & SRC_STAT_M7CORE_UNDER_RST_MASK)

#define	SRC_STAT_M7CORE_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_M7CORE_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_M7CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_HW_MASK)

#define	SRC_STAT_M7CORE_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_M7CORE_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_M7CORE_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_SW_MASK)

AUTHEN_M4DEBUG - Slice Authentication Register
#define	SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_M4DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_M4DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK)

#define	SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_M4DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_M4DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK)

#define	SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK)

#define	SRC_AUTHEN_M4DEBUG_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_M4DEBUG_USER_SHIFT (24U)

#define	SRC_AUTHEN_M4DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_USER_SHIFT)) & SRC_AUTHEN_M4DEBUG_USER_MASK)

#define	SRC_AUTHEN_M4DEBUG_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_M4DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M4DEBUG_NONSECURE_MASK)

#define	SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_M4DEBUG_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK)

CTRL_M4DEBUG - Slice Control Register
#define	SRC_CTRL_M4DEBUG_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_M4DEBUG_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_M4DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M4DEBUG_SW_RESET_MASK)

SETPOINT_M4DEBUG - Slice Setpoint Config Register
#define	SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_M4DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK)

DOMAIN_M4DEBUG - Slice Domain Config Register
#define	SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_M4DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK)

#define	SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_M4DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK)

STAT_M4DEBUG - Slice Status Register
#define	SRC_STAT_M4DEBUG_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_M4DEBUG_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_M4DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M4DEBUG_UNDER_RST_MASK)

#define	SRC_STAT_M4DEBUG_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_M4DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_HW_MASK)

#define	SRC_STAT_M4DEBUG_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_M4DEBUG_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_SW_MASK)

AUTHEN_M7DEBUG - Slice Authentication Register
#define	SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_M7DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_M7DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK)

#define	SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_M7DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_M7DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK)

#define	SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK)

#define	SRC_AUTHEN_M7DEBUG_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_M7DEBUG_USER_SHIFT (24U)

#define	SRC_AUTHEN_M7DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_USER_SHIFT)) & SRC_AUTHEN_M7DEBUG_USER_MASK)

#define	SRC_AUTHEN_M7DEBUG_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_M7DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M7DEBUG_NONSECURE_MASK)

#define	SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_M7DEBUG_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK)

CTRL_M7DEBUG - Slice Control Register
#define	SRC_CTRL_M7DEBUG_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_M7DEBUG_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_M7DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M7DEBUG_SW_RESET_MASK)

SETPOINT_M7DEBUG - Slice Setpoint Config Register
#define	SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_M7DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK)

DOMAIN_M7DEBUG - Slice Domain Config Register
#define	SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_M7DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK)

#define	SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_M7DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK)

STAT_M7DEBUG - Slice Status Register
#define	SRC_STAT_M7DEBUG_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_M7DEBUG_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_M7DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M7DEBUG_UNDER_RST_MASK)

#define	SRC_STAT_M7DEBUG_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_M7DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_HW_MASK)

#define	SRC_STAT_M7DEBUG_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_M7DEBUG_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_SW_MASK)

AUTHEN_USBPHY1 - Slice Authentication Register
#define	SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_USBPHY1_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_USBPHY1_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_USBPHY1_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK)

#define	SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_USBPHY1_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_USBPHY1_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_USBPHY1_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK)

#define	SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_USBPHY1_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK)

#define	SRC_AUTHEN_USBPHY1_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_USBPHY1_USER_SHIFT (24U)

#define	SRC_AUTHEN_USBPHY1_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_USER_SHIFT)) & SRC_AUTHEN_USBPHY1_USER_MASK)

#define	SRC_AUTHEN_USBPHY1_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_USBPHY1_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY1_NONSECURE_MASK)

#define	SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_USBPHY1_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK)

CTRL_USBPHY1 - Slice Control Register
#define	SRC_CTRL_USBPHY1_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_USBPHY1_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_USBPHY1_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY1_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY1_SW_RESET_MASK)

SETPOINT_USBPHY1 - Slice Setpoint Config Register
#define	SRC_SETPOINT_USBPHY1_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT0_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT1_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT2_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT3_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT4_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT5_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT6_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT7_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT8_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT9_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT10_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT11_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT12_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT13_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT14_MASK)

#define	SRC_SETPOINT_USBPHY1_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_USBPHY1_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT15_MASK)

DOMAIN_USBPHY1 - Slice Domain Config Register
#define	SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_USBPHY1_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_USBPHY1_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_USBPHY1_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_USBPHY1_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_USBPHY1_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_USBPHY1_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_USBPHY1_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK)

#define	SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_USBPHY1_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK)

STAT_USBPHY1 - Slice Status Register
#define	SRC_STAT_USBPHY1_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_USBPHY1_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_USBPHY1_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY1_UNDER_RST_MASK)

#define	SRC_STAT_USBPHY1_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_USBPHY1_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_USBPHY1_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_HW_MASK)

#define	SRC_STAT_USBPHY1_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_USBPHY1_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_USBPHY1_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_SW_MASK)

AUTHEN_USBPHY2 - Slice Authentication Register
#define	SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK (0x1U)

#define	SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT (0U)

#define	SRC_AUTHEN_USBPHY2_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK)

#define	SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK (0x2U)

#define	SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT (1U)

#define	SRC_AUTHEN_USBPHY2_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK)

#define	SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK (0x80U)

#define	SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT (7U)

#define	SRC_AUTHEN_USBPHY2_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK)

#define	SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK (0xF00U)

#define	SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT (8U)

#define	SRC_AUTHEN_USBPHY2_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK)

#define	SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK (0x8000U)

#define	SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT (15U)

#define	SRC_AUTHEN_USBPHY2_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK)

#define	SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK (0xF0000U)

#define	SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT (16U)

#define	SRC_AUTHEN_USBPHY2_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK)

#define	SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK (0x800000U)

#define	SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT (23U)

#define	SRC_AUTHEN_USBPHY2_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK)

#define	SRC_AUTHEN_USBPHY2_USER_MASK (0x1000000U)

#define	SRC_AUTHEN_USBPHY2_USER_SHIFT (24U)

#define	SRC_AUTHEN_USBPHY2_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_USER_SHIFT)) & SRC_AUTHEN_USBPHY2_USER_MASK)

#define	SRC_AUTHEN_USBPHY2_NONSECURE_MASK (0x2000000U)

#define	SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT (25U)

#define	SRC_AUTHEN_USBPHY2_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY2_NONSECURE_MASK)

#define	SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK (0x80000000U)

#define	SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT (31U)

#define	SRC_AUTHEN_USBPHY2_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK)

CTRL_USBPHY2 - Slice Control Register
#define	SRC_CTRL_USBPHY2_SW_RESET_MASK (0x1U)

#define	SRC_CTRL_USBPHY2_SW_RESET_SHIFT (0U)

#define	SRC_CTRL_USBPHY2_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY2_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY2_SW_RESET_MASK)

SETPOINT_USBPHY2 - Slice Setpoint Config Register
#define	SRC_SETPOINT_USBPHY2_SETPOINT0_MASK (0x1U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT (0U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT0_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT1_MASK (0x2U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT (1U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT1_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT2_MASK (0x4U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT (2U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT2_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT3_MASK (0x8U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT (3U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT3_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT4_MASK (0x10U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT (4U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT4_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT5_MASK (0x20U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT (5U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT5_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT6_MASK (0x40U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT (6U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT6_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT7_MASK (0x80U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT (7U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT7_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT8_MASK (0x100U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT (8U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT8_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT9_MASK (0x200U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT (9U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT9_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT10_MASK (0x400U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT (10U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT10_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT11_MASK (0x800U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT (11U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT11_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT12_MASK (0x1000U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT (12U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT12_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT13_MASK (0x2000U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT (13U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT13_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT14_MASK (0x4000U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT (14U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT14_MASK)

#define	SRC_SETPOINT_USBPHY2_SETPOINT15_MASK (0x8000U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT (15U)

#define	SRC_SETPOINT_USBPHY2_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT15_MASK)

DOMAIN_USBPHY2 - Slice Domain Config Register
#define	SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK (0x1U)

#define	SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT (0U)

#define	SRC_DOMAIN_USBPHY2_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK (0x2U)

#define	SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT (1U)

#define	SRC_DOMAIN_USBPHY2_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK (0x4U)

#define	SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT (2U)

#define	SRC_DOMAIN_USBPHY2_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK (0x8U)

#define	SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT (3U)

#define	SRC_DOMAIN_USBPHY2_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK (0x10U)

#define	SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT (4U)

#define	SRC_DOMAIN_USBPHY2_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK (0x20U)

#define	SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT (5U)

#define	SRC_DOMAIN_USBPHY2_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK (0x40U)

#define	SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT (6U)

#define	SRC_DOMAIN_USBPHY2_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK)

#define	SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK (0x80U)

#define	SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT (7U)

#define	SRC_DOMAIN_USBPHY2_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK)

STAT_USBPHY2 - Slice Status Register
#define	SRC_STAT_USBPHY2_UNDER_RST_MASK (0x1U)

#define	SRC_STAT_USBPHY2_UNDER_RST_SHIFT (0U)

#define	SRC_STAT_USBPHY2_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY2_UNDER_RST_MASK)

#define	SRC_STAT_USBPHY2_RST_BY_HW_MASK (0x4U)

#define	SRC_STAT_USBPHY2_RST_BY_HW_SHIFT (2U)

#define	SRC_STAT_USBPHY2_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_HW_MASK)

#define	SRC_STAT_USBPHY2_RST_BY_SW_MASK (0x8U)

#define	SRC_STAT_USBPHY2_RST_BY_SW_SHIFT (3U)

#define	SRC_STAT_USBPHY2_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_SW_MASK)

Detailed Description

Macro Definition Documentation

◆ SRC_AUTHEN_DISPLAY_DOMAIN_MODE [1/2]

#define SRC_AUTHEN_DISPLAY_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_DISPLAY_DOMAIN_MODE [2/2]

#define SRC_AUTHEN_DISPLAY_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_DISPLAY_LOCK_ASSIGN [1/2]

#define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_DISPLAY_LOCK_ASSIGN [2/2]

#define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_DISPLAY_LOCK_LIST [1/2]

#define SRC_AUTHEN_DISPLAY_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_DISPLAY_LOCK_LIST [2/2]

#define SRC_AUTHEN_DISPLAY_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_DISPLAY_LOCK_MODE [1/2]

#define SRC_AUTHEN_DISPLAY_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_DISPLAY_LOCK_MODE [2/2]

#define SRC_AUTHEN_DISPLAY_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_DISPLAY_LOCK_SETTING [1/2]

#define SRC_AUTHEN_DISPLAY_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_DISPLAY_LOCK_SETTING [2/2]

#define SRC_AUTHEN_DISPLAY_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_DISPLAY_NONSECURE [1/2]

#define SRC_AUTHEN_DISPLAY_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT)) & SRC_AUTHEN_DISPLAY_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_DISPLAY_NONSECURE [2/2]

#define SRC_AUTHEN_DISPLAY_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT)) & SRC_AUTHEN_DISPLAY_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_DISPLAY_SETPOINT_MODE [1/2]

#define SRC_AUTHEN_DISPLAY_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_DISPLAY_SETPOINT_MODE [2/2]

#define SRC_AUTHEN_DISPLAY_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_DISPLAY_USER [1/2]

#define SRC_AUTHEN_DISPLAY_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_USER_SHIFT)) & SRC_AUTHEN_DISPLAY_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_DISPLAY_USER [2/2]

#define SRC_AUTHEN_DISPLAY_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_USER_SHIFT)) & SRC_AUTHEN_DISPLAY_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_DISPLAY_WHITE_LIST [1/2]

#define SRC_AUTHEN_DISPLAY_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_DISPLAY_WHITE_LIST [2/2]

#define SRC_AUTHEN_DISPLAY_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_M4CORE_DOMAIN_MODE [1/2]

#define SRC_AUTHEN_M4CORE_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_M4CORE_DOMAIN_MODE [2/2]

#define SRC_AUTHEN_M4CORE_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_M4CORE_LOCK_ASSIGN [1/2]

#define SRC_AUTHEN_M4CORE_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_M4CORE_LOCK_ASSIGN [2/2]

#define SRC_AUTHEN_M4CORE_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_M4CORE_LOCK_LIST [1/2]

#define SRC_AUTHEN_M4CORE_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_M4CORE_LOCK_LIST [2/2]

#define SRC_AUTHEN_M4CORE_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_M4CORE_LOCK_MODE [1/2]

#define SRC_AUTHEN_M4CORE_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_M4CORE_LOCK_MODE [2/2]

#define SRC_AUTHEN_M4CORE_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_M4CORE_LOCK_SETTING [1/2]

#define SRC_AUTHEN_M4CORE_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_M4CORE_LOCK_SETTING [2/2]

#define SRC_AUTHEN_M4CORE_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_M4CORE_NONSECURE [1/2]

#define SRC_AUTHEN_M4CORE_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M4CORE_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_M4CORE_NONSECURE [2/2]

#define SRC_AUTHEN_M4CORE_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M4CORE_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_M4CORE_SETPOINT_MODE [1/2]

#define SRC_AUTHEN_M4CORE_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_M4CORE_SETPOINT_MODE [2/2]

#define SRC_AUTHEN_M4CORE_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_M4CORE_USER [1/2]

#define SRC_AUTHEN_M4CORE_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_USER_SHIFT)) & SRC_AUTHEN_M4CORE_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_M4CORE_USER [2/2]

#define SRC_AUTHEN_M4CORE_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_USER_SHIFT)) & SRC_AUTHEN_M4CORE_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_M4CORE_WHITE_LIST [1/2]

#define SRC_AUTHEN_M4CORE_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_M4CORE_WHITE_LIST [2/2]

#define SRC_AUTHEN_M4CORE_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_M4DEBUG_DOMAIN_MODE [1/2]

#define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_M4DEBUG_DOMAIN_MODE [2/2]

#define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN [1/2]

#define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN [2/2]

#define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_M4DEBUG_LOCK_LIST [1/2]

#define SRC_AUTHEN_M4DEBUG_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_M4DEBUG_LOCK_LIST [2/2]

#define SRC_AUTHEN_M4DEBUG_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_M4DEBUG_LOCK_MODE [1/2]

#define SRC_AUTHEN_M4DEBUG_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_M4DEBUG_LOCK_MODE [2/2]

#define SRC_AUTHEN_M4DEBUG_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_M4DEBUG_LOCK_SETTING [1/2]

#define SRC_AUTHEN_M4DEBUG_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_M4DEBUG_LOCK_SETTING [2/2]

#define SRC_AUTHEN_M4DEBUG_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_M4DEBUG_NONSECURE [1/2]

#define SRC_AUTHEN_M4DEBUG_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M4DEBUG_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_M4DEBUG_NONSECURE [2/2]

#define SRC_AUTHEN_M4DEBUG_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M4DEBUG_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_M4DEBUG_SETPOINT_MODE [1/2]

#define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_M4DEBUG_SETPOINT_MODE [2/2]

#define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_M4DEBUG_USER [1/2]

#define SRC_AUTHEN_M4DEBUG_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_USER_SHIFT)) & SRC_AUTHEN_M4DEBUG_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_M4DEBUG_USER [2/2]

#define SRC_AUTHEN_M4DEBUG_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_USER_SHIFT)) & SRC_AUTHEN_M4DEBUG_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_M4DEBUG_WHITE_LIST [1/2]

#define SRC_AUTHEN_M4DEBUG_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_M4DEBUG_WHITE_LIST [2/2]

#define SRC_AUTHEN_M4DEBUG_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_M7CORE_DOMAIN_MODE [1/2]

#define SRC_AUTHEN_M7CORE_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_M7CORE_DOMAIN_MODE [2/2]

#define SRC_AUTHEN_M7CORE_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_M7CORE_LOCK_ASSIGN [1/2]

#define SRC_AUTHEN_M7CORE_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_M7CORE_LOCK_ASSIGN [2/2]

#define SRC_AUTHEN_M7CORE_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_M7CORE_LOCK_LIST [1/2]

#define SRC_AUTHEN_M7CORE_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_M7CORE_LOCK_LIST [2/2]

#define SRC_AUTHEN_M7CORE_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_M7CORE_LOCK_MODE [1/2]

#define SRC_AUTHEN_M7CORE_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_M7CORE_LOCK_MODE [2/2]

#define SRC_AUTHEN_M7CORE_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_M7CORE_LOCK_SETTING [1/2]

#define SRC_AUTHEN_M7CORE_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_M7CORE_LOCK_SETTING [2/2]

#define SRC_AUTHEN_M7CORE_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_M7CORE_NONSECURE [1/2]

#define SRC_AUTHEN_M7CORE_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M7CORE_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_M7CORE_NONSECURE [2/2]

#define SRC_AUTHEN_M7CORE_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M7CORE_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_M7CORE_SETPOINT_MODE [1/2]

#define SRC_AUTHEN_M7CORE_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_M7CORE_SETPOINT_MODE [2/2]

#define SRC_AUTHEN_M7CORE_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_M7CORE_USER [1/2]

#define SRC_AUTHEN_M7CORE_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_USER_SHIFT)) & SRC_AUTHEN_M7CORE_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_M7CORE_USER [2/2]

#define SRC_AUTHEN_M7CORE_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_USER_SHIFT)) & SRC_AUTHEN_M7CORE_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_M7CORE_WHITE_LIST [1/2]

#define SRC_AUTHEN_M7CORE_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_M7CORE_WHITE_LIST [2/2]

#define SRC_AUTHEN_M7CORE_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_M7DEBUG_DOMAIN_MODE [1/2]

#define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_M7DEBUG_DOMAIN_MODE [2/2]

#define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN [1/2]

#define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN [2/2]

#define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_M7DEBUG_LOCK_LIST [1/2]

#define SRC_AUTHEN_M7DEBUG_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_M7DEBUG_LOCK_LIST [2/2]

#define SRC_AUTHEN_M7DEBUG_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_M7DEBUG_LOCK_MODE [1/2]

#define SRC_AUTHEN_M7DEBUG_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_M7DEBUG_LOCK_MODE [2/2]

#define SRC_AUTHEN_M7DEBUG_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_M7DEBUG_LOCK_SETTING [1/2]

#define SRC_AUTHEN_M7DEBUG_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_M7DEBUG_LOCK_SETTING [2/2]

#define SRC_AUTHEN_M7DEBUG_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_M7DEBUG_NONSECURE [1/2]

#define SRC_AUTHEN_M7DEBUG_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M7DEBUG_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_M7DEBUG_NONSECURE [2/2]

#define SRC_AUTHEN_M7DEBUG_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M7DEBUG_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_M7DEBUG_SETPOINT_MODE [1/2]

#define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_M7DEBUG_SETPOINT_MODE [2/2]

#define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_M7DEBUG_USER [1/2]

#define SRC_AUTHEN_M7DEBUG_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_USER_SHIFT)) & SRC_AUTHEN_M7DEBUG_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_M7DEBUG_USER [2/2]

#define SRC_AUTHEN_M7DEBUG_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_USER_SHIFT)) & SRC_AUTHEN_M7DEBUG_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_M7DEBUG_WHITE_LIST [1/2]

#define SRC_AUTHEN_M7DEBUG_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_M7DEBUG_WHITE_LIST [2/2]

#define SRC_AUTHEN_M7DEBUG_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_MEGA_DOMAIN_MODE [1/2]

#define SRC_AUTHEN_MEGA_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_MEGA_DOMAIN_MODE [2/2]

#define SRC_AUTHEN_MEGA_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_MEGA_LOCK_ASSIGN [1/2]

#define SRC_AUTHEN_MEGA_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_MEGA_LOCK_ASSIGN [2/2]

#define SRC_AUTHEN_MEGA_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_MEGA_LOCK_LIST [1/2]

#define SRC_AUTHEN_MEGA_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_MEGA_LOCK_LIST [2/2]

#define SRC_AUTHEN_MEGA_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_MEGA_LOCK_MODE [1/2]

#define SRC_AUTHEN_MEGA_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_MEGA_LOCK_MODE [2/2]

#define SRC_AUTHEN_MEGA_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_MEGA_LOCK_SETTING [1/2]

#define SRC_AUTHEN_MEGA_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_MEGA_LOCK_SETTING [2/2]

#define SRC_AUTHEN_MEGA_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_MEGA_NONSECURE [1/2]

#define SRC_AUTHEN_MEGA_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_NONSECURE_SHIFT)) & SRC_AUTHEN_MEGA_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_MEGA_NONSECURE [2/2]

#define SRC_AUTHEN_MEGA_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_NONSECURE_SHIFT)) & SRC_AUTHEN_MEGA_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_MEGA_SETPOINT_MODE [1/2]

#define SRC_AUTHEN_MEGA_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_MEGA_SETPOINT_MODE [2/2]

#define SRC_AUTHEN_MEGA_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_MEGA_USER [1/2]

#define SRC_AUTHEN_MEGA_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_USER_SHIFT)) & SRC_AUTHEN_MEGA_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_MEGA_USER [2/2]

#define SRC_AUTHEN_MEGA_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_USER_SHIFT)) & SRC_AUTHEN_MEGA_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_MEGA_WHITE_LIST [1/2]

#define SRC_AUTHEN_MEGA_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT)) & SRC_AUTHEN_MEGA_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_MEGA_WHITE_LIST [2/2]

#define SRC_AUTHEN_MEGA_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT)) & SRC_AUTHEN_MEGA_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_USBPHY1_DOMAIN_MODE [1/2]

#define SRC_AUTHEN_USBPHY1_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_USBPHY1_DOMAIN_MODE [2/2]

#define SRC_AUTHEN_USBPHY1_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_USBPHY1_LOCK_ASSIGN [1/2]

#define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_USBPHY1_LOCK_ASSIGN [2/2]

#define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_USBPHY1_LOCK_LIST [1/2]

#define SRC_AUTHEN_USBPHY1_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_USBPHY1_LOCK_LIST [2/2]

#define SRC_AUTHEN_USBPHY1_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_USBPHY1_LOCK_MODE [1/2]

#define SRC_AUTHEN_USBPHY1_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_USBPHY1_LOCK_MODE [2/2]

#define SRC_AUTHEN_USBPHY1_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_USBPHY1_LOCK_SETTING [1/2]

#define SRC_AUTHEN_USBPHY1_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_USBPHY1_LOCK_SETTING [2/2]

#define SRC_AUTHEN_USBPHY1_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_USBPHY1_NONSECURE [1/2]

#define SRC_AUTHEN_USBPHY1_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY1_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_USBPHY1_NONSECURE [2/2]

#define SRC_AUTHEN_USBPHY1_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY1_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_USBPHY1_SETPOINT_MODE [1/2]

#define SRC_AUTHEN_USBPHY1_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_USBPHY1_SETPOINT_MODE [2/2]

#define SRC_AUTHEN_USBPHY1_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_USBPHY1_USER [1/2]

#define SRC_AUTHEN_USBPHY1_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_USER_SHIFT)) & SRC_AUTHEN_USBPHY1_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_USBPHY1_USER [2/2]

#define SRC_AUTHEN_USBPHY1_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_USER_SHIFT)) & SRC_AUTHEN_USBPHY1_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_USBPHY1_WHITE_LIST [1/2]

#define SRC_AUTHEN_USBPHY1_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_USBPHY1_WHITE_LIST [2/2]

#define SRC_AUTHEN_USBPHY1_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_USBPHY2_DOMAIN_MODE [1/2]

#define SRC_AUTHEN_USBPHY2_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_USBPHY2_DOMAIN_MODE [2/2]

#define SRC_AUTHEN_USBPHY2_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_USBPHY2_LOCK_ASSIGN [1/2]

#define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_USBPHY2_LOCK_ASSIGN [2/2]

#define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_USBPHY2_LOCK_LIST [1/2]

#define SRC_AUTHEN_USBPHY2_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_USBPHY2_LOCK_LIST [2/2]

#define SRC_AUTHEN_USBPHY2_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_USBPHY2_LOCK_MODE [1/2]

#define SRC_AUTHEN_USBPHY2_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_USBPHY2_LOCK_MODE [2/2]

#define SRC_AUTHEN_USBPHY2_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_USBPHY2_LOCK_SETTING [1/2]

#define SRC_AUTHEN_USBPHY2_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_USBPHY2_LOCK_SETTING [2/2]

#define SRC_AUTHEN_USBPHY2_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_USBPHY2_NONSECURE [1/2]

#define SRC_AUTHEN_USBPHY2_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY2_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_USBPHY2_NONSECURE [2/2]

#define SRC_AUTHEN_USBPHY2_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY2_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_USBPHY2_SETPOINT_MODE [1/2]

#define SRC_AUTHEN_USBPHY2_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_USBPHY2_SETPOINT_MODE [2/2]

#define SRC_AUTHEN_USBPHY2_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_USBPHY2_USER [1/2]

#define SRC_AUTHEN_USBPHY2_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_USER_SHIFT)) & SRC_AUTHEN_USBPHY2_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_USBPHY2_USER [2/2]

#define SRC_AUTHEN_USBPHY2_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_USER_SHIFT)) & SRC_AUTHEN_USBPHY2_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_USBPHY2_WHITE_LIST [1/2]

#define SRC_AUTHEN_USBPHY2_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_USBPHY2_WHITE_LIST [2/2]

#define SRC_AUTHEN_USBPHY2_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_WAKEUP_DOMAIN_MODE [1/2]

#define SRC_AUTHEN_WAKEUP_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_WAKEUP_DOMAIN_MODE [2/2]

#define SRC_AUTHEN_WAKEUP_DOMAIN_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK)

DOMAIN_MODE 0b0..slice hardware reset will NOT be triggered by CPU power mode transition 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.

◆ SRC_AUTHEN_WAKEUP_LOCK_ASSIGN [1/2]

#define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_WAKEUP_LOCK_ASSIGN [2/2]

#define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK)

LOCK_ASSIGN - Assign list lock

◆ SRC_AUTHEN_WAKEUP_LOCK_LIST [1/2]

#define SRC_AUTHEN_WAKEUP_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_WAKEUP_LOCK_LIST [2/2]

#define SRC_AUTHEN_WAKEUP_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ SRC_AUTHEN_WAKEUP_LOCK_MODE [1/2]

#define SRC_AUTHEN_WAKEUP_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_WAKEUP_LOCK_MODE [2/2]

#define SRC_AUTHEN_WAKEUP_LOCK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK)

LOCK_MODE - Domain/Setpoint mode lock

◆ SRC_AUTHEN_WAKEUP_LOCK_SETTING [1/2]

#define SRC_AUTHEN_WAKEUP_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_WAKEUP_LOCK_SETTING [2/2]

#define SRC_AUTHEN_WAKEUP_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ SRC_AUTHEN_WAKEUP_NONSECURE [1/2]

#define SRC_AUTHEN_WAKEUP_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT)) & SRC_AUTHEN_WAKEUP_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_WAKEUP_NONSECURE [2/2]

#define SRC_AUTHEN_WAKEUP_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT)) & SRC_AUTHEN_WAKEUP_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ SRC_AUTHEN_WAKEUP_SETPOINT_MODE [1/2]

#define SRC_AUTHEN_WAKEUP_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_WAKEUP_SETPOINT_MODE [2/2]

#define SRC_AUTHEN_WAKEUP_SETPOINT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK)

SETPOINT_MODE 0b0..slice hardware reset will NOT be triggered by Setpoint transition 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.

◆ SRC_AUTHEN_WAKEUP_USER [1/2]

#define SRC_AUTHEN_WAKEUP_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_USER_SHIFT)) & SRC_AUTHEN_WAKEUP_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_WAKEUP_USER [2/2]

#define SRC_AUTHEN_WAKEUP_USER ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_USER_SHIFT)) & SRC_AUTHEN_WAKEUP_USER_MASK)

USER - Allow user mode access

◆ SRC_AUTHEN_WAKEUP_WHITE_LIST [1/2]

#define SRC_AUTHEN_WAKEUP_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_AUTHEN_WAKEUP_WHITE_LIST [2/2]

#define SRC_AUTHEN_WAKEUP_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ SRC_CTRL_DISPLAY_SW_RESET [1/2]

#define SRC_CTRL_DISPLAY_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_DISPLAY_SW_RESET_SHIFT)) & SRC_CTRL_DISPLAY_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_DISPLAY_SW_RESET [2/2]

#define SRC_CTRL_DISPLAY_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_DISPLAY_SW_RESET_SHIFT)) & SRC_CTRL_DISPLAY_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_M4CORE_SW_RESET [1/2]

#define SRC_CTRL_M4CORE_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4CORE_SW_RESET_SHIFT)) & SRC_CTRL_M4CORE_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_M4CORE_SW_RESET [2/2]

#define SRC_CTRL_M4CORE_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4CORE_SW_RESET_SHIFT)) & SRC_CTRL_M4CORE_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_M4DEBUG_SW_RESET [1/2]

#define SRC_CTRL_M4DEBUG_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M4DEBUG_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_M4DEBUG_SW_RESET [2/2]

#define SRC_CTRL_M4DEBUG_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M4DEBUG_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_M7CORE_SW_RESET [1/2]

#define SRC_CTRL_M7CORE_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7CORE_SW_RESET_SHIFT)) & SRC_CTRL_M7CORE_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_M7CORE_SW_RESET [2/2]

#define SRC_CTRL_M7CORE_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7CORE_SW_RESET_SHIFT)) & SRC_CTRL_M7CORE_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_M7DEBUG_SW_RESET [1/2]

#define SRC_CTRL_M7DEBUG_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M7DEBUG_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_M7DEBUG_SW_RESET [2/2]

#define SRC_CTRL_M7DEBUG_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M7DEBUG_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_MEGA_SW_RESET [1/2]

#define SRC_CTRL_MEGA_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_MEGA_SW_RESET_SHIFT)) & SRC_CTRL_MEGA_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_MEGA_SW_RESET [2/2]

#define SRC_CTRL_MEGA_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_MEGA_SW_RESET_SHIFT)) & SRC_CTRL_MEGA_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_USBPHY1_SW_RESET [1/2]

#define SRC_CTRL_USBPHY1_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY1_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY1_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_USBPHY1_SW_RESET [2/2]

#define SRC_CTRL_USBPHY1_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY1_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY1_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_USBPHY2_SW_RESET [1/2]

#define SRC_CTRL_USBPHY2_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY2_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY2_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_USBPHY2_SW_RESET [2/2]

#define SRC_CTRL_USBPHY2_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY2_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY2_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_WAKEUP_SW_RESET [1/2]

#define SRC_CTRL_WAKEUP_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_WAKEUP_SW_RESET_SHIFT)) & SRC_CTRL_WAKEUP_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_CTRL_WAKEUP_SW_RESET [2/2]

#define SRC_CTRL_WAKEUP_SW_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_WAKEUP_SW_RESET_SHIFT)) & SRC_CTRL_WAKEUP_SW_RESET_MASK)

SW_RESET 0b0..do not assert slice software reset 0b1..assert slice software reset

◆ SRC_DOMAIN_DISPLAY_CPU0_RUN [1/2]

#define SRC_DOMAIN_DISPLAY_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_DISPLAY_CPU0_RUN [2/2]

#define SRC_DOMAIN_DISPLAY_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_DISPLAY_CPU0_STOP [1/2]

#define SRC_DOMAIN_DISPLAY_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_DISPLAY_CPU0_STOP [2/2]

#define SRC_DOMAIN_DISPLAY_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_DISPLAY_CPU0_SUSP [1/2]

#define SRC_DOMAIN_DISPLAY_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_DISPLAY_CPU0_SUSP [2/2]

#define SRC_DOMAIN_DISPLAY_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_DISPLAY_CPU0_WAIT [1/2]

#define SRC_DOMAIN_DISPLAY_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_DISPLAY_CPU0_WAIT [2/2]

#define SRC_DOMAIN_DISPLAY_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_DISPLAY_CPU1_RUN [1/2]

#define SRC_DOMAIN_DISPLAY_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_DISPLAY_CPU1_RUN [2/2]

#define SRC_DOMAIN_DISPLAY_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_DISPLAY_CPU1_STOP [1/2]

#define SRC_DOMAIN_DISPLAY_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_DISPLAY_CPU1_STOP [2/2]

#define SRC_DOMAIN_DISPLAY_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_DISPLAY_CPU1_SUSP [1/2]

#define SRC_DOMAIN_DISPLAY_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_DISPLAY_CPU1_SUSP [2/2]

#define SRC_DOMAIN_DISPLAY_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_DISPLAY_CPU1_WAIT [1/2]

#define SRC_DOMAIN_DISPLAY_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_DISPLAY_CPU1_WAIT [2/2]

#define SRC_DOMAIN_DISPLAY_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_M4CORE_CPU0_RUN [1/2]

#define SRC_DOMAIN_M4CORE_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_M4CORE_CPU0_RUN [2/2]

#define SRC_DOMAIN_M4CORE_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_M4CORE_CPU0_STOP [1/2]

#define SRC_DOMAIN_M4CORE_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_M4CORE_CPU0_STOP [2/2]

#define SRC_DOMAIN_M4CORE_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_M4CORE_CPU0_SUSP [1/2]

#define SRC_DOMAIN_M4CORE_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_M4CORE_CPU0_SUSP [2/2]

#define SRC_DOMAIN_M4CORE_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_M4CORE_CPU0_WAIT [1/2]

#define SRC_DOMAIN_M4CORE_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_M4CORE_CPU0_WAIT [2/2]

#define SRC_DOMAIN_M4CORE_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_M4CORE_CPU1_RUN [1/2]

#define SRC_DOMAIN_M4CORE_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_M4CORE_CPU1_RUN [2/2]

#define SRC_DOMAIN_M4CORE_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_M4CORE_CPU1_STOP [1/2]

#define SRC_DOMAIN_M4CORE_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_M4CORE_CPU1_STOP [2/2]

#define SRC_DOMAIN_M4CORE_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_M4CORE_CPU1_SUSP [1/2]

#define SRC_DOMAIN_M4CORE_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_M4CORE_CPU1_SUSP [2/2]

#define SRC_DOMAIN_M4CORE_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_M4CORE_CPU1_WAIT [1/2]

#define SRC_DOMAIN_M4CORE_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_M4CORE_CPU1_WAIT [2/2]

#define SRC_DOMAIN_M4CORE_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_M4DEBUG_CPU0_RUN [1/2]

#define SRC_DOMAIN_M4DEBUG_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_M4DEBUG_CPU0_RUN [2/2]

#define SRC_DOMAIN_M4DEBUG_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_M4DEBUG_CPU0_STOP [1/2]

#define SRC_DOMAIN_M4DEBUG_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_M4DEBUG_CPU0_STOP [2/2]

#define SRC_DOMAIN_M4DEBUG_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_M4DEBUG_CPU0_SUSP [1/2]

#define SRC_DOMAIN_M4DEBUG_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_M4DEBUG_CPU0_SUSP [2/2]

#define SRC_DOMAIN_M4DEBUG_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_M4DEBUG_CPU0_WAIT [1/2]

#define SRC_DOMAIN_M4DEBUG_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_M4DEBUG_CPU0_WAIT [2/2]

#define SRC_DOMAIN_M4DEBUG_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_M4DEBUG_CPU1_RUN [1/2]

#define SRC_DOMAIN_M4DEBUG_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_M4DEBUG_CPU1_RUN [2/2]

#define SRC_DOMAIN_M4DEBUG_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_M4DEBUG_CPU1_STOP [1/2]

#define SRC_DOMAIN_M4DEBUG_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_M4DEBUG_CPU1_STOP [2/2]

#define SRC_DOMAIN_M4DEBUG_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_M4DEBUG_CPU1_SUSP [1/2]

#define SRC_DOMAIN_M4DEBUG_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_M4DEBUG_CPU1_SUSP [2/2]

#define SRC_DOMAIN_M4DEBUG_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_M4DEBUG_CPU1_WAIT [1/2]

#define SRC_DOMAIN_M4DEBUG_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_M4DEBUG_CPU1_WAIT [2/2]

#define SRC_DOMAIN_M4DEBUG_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_M7CORE_CPU0_RUN [1/2]

#define SRC_DOMAIN_M7CORE_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_M7CORE_CPU0_RUN [2/2]

#define SRC_DOMAIN_M7CORE_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_M7CORE_CPU0_STOP [1/2]

#define SRC_DOMAIN_M7CORE_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_M7CORE_CPU0_STOP [2/2]

#define SRC_DOMAIN_M7CORE_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_M7CORE_CPU0_SUSP [1/2]

#define SRC_DOMAIN_M7CORE_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_M7CORE_CPU0_SUSP [2/2]

#define SRC_DOMAIN_M7CORE_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_M7CORE_CPU0_WAIT [1/2]

#define SRC_DOMAIN_M7CORE_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_M7CORE_CPU0_WAIT [2/2]

#define SRC_DOMAIN_M7CORE_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_M7CORE_CPU1_RUN [1/2]

#define SRC_DOMAIN_M7CORE_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_M7CORE_CPU1_RUN [2/2]

#define SRC_DOMAIN_M7CORE_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_M7CORE_CPU1_STOP [1/2]

#define SRC_DOMAIN_M7CORE_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_M7CORE_CPU1_STOP [2/2]

#define SRC_DOMAIN_M7CORE_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_M7CORE_CPU1_SUSP [1/2]

#define SRC_DOMAIN_M7CORE_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_M7CORE_CPU1_SUSP [2/2]

#define SRC_DOMAIN_M7CORE_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_M7CORE_CPU1_WAIT [1/2]

#define SRC_DOMAIN_M7CORE_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_M7CORE_CPU1_WAIT [2/2]

#define SRC_DOMAIN_M7CORE_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_M7DEBUG_CPU0_RUN [1/2]

#define SRC_DOMAIN_M7DEBUG_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_M7DEBUG_CPU0_RUN [2/2]

#define SRC_DOMAIN_M7DEBUG_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_M7DEBUG_CPU0_STOP [1/2]

#define SRC_DOMAIN_M7DEBUG_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_M7DEBUG_CPU0_STOP [2/2]

#define SRC_DOMAIN_M7DEBUG_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_M7DEBUG_CPU0_SUSP [1/2]

#define SRC_DOMAIN_M7DEBUG_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_M7DEBUG_CPU0_SUSP [2/2]

#define SRC_DOMAIN_M7DEBUG_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_M7DEBUG_CPU0_WAIT [1/2]

#define SRC_DOMAIN_M7DEBUG_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_M7DEBUG_CPU0_WAIT [2/2]

#define SRC_DOMAIN_M7DEBUG_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_M7DEBUG_CPU1_RUN [1/2]

#define SRC_DOMAIN_M7DEBUG_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_M7DEBUG_CPU1_RUN [2/2]

#define SRC_DOMAIN_M7DEBUG_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_M7DEBUG_CPU1_STOP [1/2]

#define SRC_DOMAIN_M7DEBUG_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_M7DEBUG_CPU1_STOP [2/2]

#define SRC_DOMAIN_M7DEBUG_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_M7DEBUG_CPU1_SUSP [1/2]

#define SRC_DOMAIN_M7DEBUG_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_M7DEBUG_CPU1_SUSP [2/2]

#define SRC_DOMAIN_M7DEBUG_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_M7DEBUG_CPU1_WAIT [1/2]

#define SRC_DOMAIN_M7DEBUG_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_M7DEBUG_CPU1_WAIT [2/2]

#define SRC_DOMAIN_M7DEBUG_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_MEGA_CPU0_RUN [1/2]

#define SRC_DOMAIN_MEGA_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_MEGA_CPU0_RUN [2/2]

#define SRC_DOMAIN_MEGA_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_MEGA_CPU0_STOP [1/2]

#define SRC_DOMAIN_MEGA_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_MEGA_CPU0_STOP [2/2]

#define SRC_DOMAIN_MEGA_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_MEGA_CPU0_SUSP [1/2]

#define SRC_DOMAIN_MEGA_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_MEGA_CPU0_SUSP [2/2]

#define SRC_DOMAIN_MEGA_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_MEGA_CPU0_WAIT [1/2]

#define SRC_DOMAIN_MEGA_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_MEGA_CPU0_WAIT [2/2]

#define SRC_DOMAIN_MEGA_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_MEGA_CPU1_RUN [1/2]

#define SRC_DOMAIN_MEGA_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_MEGA_CPU1_RUN [2/2]

#define SRC_DOMAIN_MEGA_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_MEGA_CPU1_STOP [1/2]

#define SRC_DOMAIN_MEGA_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_MEGA_CPU1_STOP [2/2]

#define SRC_DOMAIN_MEGA_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_MEGA_CPU1_SUSP [1/2]

#define SRC_DOMAIN_MEGA_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_MEGA_CPU1_SUSP [2/2]

#define SRC_DOMAIN_MEGA_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_MEGA_CPU1_WAIT [1/2]

#define SRC_DOMAIN_MEGA_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_MEGA_CPU1_WAIT [2/2]

#define SRC_DOMAIN_MEGA_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_USBPHY1_CPU0_RUN [1/2]

#define SRC_DOMAIN_USBPHY1_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_USBPHY1_CPU0_RUN [2/2]

#define SRC_DOMAIN_USBPHY1_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_USBPHY1_CPU0_STOP [1/2]

#define SRC_DOMAIN_USBPHY1_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_USBPHY1_CPU0_STOP [2/2]

#define SRC_DOMAIN_USBPHY1_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_USBPHY1_CPU0_SUSP [1/2]

#define SRC_DOMAIN_USBPHY1_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_USBPHY1_CPU0_SUSP [2/2]

#define SRC_DOMAIN_USBPHY1_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_USBPHY1_CPU0_WAIT [1/2]

#define SRC_DOMAIN_USBPHY1_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_USBPHY1_CPU0_WAIT [2/2]

#define SRC_DOMAIN_USBPHY1_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_USBPHY1_CPU1_RUN [1/2]

#define SRC_DOMAIN_USBPHY1_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_USBPHY1_CPU1_RUN [2/2]

#define SRC_DOMAIN_USBPHY1_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_USBPHY1_CPU1_STOP [1/2]

#define SRC_DOMAIN_USBPHY1_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_USBPHY1_CPU1_STOP [2/2]

#define SRC_DOMAIN_USBPHY1_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_USBPHY1_CPU1_SUSP [1/2]

#define SRC_DOMAIN_USBPHY1_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_USBPHY1_CPU1_SUSP [2/2]

#define SRC_DOMAIN_USBPHY1_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_USBPHY1_CPU1_WAIT [1/2]

#define SRC_DOMAIN_USBPHY1_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_USBPHY1_CPU1_WAIT [2/2]

#define SRC_DOMAIN_USBPHY1_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_USBPHY2_CPU0_RUN [1/2]

#define SRC_DOMAIN_USBPHY2_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_USBPHY2_CPU0_RUN [2/2]

#define SRC_DOMAIN_USBPHY2_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_USBPHY2_CPU0_STOP [1/2]

#define SRC_DOMAIN_USBPHY2_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_USBPHY2_CPU0_STOP [2/2]

#define SRC_DOMAIN_USBPHY2_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_USBPHY2_CPU0_SUSP [1/2]

#define SRC_DOMAIN_USBPHY2_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_USBPHY2_CPU0_SUSP [2/2]

#define SRC_DOMAIN_USBPHY2_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_USBPHY2_CPU0_WAIT [1/2]

#define SRC_DOMAIN_USBPHY2_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_USBPHY2_CPU0_WAIT [2/2]

#define SRC_DOMAIN_USBPHY2_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_USBPHY2_CPU1_RUN [1/2]

#define SRC_DOMAIN_USBPHY2_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_USBPHY2_CPU1_RUN [2/2]

#define SRC_DOMAIN_USBPHY2_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_USBPHY2_CPU1_STOP [1/2]

#define SRC_DOMAIN_USBPHY2_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_USBPHY2_CPU1_STOP [2/2]

#define SRC_DOMAIN_USBPHY2_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_USBPHY2_CPU1_SUSP [1/2]

#define SRC_DOMAIN_USBPHY2_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_USBPHY2_CPU1_SUSP [2/2]

#define SRC_DOMAIN_USBPHY2_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_USBPHY2_CPU1_WAIT [1/2]

#define SRC_DOMAIN_USBPHY2_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_USBPHY2_CPU1_WAIT [2/2]

#define SRC_DOMAIN_USBPHY2_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_WAKEUP_CPU0_RUN [1/2]

#define SRC_DOMAIN_WAKEUP_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_WAKEUP_CPU0_RUN [2/2]

#define SRC_DOMAIN_WAKEUP_CPU0_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK)

CPU0_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU0 in RUN mode 0b1..Slice reset will be asserted when CPU0 in RUN mode

◆ SRC_DOMAIN_WAKEUP_CPU0_STOP [1/2]

#define SRC_DOMAIN_WAKEUP_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_WAKEUP_CPU0_STOP [2/2]

#define SRC_DOMAIN_WAKEUP_CPU0_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK)

CPU0_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU0 in STOP mode 0b1..Slice reset will be asserted when CPU0 in STOP mode

◆ SRC_DOMAIN_WAKEUP_CPU0_SUSP [1/2]

#define SRC_DOMAIN_WAKEUP_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_WAKEUP_CPU0_SUSP [2/2]

#define SRC_DOMAIN_WAKEUP_CPU0_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK)

CPU0_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode

◆ SRC_DOMAIN_WAKEUP_CPU0_WAIT [1/2]

#define SRC_DOMAIN_WAKEUP_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_WAKEUP_CPU0_WAIT [2/2]

#define SRC_DOMAIN_WAKEUP_CPU0_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK)

CPU0_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode 0b1..Slice reset will be asserted when CPU0 in WAIT mode

◆ SRC_DOMAIN_WAKEUP_CPU1_RUN [1/2]

#define SRC_DOMAIN_WAKEUP_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_WAKEUP_CPU1_RUN [2/2]

#define SRC_DOMAIN_WAKEUP_CPU1_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK)

CPU1_RUN - CPU mode setting for RUN 0b0..Slice reset will be de-asserted when CPU1 in RUN mode 0b1..Slice reset will be asserted when CPU1 in RUN mode

◆ SRC_DOMAIN_WAKEUP_CPU1_STOP [1/2]

#define SRC_DOMAIN_WAKEUP_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_WAKEUP_CPU1_STOP [2/2]

#define SRC_DOMAIN_WAKEUP_CPU1_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK)

CPU1_STOP - CPU mode setting for STOP 0b0..Slice reset will be de-asserted when CPU1 in STOP mode 0b1..Slice reset will be asserted when CPU1 in STOP mode

◆ SRC_DOMAIN_WAKEUP_CPU1_SUSP [1/2]

#define SRC_DOMAIN_WAKEUP_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_WAKEUP_CPU1_SUSP [2/2]

#define SRC_DOMAIN_WAKEUP_CPU1_SUSP ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK)

CPU1_SUSP - CPU mode setting for SUSPEND 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode

◆ SRC_DOMAIN_WAKEUP_CPU1_WAIT [1/2]

#define SRC_DOMAIN_WAKEUP_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_DOMAIN_WAKEUP_CPU1_WAIT [2/2]

#define SRC_DOMAIN_WAKEUP_CPU1_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK)

CPU1_WAIT - CPU mode setting for WAIT 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode 0b1..Slice reset will be asserted when CPU1 in WAIT mode

◆ SRC_GPR_GPR [1/2]

#define SRC_GPR_GPR ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_GPR_SHIFT)) & SRC_GPR_GPR_MASK)

GPR - General Purpose Register.

◆ SRC_GPR_GPR [2/2]

#define SRC_GPR_GPR ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_GPR_SHIFT)) & SRC_GPR_GPR_MASK)

GPR - General Purpose Register.

◆ SRC_SCR_BT_RELEASE_M4 [1/2]

#define SRC_SCR_BT_RELEASE_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M4_SHIFT)) & SRC_SCR_BT_RELEASE_M4_MASK)

BT_RELEASE_M4 0b0..cm4 core reset is asserted 0b1..cm4 core reset is released

◆ SRC_SCR_BT_RELEASE_M4 [2/2]

#define SRC_SCR_BT_RELEASE_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M4_SHIFT)) & SRC_SCR_BT_RELEASE_M4_MASK)

BT_RELEASE_M4 0b0..cm4 core reset is asserted 0b1..cm4 core reset is released

◆ SRC_SCR_BT_RELEASE_M7 [1/2]

#define SRC_SCR_BT_RELEASE_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M7_SHIFT)) & SRC_SCR_BT_RELEASE_M7_MASK)

BT_RELEASE_M7 0b0..cm7 core reset is asserted 0b1..cm7 core reset is released

◆ SRC_SCR_BT_RELEASE_M7 [2/2]

#define SRC_SCR_BT_RELEASE_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M7_SHIFT)) & SRC_SCR_BT_RELEASE_M7_MASK)

BT_RELEASE_M7 0b0..cm7 core reset is asserted 0b1..cm7 core reset is released

◆ SRC_SCR_CORE0_DBG_RST

#define SRC_SCR_CORE0_DBG_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)

core0_dbg_rst 0b0..do not assert core0 debug reset 0b1..assert core0 debug reset

◆ SRC_SCR_CORE0_RST

#define SRC_SCR_CORE0_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)

core0_rst 0b0..do not assert core0 reset 0b1..assert core0 reset

◆ SRC_SCR_DBG_RST_MSK_PG

#define SRC_SCR_DBG_RST_MSK_PG ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)

dbg_rst_msk_pg 0b0..do not mask core debug resets (debug resets will be asserted after power gating event) 0b1..mask core debug resets (debug resets won't be asserted after power gating event)

◆ SRC_SCR_MASK_WDOG3_RST

#define SRC_SCR_MASK_WDOG3_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)

mask_wdog3_rst 0b0101..wdog3_rst_b is masked 0b1010..wdog3_rst_b is not masked

◆ SRC_SCR_MASK_WDOG_RST

#define SRC_SCR_MASK_WDOG_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)

mask_wdog_rst 0b0101..wdog_rst_b is masked 0b1010..wdog_rst_b is not masked (default)

◆ SRC_SETPOINT_DISPLAY_SETPOINT0 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT0 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT1 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT1 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT10 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT10 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT11 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT11 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT12 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT12 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT13 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT13 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT14 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT14 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT15 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT15 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT2 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT2 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT3 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT3 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT4 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT4 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT5 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT5 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT6 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT6 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT7 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT7 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT8 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT8 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT9 [1/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_DISPLAY_SETPOINT9 [2/2]

#define SRC_SETPOINT_DISPLAY_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT0 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT0 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT1 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT1 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT10 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT10 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT11 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT11 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT12 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT12 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT13 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT13 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT14 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT14 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT15 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT15 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT2 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT2 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT3 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT3 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT4 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT4 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT5 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT5 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT6 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT6 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT7 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT7 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT8 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT8 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT9 [1/2]

#define SRC_SETPOINT_M4CORE_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4CORE_SETPOINT9 [2/2]

#define SRC_SETPOINT_M4CORE_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT0 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT0 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT1 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT1 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT10 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT10 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT11 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT11 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT12 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT12 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT13 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT13 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT14 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT14 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT15 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT15 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT2 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT2 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT3 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT3 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT4 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT4 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT5 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT5 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT6 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT6 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT7 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT7 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT8 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT8 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT9 [1/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M4DEBUG_SETPOINT9 [2/2]

#define SRC_SETPOINT_M4DEBUG_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT0 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT0 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT1 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT1 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT10 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT10 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT11 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT11 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT12 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT12 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT13 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT13 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT14 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT14 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT15 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT15 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT2 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT2 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT3 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT3 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT4 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT4 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT5 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT5 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT6 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT6 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT7 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT7 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT8 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT8 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT9 [1/2]

#define SRC_SETPOINT_M7CORE_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7CORE_SETPOINT9 [2/2]

#define SRC_SETPOINT_M7CORE_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT0 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT0 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT1 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT1 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT10 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT10 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT11 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT11 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT12 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT12 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT13 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT13 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT14 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT14 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT15 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT15 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT2 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT2 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT3 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT3 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT4 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT4 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT5 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT5 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT6 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT6 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT7 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT7 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT8 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT8 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT9 [1/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_M7DEBUG_SETPOINT9 [2/2]

#define SRC_SETPOINT_M7DEBUG_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT0 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT0_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT0 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT0_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT1 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT1_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT1 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT1_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT10 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT10_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT10 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT10_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT11 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT11_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT11 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT11_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT12 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT12_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT12 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT12_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT13 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT13_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT13 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT13_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT14 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT14_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT14 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT14_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT15 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT15_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT15 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT15_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT2 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT2_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT2 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT2_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT3 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT3_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT3 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT3_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT4 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT4_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT4 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT4_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT5 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT5_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT5 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT5_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT6 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT6_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT6 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT6_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT7 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT7_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT7 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT7_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT8 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT8_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT8 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT8_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT9 [1/2]

#define SRC_SETPOINT_MEGA_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT9_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_MEGA_SETPOINT9 [2/2]

#define SRC_SETPOINT_MEGA_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT9_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT0 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT0 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT1 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT1 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT10 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT10 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT11 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT11 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT12 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT12 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT13 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT13 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT14 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT14 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT15 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT15 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT2 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT2 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT3 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT3 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT4 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT4 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT5 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT5 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT6 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT6 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT7 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT7 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT8 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT8 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT9 [1/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY1_SETPOINT9 [2/2]

#define SRC_SETPOINT_USBPHY1_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT0 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT0 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT1 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT1 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT10 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT10 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT11 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT11 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT12 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT12 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT13 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT13 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT14 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT14 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT15 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT15 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT2 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT2 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT3 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT3 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT4 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT4 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT5 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT5 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT6 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT6 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT7 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT7 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT8 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT8 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT9 [1/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_USBPHY2_SETPOINT9 [2/2]

#define SRC_SETPOINT_USBPHY2_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT0 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT0 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT0 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT0_MASK)

SETPOINT0 - SETPOINT0 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT1 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT1 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT1 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT1_MASK)

SETPOINT1 - SETPOINT1 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT10 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT10 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT10 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT10_MASK)

SETPOINT10 - SETPOINT10 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT11 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT11 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT11 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT11_MASK)

SETPOINT11 - SETPOINT11 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT12 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT12 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT12 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT12_MASK)

SETPOINT12 - SETPOINT12 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT13 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT13 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT13 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT13_MASK)

SETPOINT13 - SETPOINT13 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT14 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT14 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT14 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT14_MASK)

SETPOINT14 - SETPOINT14 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT15 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT15 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT15 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT15_MASK)

SETPOINT15 - SETPOINT15 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT2 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT2 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT2 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT2_MASK)

SETPOINT2 - SETPOINT2 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT3 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT3 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT3 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT3_MASK)

SETPOINT3 - SETPOINT3 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT4 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT4 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT4_MASK)

SETPOINT4 - SETPOINT4 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT5 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT5 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT5 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT5_MASK)

SETPOINT5 - SETPOINT5 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT6 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT6 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT6 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT6_MASK)

SETPOINT6 - SETPOINT6 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT7 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT7 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT7_MASK)

SETPOINT7 - SETPOINT7 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT8 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT8 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT8 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT8_MASK)

SETPOINT8 - SETPOINT8 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT9 [1/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SETPOINT_WAKEUP_SETPOINT9 [2/2]

#define SRC_SETPOINT_WAKEUP_SETPOINT9 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT9_MASK)

SETPOINT9 - SETPOINT9 0b0..Slice reset will be de-asserted when system in Setpoint n 0b1..Slice reset will be asserted when system in Setpoint n

◆ SRC_SRMR_CSU_RESET_MODE [1/2]

#define SRC_SRMR_CSU_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_CSU_RESET_MODE_SHIFT)) & SRC_SRMR_CSU_RESET_MODE_MASK)

CSU_RESET_MODE - CSU reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_CSU_RESET_MODE [2/2]

#define SRC_SRMR_CSU_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_CSU_RESET_MODE_SHIFT)) & SRC_SRMR_CSU_RESET_MODE_MASK)

CSU_RESET_MODE - CSU reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_JTAGSW_RESET_MODE [1/2]

#define SRC_SRMR_JTAGSW_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_JTAGSW_RESET_MODE_SHIFT)) & SRC_SRMR_JTAGSW_RESET_MODE_MASK)

JTAGSW_RESET_MODE - Jtag SW reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_JTAGSW_RESET_MODE [2/2]

#define SRC_SRMR_JTAGSW_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_JTAGSW_RESET_MODE_SHIFT)) & SRC_SRMR_JTAGSW_RESET_MODE_MASK)

JTAGSW_RESET_MODE - Jtag SW reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_M4LOCKUP_RESET_MODE [1/2]

#define SRC_SRMR_M4LOCKUP_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M4LOCKUP_RESET_MODE_MASK)

M4LOCKUP_RESET_MODE - M4 core lockup reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_M4LOCKUP_RESET_MODE [2/2]

#define SRC_SRMR_M4LOCKUP_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M4LOCKUP_RESET_MODE_MASK)

M4LOCKUP_RESET_MODE - M4 core lockup reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_M4REQ_RESET_MODE [1/2]

#define SRC_SRMR_M4REQ_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M4REQ_RESET_MODE_MASK)

M4REQ_RESET_MODE - M4 request reset configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_M4REQ_RESET_MODE [2/2]

#define SRC_SRMR_M4REQ_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M4REQ_RESET_MODE_MASK)

M4REQ_RESET_MODE - M4 request reset configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_M7LOCKUP_RESET_MODE [1/2]

#define SRC_SRMR_M7LOCKUP_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M7LOCKUP_RESET_MODE_MASK)

M7LOCKUP_RESET_MODE - M7 core lockup reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_M7LOCKUP_RESET_MODE [2/2]

#define SRC_SRMR_M7LOCKUP_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M7LOCKUP_RESET_MODE_MASK)

M7LOCKUP_RESET_MODE - M7 core lockup reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_M7REQ_RESET_MODE [1/2]

#define SRC_SRMR_M7REQ_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M7REQ_RESET_MODE_MASK)

M7REQ_RESET_MODE - M7 request reset configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_M7REQ_RESET_MODE [2/2]

#define SRC_SRMR_M7REQ_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M7REQ_RESET_MODE_MASK)

M7REQ_RESET_MODE - M7 request reset configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_OVERVOLT_RESET_MODE [1/2]

#define SRC_SRMR_OVERVOLT_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT)) & SRC_SRMR_OVERVOLT_RESET_MODE_MASK)

OVERVOLT_RESET_MODE - Jtag SW reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_OVERVOLT_RESET_MODE [2/2]

#define SRC_SRMR_OVERVOLT_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT)) & SRC_SRMR_OVERVOLT_RESET_MODE_MASK)

OVERVOLT_RESET_MODE - Jtag SW reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_TEMPSENSE_RESET_MODE [1/2]

#define SRC_SRMR_TEMPSENSE_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_SRMR_TEMPSENSE_RESET_MODE_MASK)

TEMPSENSE_RESET_MODE - Tempsense reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_TEMPSENSE_RESET_MODE [2/2]

#define SRC_SRMR_TEMPSENSE_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_SRMR_TEMPSENSE_RESET_MODE_MASK)

TEMPSENSE_RESET_MODE - Tempsense reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_WDOG3_RESET_MODE [1/2]

#define SRC_SRMR_WDOG3_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG3_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG3_RESET_MODE_MASK)

WDOG3_RESET_MODE - Wdog3 reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_WDOG3_RESET_MODE [2/2]

#define SRC_SRMR_WDOG3_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG3_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG3_RESET_MODE_MASK)

WDOG3_RESET_MODE - Wdog3 reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_WDOG4_RESET_MODE [1/2]

#define SRC_SRMR_WDOG4_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG4_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG4_RESET_MODE_MASK)

WDOG4_RESET_MODE - Wdog4 reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_WDOG4_RESET_MODE [2/2]

#define SRC_SRMR_WDOG4_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG4_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG4_RESET_MODE_MASK)

WDOG4_RESET_MODE - Wdog4 reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_WDOG_RESET_MODE [1/2]

#define SRC_SRMR_WDOG_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG_RESET_MODE_MASK)

WDOG_RESET_MODE - Wdog reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRMR_WDOG_RESET_MODE [2/2]

#define SRC_SRMR_WDOG_RESET_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG_RESET_MODE_MASK)

WDOG_RESET_MODE - Wdog reset mode configuration 0b00..reset system 0b01..reserved 0b10..reserved 0b11..do not reset anything

◆ SRC_SRSR_CDOG_RST_M4 [1/2]

#define SRC_SRSR_CDOG_RST_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M4_SHIFT)) & SRC_SRSR_CDOG_RST_M4_MASK)

CDOG_RST_M4 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_CDOG_RST_M4 [2/2]

#define SRC_SRSR_CDOG_RST_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M4_SHIFT)) & SRC_SRSR_CDOG_RST_M4_MASK)

CDOG_RST_M4 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_CDOG_RST_M7 [1/2]

#define SRC_SRSR_CDOG_RST_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M7_SHIFT)) & SRC_SRSR_CDOG_RST_M7_MASK)

CDOG_RST_M7 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_CDOG_RST_M7 [2/2]

#define SRC_SRSR_CDOG_RST_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M7_SHIFT)) & SRC_SRSR_CDOG_RST_M7_MASK)

CDOG_RST_M7 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_CSU_RESET_B

#define SRC_SRSR_CSU_RESET_B ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)

csu_reset_b 0b0..Reset is not a result of the csu_reset_b event. 0b1..Reset is a result of the csu_reset_b event.

◆ SRC_SRSR_CSU_RESET_B_M4 [1/2]

#define SRC_SRSR_CSU_RESET_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M4_SHIFT)) & SRC_SRSR_CSU_RESET_B_M4_MASK)

CSU_RESET_B_M4 0b0..Reset is not a result of the csu_reset_b event. 0b1..Reset is a result of the csu_reset_b event.

◆ SRC_SRSR_CSU_RESET_B_M4 [2/2]

#define SRC_SRSR_CSU_RESET_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M4_SHIFT)) & SRC_SRSR_CSU_RESET_B_M4_MASK)

CSU_RESET_B_M4 0b0..Reset is not a result of the csu_reset_b event. 0b1..Reset is a result of the csu_reset_b event.

◆ SRC_SRSR_CSU_RESET_B_M7 [1/2]

#define SRC_SRSR_CSU_RESET_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M7_SHIFT)) & SRC_SRSR_CSU_RESET_B_M7_MASK)

CSU_RESET_B_M7 0b0..Reset is not a result of the csu_reset_b event. 0b1..Reset is a result of the csu_reset_b event.

◆ SRC_SRSR_CSU_RESET_B_M7 [2/2]

#define SRC_SRSR_CSU_RESET_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M7_SHIFT)) & SRC_SRSR_CSU_RESET_B_M7_MASK)

CSU_RESET_B_M7 0b0..Reset is not a result of the csu_reset_b event. 0b1..Reset is a result of the csu_reset_b event.

◆ SRC_SRSR_IPP_RESET_B

#define SRC_SRSR_IPP_RESET_B ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)

ipp_reset_b 0b0..Reset is not a result of ipp_reset_b pin. 0b1..Reset is a result of ipp_reset_b pin.

◆ SRC_SRSR_IPP_RESET_B_M4 [1/2]

#define SRC_SRSR_IPP_RESET_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_RESET_B_M4_MASK)

IPP_RESET_B_M4 0b0..Reset is not a result of ipp_reset_b pin. 0b1..Reset is a result of ipp_reset_b pin.

◆ SRC_SRSR_IPP_RESET_B_M4 [2/2]

#define SRC_SRSR_IPP_RESET_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_RESET_B_M4_MASK)

IPP_RESET_B_M4 0b0..Reset is not a result of ipp_reset_b pin. 0b1..Reset is a result of ipp_reset_b pin.

◆ SRC_SRSR_IPP_RESET_B_M7 [1/2]

#define SRC_SRSR_IPP_RESET_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_RESET_B_M7_MASK)

IPP_RESET_B_M7 0b0..Reset is not a result of ipp_reset_b pin. 0b1..Reset is a result of ipp_reset_b pin.

◆ SRC_SRSR_IPP_RESET_B_M7 [2/2]

#define SRC_SRSR_IPP_RESET_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_RESET_B_M7_MASK)

IPP_RESET_B_M7 0b0..Reset is not a result of ipp_reset_b pin. 0b1..Reset is a result of ipp_reset_b pin.

◆ SRC_SRSR_IPP_USER_RESET_B

#define SRC_SRSR_IPP_USER_RESET_B ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)

ipp_user_reset_b 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.

◆ SRC_SRSR_IPP_USER_RESET_B_M4 [1/2]

#define SRC_SRSR_IPP_USER_RESET_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M4_MASK)

IPP_USER_RESET_B_M4 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.

◆ SRC_SRSR_IPP_USER_RESET_B_M4 [2/2]

#define SRC_SRSR_IPP_USER_RESET_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M4_MASK)

IPP_USER_RESET_B_M4 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.

◆ SRC_SRSR_IPP_USER_RESET_B_M7 [1/2]

#define SRC_SRSR_IPP_USER_RESET_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M7_MASK)

IPP_USER_RESET_B_M7 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.

◆ SRC_SRSR_IPP_USER_RESET_B_M7 [2/2]

#define SRC_SRSR_IPP_USER_RESET_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M7_MASK)

IPP_USER_RESET_B_M7 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.

◆ SRC_SRSR_JTAG_RST_B

#define SRC_SRSR_JTAG_RST_B ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)

jtag_rst_b 0b0..Reset is not a result of HIGH-Z reset from JTAG. 0b1..Reset is a result of HIGH-Z reset from JTAG.

◆ SRC_SRSR_JTAG_RST_B_M4 [1/2]

#define SRC_SRSR_JTAG_RST_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M4_SHIFT)) & SRC_SRSR_JTAG_RST_B_M4_MASK)

JTAG_RST_B_M4 0b0..Reset is not a result of HIGH-Z reset from JTAG. 0b1..Reset is a result of HIGH-Z reset from JTAG.

◆ SRC_SRSR_JTAG_RST_B_M4 [2/2]

#define SRC_SRSR_JTAG_RST_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M4_SHIFT)) & SRC_SRSR_JTAG_RST_B_M4_MASK)

JTAG_RST_B_M4 0b0..Reset is not a result of HIGH-Z reset from JTAG. 0b1..Reset is a result of HIGH-Z reset from JTAG.

◆ SRC_SRSR_JTAG_RST_B_M7 [1/2]

#define SRC_SRSR_JTAG_RST_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M7_SHIFT)) & SRC_SRSR_JTAG_RST_B_M7_MASK)

JTAG_RST_B_M7 0b0..Reset is not a result of HIGH-Z reset from JTAG. 0b1..Reset is a result of HIGH-Z reset from JTAG.

◆ SRC_SRSR_JTAG_RST_B_M7 [2/2]

#define SRC_SRSR_JTAG_RST_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M7_SHIFT)) & SRC_SRSR_JTAG_RST_B_M7_MASK)

JTAG_RST_B_M7 0b0..Reset is not a result of HIGH-Z reset from JTAG. 0b1..Reset is a result of HIGH-Z reset from JTAG.

◆ SRC_SRSR_JTAG_SW_RST

#define SRC_SRSR_JTAG_SW_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)

jtag_sw_rst 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_JTAG_SW_RST_M4 [1/2]

#define SRC_SRSR_JTAG_SW_RST_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M4_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M4_MASK)

JTAG_SW_RST_M4 0b0..Reset is not a result of software reset from JTAG. 0b1..Reset is a result of software reset from JTAG.

◆ SRC_SRSR_JTAG_SW_RST_M4 [2/2]

#define SRC_SRSR_JTAG_SW_RST_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M4_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M4_MASK)

JTAG_SW_RST_M4 0b0..Reset is not a result of software reset from JTAG. 0b1..Reset is a result of software reset from JTAG.

◆ SRC_SRSR_JTAG_SW_RST_M7 [1/2]

#define SRC_SRSR_JTAG_SW_RST_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M7_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M7_MASK)

JTAG_SW_RST_M7 0b0..Reset is not a result of software reset from JTAG. 0b1..Reset is a result of software reset from JTAG.

◆ SRC_SRSR_JTAG_SW_RST_M7 [2/2]

#define SRC_SRSR_JTAG_SW_RST_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M7_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M7_MASK)

JTAG_SW_RST_M7 0b0..Reset is not a result of software reset from JTAG. 0b1..Reset is a result of software reset from JTAG.

◆ SRC_SRSR_LOCKUP_SYSRESETREQ

#define SRC_SRSR_LOCKUP_SYSRESETREQ ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)

lockup_sysresetreq 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_M4_LOCKUP_M4 [1/2]

#define SRC_SRSR_M4_LOCKUP_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M4_SHIFT)) & SRC_SRSR_M4_LOCKUP_M4_MASK)

M4_LOCKUP_M4 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_M4_LOCKUP_M4 [2/2]

#define SRC_SRSR_M4_LOCKUP_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M4_SHIFT)) & SRC_SRSR_M4_LOCKUP_M4_MASK)

M4_LOCKUP_M4 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_M4_LOCKUP_M7 [1/2]

#define SRC_SRSR_M4_LOCKUP_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M7_SHIFT)) & SRC_SRSR_M4_LOCKUP_M7_MASK)

M4_LOCKUP_M7 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_M4_LOCKUP_M7 [2/2]

#define SRC_SRSR_M4_LOCKUP_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M7_SHIFT)) & SRC_SRSR_M4_LOCKUP_M7_MASK)

M4_LOCKUP_M7 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_M4_REQUEST_M4 [1/2]

#define SRC_SRSR_M4_REQUEST_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M4_SHIFT)) & SRC_SRSR_M4_REQUEST_M4_MASK)

M4_REQUEST_M4 0b0..Reset is not a result of m4 reset request. 0b1..Reset is a result of m4 reset request.

◆ SRC_SRSR_M4_REQUEST_M4 [2/2]

#define SRC_SRSR_M4_REQUEST_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M4_SHIFT)) & SRC_SRSR_M4_REQUEST_M4_MASK)

M4_REQUEST_M4 0b0..Reset is not a result of m4 reset request. 0b1..Reset is a result of m4 reset request.

◆ SRC_SRSR_M4_REQUEST_M7 [1/2]

#define SRC_SRSR_M4_REQUEST_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M7_SHIFT)) & SRC_SRSR_M4_REQUEST_M7_MASK)

M4_REQUEST_M7 0b0..Reset is not a result of m4 reset request. 0b1..Reset is a result of m4 reset request.

◆ SRC_SRSR_M4_REQUEST_M7 [2/2]

#define SRC_SRSR_M4_REQUEST_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M7_SHIFT)) & SRC_SRSR_M4_REQUEST_M7_MASK)

M4_REQUEST_M7 0b0..Reset is not a result of m4 reset request. 0b1..Reset is a result of m4 reset request.

◆ SRC_SRSR_M7_LOCKUP_M4 [1/2]

#define SRC_SRSR_M7_LOCKUP_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M4_SHIFT)) & SRC_SRSR_M7_LOCKUP_M4_MASK)

M7_LOCKUP_M4 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_M7_LOCKUP_M4 [2/2]

#define SRC_SRSR_M7_LOCKUP_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M4_SHIFT)) & SRC_SRSR_M7_LOCKUP_M4_MASK)

M7_LOCKUP_M4 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_M7_LOCKUP_M7 [1/2]

#define SRC_SRSR_M7_LOCKUP_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M7_SHIFT)) & SRC_SRSR_M7_LOCKUP_M7_MASK)

M7_LOCKUP_M7 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_M7_LOCKUP_M7 [2/2]

#define SRC_SRSR_M7_LOCKUP_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M7_SHIFT)) & SRC_SRSR_M7_LOCKUP_M7_MASK)

M7_LOCKUP_M7 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_M7_REQUEST_M4 [1/2]

#define SRC_SRSR_M7_REQUEST_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M4_SHIFT)) & SRC_SRSR_M7_REQUEST_M4_MASK)

M7_REQUEST_M4 0b0..Reset is not a result of m7 reset request. 0b1..Reset is a result of m7 reset request.

◆ SRC_SRSR_M7_REQUEST_M4 [2/2]

#define SRC_SRSR_M7_REQUEST_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M4_SHIFT)) & SRC_SRSR_M7_REQUEST_M4_MASK)

M7_REQUEST_M4 0b0..Reset is not a result of m7 reset request. 0b1..Reset is a result of m7 reset request.

◆ SRC_SRSR_M7_REQUEST_M7 [1/2]

#define SRC_SRSR_M7_REQUEST_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M7_SHIFT)) & SRC_SRSR_M7_REQUEST_M7_MASK)

M7_REQUEST_M7 0b0..Reset is not a result of m7 reset request. 0b1..Reset is a result of m7 reset request.

◆ SRC_SRSR_M7_REQUEST_M7 [2/2]

#define SRC_SRSR_M7_REQUEST_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M7_SHIFT)) & SRC_SRSR_M7_REQUEST_M7_MASK)

M7_REQUEST_M7 0b0..Reset is not a result of m7 reset request. 0b1..Reset is a result of m7 reset request.

◆ SRC_SRSR_OVERVOLT_RST_M4 [1/2]

#define SRC_SRSR_OVERVOLT_RST_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M4_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M4_MASK)

OVERVOLT_RST_M4 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_OVERVOLT_RST_M4 [2/2]

#define SRC_SRSR_OVERVOLT_RST_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M4_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M4_MASK)

OVERVOLT_RST_M4 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_OVERVOLT_RST_M7 [1/2]

#define SRC_SRSR_OVERVOLT_RST_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M7_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M7_MASK)

OVERVOLT_RST_M7 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_OVERVOLT_RST_M7 [2/2]

#define SRC_SRSR_OVERVOLT_RST_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M7_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M7_MASK)

OVERVOLT_RST_M7 0b0..Reset is not a result of the mentioned case. 0b1..Reset is a result of the mentioned case.

◆ SRC_SRSR_TEMPSENSE_RST_B

#define SRC_SRSR_TEMPSENSE_RST_B ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)

tempsense_rst_b 0b0..Reset is not a result of software reset from Temperature Sensor. 0b1..Reset is a result of software reset from Temperature Sensor.

◆ SRC_SRSR_TEMPSENSE_RST_B_M4 [1/2]

#define SRC_SRSR_TEMPSENSE_RST_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M4_MASK)

TEMPSENSE_RST_B_M4 0b0..Reset is not a result of software reset from Temperature Sensor. 0b1..Reset is a result of software reset from Temperature Sensor.

◆ SRC_SRSR_TEMPSENSE_RST_B_M4 [2/2]

#define SRC_SRSR_TEMPSENSE_RST_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M4_MASK)

TEMPSENSE_RST_B_M4 0b0..Reset is not a result of software reset from Temperature Sensor. 0b1..Reset is a result of software reset from Temperature Sensor.

◆ SRC_SRSR_TEMPSENSE_RST_B_M7 [1/2]

#define SRC_SRSR_TEMPSENSE_RST_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M7_MASK)

TEMPSENSE_RST_B_M7 0b0..Reset is not a result of software reset from Temperature Sensor. 0b1..Reset is a result of software reset from Temperature Sensor.

◆ SRC_SRSR_TEMPSENSE_RST_B_M7 [2/2]

#define SRC_SRSR_TEMPSENSE_RST_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M7_MASK)

TEMPSENSE_RST_B_M7 0b0..Reset is not a result of software reset from Temperature Sensor. 0b1..Reset is a result of software reset from Temperature Sensor.

◆ SRC_SRSR_WDOG3_RST_B

#define SRC_SRSR_WDOG3_RST_B ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)

wdog3_rst_b 0b0..Reset is not a result of the watchdog3 time-out event. 0b1..Reset is a result of the watchdog3 time-out event.

◆ SRC_SRSR_WDOG3_RST_B_M4 [1/2]

#define SRC_SRSR_WDOG3_RST_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M4_MASK)

WDOG3_RST_B_M4 0b0..Reset is not a result of the watchdog3 time-out event. 0b1..Reset is a result of the watchdog3 time-out event.

◆ SRC_SRSR_WDOG3_RST_B_M4 [2/2]

#define SRC_SRSR_WDOG3_RST_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M4_MASK)

WDOG3_RST_B_M4 0b0..Reset is not a result of the watchdog3 time-out event. 0b1..Reset is a result of the watchdog3 time-out event.

◆ SRC_SRSR_WDOG3_RST_B_M7 [1/2]

#define SRC_SRSR_WDOG3_RST_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M7_MASK)

WDOG3_RST_B_M7 0b0..Reset is not a result of the watchdog3 time-out event. 0b1..Reset is a result of the watchdog3 time-out event.

◆ SRC_SRSR_WDOG3_RST_B_M7 [2/2]

#define SRC_SRSR_WDOG3_RST_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M7_MASK)

WDOG3_RST_B_M7 0b0..Reset is not a result of the watchdog3 time-out event. 0b1..Reset is a result of the watchdog3 time-out event.

◆ SRC_SRSR_WDOG4_RST_B_M4 [1/2]

#define SRC_SRSR_WDOG4_RST_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M4_MASK)

WDOG4_RST_B_M4 0b0..Reset is not a result of the watchdog4 time-out event. 0b1..Reset is a result of the watchdog4 time-out event.

◆ SRC_SRSR_WDOG4_RST_B_M4 [2/2]

#define SRC_SRSR_WDOG4_RST_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M4_MASK)

WDOG4_RST_B_M4 0b0..Reset is not a result of the watchdog4 time-out event. 0b1..Reset is a result of the watchdog4 time-out event.

◆ SRC_SRSR_WDOG4_RST_B_M7 [1/2]

#define SRC_SRSR_WDOG4_RST_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M7_MASK)

WDOG4_RST_B_M7 0b0..Reset is not a result of the watchdog4 time-out event. 0b1..Reset is a result of the watchdog4 time-out event.

◆ SRC_SRSR_WDOG4_RST_B_M7 [2/2]

#define SRC_SRSR_WDOG4_RST_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M7_MASK)

WDOG4_RST_B_M7 0b0..Reset is not a result of the watchdog4 time-out event. 0b1..Reset is a result of the watchdog4 time-out event.

◆ SRC_SRSR_WDOG_RST_B

#define SRC_SRSR_WDOG_RST_B ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)

wdog_rst_b 0b0..Reset is not a result of the watchdog time-out event. 0b1..Reset is a result of the watchdog time-out event.

◆ SRC_SRSR_WDOG_RST_B_M4 [1/2]

#define SRC_SRSR_WDOG_RST_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG_RST_B_M4_MASK)

WDOG_RST_B_M4 0b0..Reset is not a result of the watchdog time-out event. 0b1..Reset is a result of the watchdog time-out event.

◆ SRC_SRSR_WDOG_RST_B_M4 [2/2]

#define SRC_SRSR_WDOG_RST_B_M4 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG_RST_B_M4_MASK)

WDOG_RST_B_M4 0b0..Reset is not a result of the watchdog time-out event. 0b1..Reset is a result of the watchdog time-out event.

◆ SRC_SRSR_WDOG_RST_B_M7 [1/2]

#define SRC_SRSR_WDOG_RST_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG_RST_B_M7_MASK)

WDOG_RST_B_M7 0b0..Reset is not a result of the watchdog time-out event. 0b1..Reset is a result of the watchdog time-out event.

◆ SRC_SRSR_WDOG_RST_B_M7 [2/2]

#define SRC_SRSR_WDOG_RST_B_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG_RST_B_M7_MASK)

WDOG_RST_B_M7 0b0..Reset is not a result of the watchdog time-out event. 0b1..Reset is a result of the watchdog time-out event.

◆ SRC_STAT_DISPLAY_RST_BY_HW [1/2]

#define SRC_STAT_DISPLAY_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_HW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_DISPLAY_RST_BY_HW [2/2]

#define SRC_STAT_DISPLAY_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_HW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_DISPLAY_RST_BY_SW [1/2]

#define SRC_STAT_DISPLAY_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_SW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_DISPLAY_RST_BY_SW [2/2]

#define SRC_STAT_DISPLAY_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_SW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_DISPLAY_UNDER_RST [1/2]

#define SRC_STAT_DISPLAY_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_UNDER_RST_SHIFT)) & SRC_STAT_DISPLAY_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_DISPLAY_UNDER_RST [2/2]

#define SRC_STAT_DISPLAY_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_UNDER_RST_SHIFT)) & SRC_STAT_DISPLAY_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_M4CORE_RST_BY_HW [1/2]

#define SRC_STAT_M4CORE_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_M4CORE_RST_BY_HW [2/2]

#define SRC_STAT_M4CORE_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_M4CORE_RST_BY_SW [1/2]

#define SRC_STAT_M4CORE_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_M4CORE_RST_BY_SW [2/2]

#define SRC_STAT_M4CORE_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_M4CORE_UNDER_RST [1/2]

#define SRC_STAT_M4CORE_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_UNDER_RST_SHIFT)) & SRC_STAT_M4CORE_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_M4CORE_UNDER_RST [2/2]

#define SRC_STAT_M4CORE_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_UNDER_RST_SHIFT)) & SRC_STAT_M4CORE_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_M4DEBUG_RST_BY_HW [1/2]

#define SRC_STAT_M4DEBUG_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_M4DEBUG_RST_BY_HW [2/2]

#define SRC_STAT_M4DEBUG_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_M4DEBUG_RST_BY_SW [1/2]

#define SRC_STAT_M4DEBUG_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_M4DEBUG_RST_BY_SW [2/2]

#define SRC_STAT_M4DEBUG_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_M4DEBUG_UNDER_RST [1/2]

#define SRC_STAT_M4DEBUG_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M4DEBUG_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_M4DEBUG_UNDER_RST [2/2]

#define SRC_STAT_M4DEBUG_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M4DEBUG_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_M7CORE_RST_BY_HW [1/2]

#define SRC_STAT_M7CORE_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_M7CORE_RST_BY_HW [2/2]

#define SRC_STAT_M7CORE_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_M7CORE_RST_BY_SW [1/2]

#define SRC_STAT_M7CORE_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_M7CORE_RST_BY_SW [2/2]

#define SRC_STAT_M7CORE_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_M7CORE_UNDER_RST [1/2]

#define SRC_STAT_M7CORE_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_UNDER_RST_SHIFT)) & SRC_STAT_M7CORE_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_M7CORE_UNDER_RST [2/2]

#define SRC_STAT_M7CORE_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_UNDER_RST_SHIFT)) & SRC_STAT_M7CORE_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_M7DEBUG_RST_BY_HW [1/2]

#define SRC_STAT_M7DEBUG_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_M7DEBUG_RST_BY_HW [2/2]

#define SRC_STAT_M7DEBUG_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_M7DEBUG_RST_BY_SW [1/2]

#define SRC_STAT_M7DEBUG_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_M7DEBUG_RST_BY_SW [2/2]

#define SRC_STAT_M7DEBUG_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_M7DEBUG_UNDER_RST [1/2]

#define SRC_STAT_M7DEBUG_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M7DEBUG_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_M7DEBUG_UNDER_RST [2/2]

#define SRC_STAT_M7DEBUG_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M7DEBUG_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_MEGA_RST_BY_HW [1/2]

#define SRC_STAT_MEGA_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_HW_SHIFT)) & SRC_STAT_MEGA_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_MEGA_RST_BY_HW [2/2]

#define SRC_STAT_MEGA_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_HW_SHIFT)) & SRC_STAT_MEGA_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_MEGA_RST_BY_SW [1/2]

#define SRC_STAT_MEGA_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_SW_SHIFT)) & SRC_STAT_MEGA_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_MEGA_RST_BY_SW [2/2]

#define SRC_STAT_MEGA_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_SW_SHIFT)) & SRC_STAT_MEGA_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_MEGA_UNDER_RST [1/2]

#define SRC_STAT_MEGA_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_UNDER_RST_SHIFT)) & SRC_STAT_MEGA_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_MEGA_UNDER_RST [2/2]

#define SRC_STAT_MEGA_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_UNDER_RST_SHIFT)) & SRC_STAT_MEGA_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_USBPHY1_RST_BY_HW [1/2]

#define SRC_STAT_USBPHY1_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_USBPHY1_RST_BY_HW [2/2]

#define SRC_STAT_USBPHY1_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_USBPHY1_RST_BY_SW [1/2]

#define SRC_STAT_USBPHY1_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_USBPHY1_RST_BY_SW [2/2]

#define SRC_STAT_USBPHY1_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_USBPHY1_UNDER_RST [1/2]

#define SRC_STAT_USBPHY1_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY1_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_USBPHY1_UNDER_RST [2/2]

#define SRC_STAT_USBPHY1_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY1_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_USBPHY2_RST_BY_HW [1/2]

#define SRC_STAT_USBPHY2_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_USBPHY2_RST_BY_HW [2/2]

#define SRC_STAT_USBPHY2_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_USBPHY2_RST_BY_SW [1/2]

#define SRC_STAT_USBPHY2_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_USBPHY2_RST_BY_SW [2/2]

#define SRC_STAT_USBPHY2_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_USBPHY2_UNDER_RST [1/2]

#define SRC_STAT_USBPHY2_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY2_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_USBPHY2_UNDER_RST [2/2]

#define SRC_STAT_USBPHY2_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY2_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_WAKEUP_RST_BY_HW [1/2]

#define SRC_STAT_WAKEUP_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_HW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_WAKEUP_RST_BY_HW [2/2]

#define SRC_STAT_WAKEUP_RST_BY_HW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_HW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_HW_MASK)

RST_BY_HW 0b0..the reset is not caused by the power mode transfer 0b1..the reset is caused by the power mode transfer

◆ SRC_STAT_WAKEUP_RST_BY_SW [1/2]

#define SRC_STAT_WAKEUP_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_SW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_WAKEUP_RST_BY_SW [2/2]

#define SRC_STAT_WAKEUP_RST_BY_SW ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_SW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_SW_MASK)

RST_BY_SW 0b0..the reset is not caused by software setting 0b1..the reset is caused by software setting

◆ SRC_STAT_WAKEUP_UNDER_RST [1/2]

#define SRC_STAT_WAKEUP_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_UNDER_RST_SHIFT)) & SRC_STAT_WAKEUP_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

◆ SRC_STAT_WAKEUP_UNDER_RST [2/2]

#define SRC_STAT_WAKEUP_UNDER_RST ( x ) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_UNDER_RST_SHIFT)) & SRC_STAT_WAKEUP_UNDER_RST_MASK)

UNDER_RST 0b0..the reset is finished 0b1..the reset is in process

Macros

SCR - SRC Control Register

SBMR1 - SRC Boot Mode Register 1

SRSR - SRC Reset Status Register

SBMR2 - SRC Boot Mode Register 2

GPR - SRC General Purpose Register 1..SRC General Purpose Register 10

SCR - SRC Control Register

SRMR - SRC Reset Mode Register

SBMR1 - SRC Boot Mode Register 1

SBMR2 - SRC Boot Mode Register 2

SRSR - SRC Reset Status Register

GPR - SRC General Purpose Register

AUTHEN_MEGA - Slice Authentication Register

CTRL_MEGA - Slice Control Register

SETPOINT_MEGA - Slice Setpoint Config Register

DOMAIN_MEGA - Slice Domain Config Register

STAT_MEGA - Slice Status Register

AUTHEN_DISPLAY - Slice Authentication Register

CTRL_DISPLAY - Slice Control Register

SETPOINT_DISPLAY - Slice Setpoint Config Register

DOMAIN_DISPLAY - Slice Domain Config Register

STAT_DISPLAY - Slice Status Register

AUTHEN_WAKEUP - Slice Authentication Register

CTRL_WAKEUP - Slice Control Register

SETPOINT_WAKEUP - Slice Setpoint Config Register

DOMAIN_WAKEUP - Slice Domain Config Register

STAT_WAKEUP - Slice Status Register

AUTHEN_M4CORE - Slice Authentication Register

CTRL_M4CORE - Slice Control Register

SETPOINT_M4CORE - Slice Setpoint Config Register

DOMAIN_M4CORE - Slice Domain Config Register

STAT_M4CORE - Slice Status Register

AUTHEN_M7CORE - Slice Authentication Register

CTRL_M7CORE - Slice Control Register

SETPOINT_M7CORE - Slice Setpoint Config Register

DOMAIN_M7CORE - Slice Domain Config Register

STAT_M7CORE - Slice Status Register

AUTHEN_M4DEBUG - Slice Authentication Register

CTRL_M4DEBUG - Slice Control Register

SETPOINT_M4DEBUG - Slice Setpoint Config Register

DOMAIN_M4DEBUG - Slice Domain Config Register

STAT_M4DEBUG - Slice Status Register

AUTHEN_M7DEBUG - Slice Authentication Register

CTRL_M7DEBUG - Slice Control Register

SETPOINT_M7DEBUG - Slice Setpoint Config Register

DOMAIN_M7DEBUG - Slice Domain Config Register

STAT_M7DEBUG - Slice Status Register

AUTHEN_USBPHY1 - Slice Authentication Register

CTRL_USBPHY1 - Slice Control Register

SETPOINT_USBPHY1 - Slice Setpoint Config Register

DOMAIN_USBPHY1 - Slice Domain Config Register

STAT_USBPHY1 - Slice Status Register

AUTHEN_USBPHY2 - Slice Authentication Register

CTRL_USBPHY2 - Slice Control Register

SETPOINT_USBPHY2 - Slice Setpoint Config Register

DOMAIN_USBPHY2 - Slice Domain Config Register

STAT_USBPHY2 - Slice Status Register

SCR - SRC Control Register

SRMR - SRC Reset Mode Register

SBMR1 - SRC Boot Mode Register 1

SBMR2 - SRC Boot Mode Register 2

SRSR - SRC Reset Status Register

GPR - SRC General Purpose Register

AUTHEN_MEGA - Slice Authentication Register

CTRL_MEGA - Slice Control Register

SETPOINT_MEGA - Slice Setpoint Config Register

DOMAIN_MEGA - Slice Domain Config Register

STAT_MEGA - Slice Status Register

AUTHEN_DISPLAY - Slice Authentication Register

CTRL_DISPLAY - Slice Control Register

SETPOINT_DISPLAY - Slice Setpoint Config Register

DOMAIN_DISPLAY - Slice Domain Config Register

STAT_DISPLAY - Slice Status Register

AUTHEN_WAKEUP - Slice Authentication Register

CTRL_WAKEUP - Slice Control Register

SETPOINT_WAKEUP - Slice Setpoint Config Register

DOMAIN_WAKEUP - Slice Domain Config Register

STAT_WAKEUP - Slice Status Register

AUTHEN_M4CORE - Slice Authentication Register

CTRL_M4CORE - Slice Control Register