RTEMS 6.1-rc6
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Macros
Interrupt distribution control (INTCTRL)

This group contains register bit definitions. More...

Macros

#define GRSPW2_INTCTRL_INTNUM_SHIFT   26
 
#define GRSPW2_INTCTRL_INTNUM_MASK   0xfc000000U
 
#define GRSPW2_INTCTRL_INTNUM_GET(_reg)
 
#define GRSPW2_INTCTRL_INTNUM_SET(_reg, _val)
 
#define GRSPW2_INTCTRL_INTNUM(_val)
 
#define GRSPW2_INTCTRL_RS   0x2000000U
 
#define GRSPW2_INTCTRL_EE   0x1000000U
 
#define GRSPW2_INTCTRL_IA   0x800000U
 
#define GRSPW2_INTCTRL_RES   0x2U
 
#define GRSPW2_INTCTRL_RES   0x40000U
 
#define GRSPW2_INTCTRL_RES   0x2000U
 
#define GRSPW2_INTCTRL_TQ_SHIFT   21
 
#define GRSPW2_INTCTRL_TQ_MASK   0x600000U
 
#define GRSPW2_INTCTRL_TQ_GET(_reg)
 
#define GRSPW2_INTCTRL_TQ_SET(_reg, _val)
 
#define GRSPW2_INTCTRL_TQ(_val)
 
#define GRSPW2_INTCTRL_AQ   0x100000U
 
#define GRSPW2_INTCTRL_IQ   0x80000U
 
#define GRSPW2_INTCTRL_AA_SHIFT   16
 
#define GRSPW2_INTCTRL_AA_MASK   0x30000U
 
#define GRSPW2_INTCTRL_AA_GET(_reg)
 
#define GRSPW2_INTCTRL_AA_SET(_reg, _val)
 
#define GRSPW2_INTCTRL_AA(_val)
 
#define GRSPW2_INTCTRL_AT   0x8000U
 
#define GRSPW2_INTCTRL_IT   0x4000U
 
#define GRSPW2_INTCTRL_ID_SHIFT   8
 
#define GRSPW2_INTCTRL_ID_MASK   0x1f00U
 
#define GRSPW2_INTCTRL_ID_GET(_reg)
 
#define GRSPW2_INTCTRL_ID_SET(_reg, _val)
 
#define GRSPW2_INTCTRL_ID(_val)
 
#define GRSPW2_INTCTRL_II   0x80U
 
#define GRSPW2_INTCTRL_TXINT   0x40U
 

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

◆ GRSPW2_INTCTRL_AA

#define GRSPW2_INTCTRL_AA (   _val)
Value:
( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & \
GRSPW2_INTCTRL_AA_MASK )

◆ GRSPW2_INTCTRL_AA_GET

#define GRSPW2_INTCTRL_AA_GET (   _reg)
Value:
( ( ( _reg ) & GRSPW2_INTCTRL_AA_MASK ) >> \
GRSPW2_INTCTRL_AA_SHIFT )

◆ GRSPW2_INTCTRL_AA_SET

#define GRSPW2_INTCTRL_AA_SET (   _reg,
  _val 
)
Value:
( ( ( _reg ) & ~GRSPW2_INTCTRL_AA_MASK ) | \
( ( ( _val ) << GRSPW2_INTCTRL_AA_SHIFT ) & \
GRSPW2_INTCTRL_AA_MASK ) )

◆ GRSPW2_INTCTRL_ID

#define GRSPW2_INTCTRL_ID (   _val)
Value:
( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & \
GRSPW2_INTCTRL_ID_MASK )

◆ GRSPW2_INTCTRL_ID_GET

#define GRSPW2_INTCTRL_ID_GET (   _reg)
Value:
( ( ( _reg ) & GRSPW2_INTCTRL_ID_MASK ) >> \
GRSPW2_INTCTRL_ID_SHIFT )

◆ GRSPW2_INTCTRL_ID_SET

#define GRSPW2_INTCTRL_ID_SET (   _reg,
  _val 
)
Value:
( ( ( _reg ) & ~GRSPW2_INTCTRL_ID_MASK ) | \
( ( ( _val ) << GRSPW2_INTCTRL_ID_SHIFT ) & \
GRSPW2_INTCTRL_ID_MASK ) )

◆ GRSPW2_INTCTRL_INTNUM

#define GRSPW2_INTCTRL_INTNUM (   _val)
Value:
( ( ( _val ) << GRSPW2_INTCTRL_INTNUM_SHIFT ) & \
GRSPW2_INTCTRL_INTNUM_MASK )

◆ GRSPW2_INTCTRL_INTNUM_GET

#define GRSPW2_INTCTRL_INTNUM_GET (   _reg)
Value:
( ( ( _reg ) & GRSPW2_INTCTRL_INTNUM_MASK ) >> \
GRSPW2_INTCTRL_INTNUM_SHIFT )

◆ GRSPW2_INTCTRL_INTNUM_SET

#define GRSPW2_INTCTRL_INTNUM_SET (   _reg,
  _val 
)
Value:
( ( ( _reg ) & ~GRSPW2_INTCTRL_INTNUM_MASK ) | \
( ( ( _val ) << GRSPW2_INTCTRL_INTNUM_SHIFT ) & \
GRSPW2_INTCTRL_INTNUM_MASK ) )

◆ GRSPW2_INTCTRL_TQ

#define GRSPW2_INTCTRL_TQ (   _val)
Value:
( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & \
GRSPW2_INTCTRL_TQ_MASK )

◆ GRSPW2_INTCTRL_TQ_GET

#define GRSPW2_INTCTRL_TQ_GET (   _reg)
Value:
( ( ( _reg ) & GRSPW2_INTCTRL_TQ_MASK ) >> \
GRSPW2_INTCTRL_TQ_SHIFT )

◆ GRSPW2_INTCTRL_TQ_SET

#define GRSPW2_INTCTRL_TQ_SET (   _reg,
  _val 
)
Value:
( ( ( _reg ) & ~GRSPW2_INTCTRL_TQ_MASK ) | \
( ( ( _val ) << GRSPW2_INTCTRL_TQ_SHIFT ) & \
GRSPW2_INTCTRL_TQ_MASK ) )