Capability register 0 (CAP0)

This group contains register bit definitions. More...

Macros
#define	GRIOMMU_CAP0_A   0x80000000U
#define	GRIOMMU_CAP0_AC   0x40000000U
#define	GRIOMMU_CAP0_CA   0x20000000U
#define	GRIOMMU_CAP0_CP   0x10000000U
#define	GRIOMMU_CAP0_NARB_SHIFT   20
#define	GRIOMMU_CAP0_NARB_MASK   0xf00000U
#define	GRIOMMU_CAP0_NARB_GET(_reg)
#define	GRIOMMU_CAP0_NARB_SET(_reg, _val)
#define	GRIOMMU_CAP0_NARB(_val)
#define	GRIOMMU_CAP0_CS   0x80000U
#define	GRIOMMU_CAP0_FT_SHIFT   17
#define	GRIOMMU_CAP0_FT_MASK   0x60000U
#define	GRIOMMU_CAP0_FT_GET(_reg)
#define	GRIOMMU_CAP0_FT_SET(_reg, _val)
#define	GRIOMMU_CAP0_FT(_val)
#define	GRIOMMU_CAP0_ST   0x10000U
#define	GRIOMMU_CAP0_I   0x8000U
#define	GRIOMMU_CAP0_IT   0x4000U
#define	GRIOMMU_CAP0_IA   0x2000U
#define	GRIOMMU_CAP0_IP   0x1000U
#define	GRIOMMU_CAP0_MB   0x100U
#define	GRIOMMU_CAP0_GRPS_SHIFT   4
#define	GRIOMMU_CAP0_GRPS_MASK   0xf0U
#define	GRIOMMU_CAP0_GRPS_GET(_reg)
#define	GRIOMMU_CAP0_GRPS_SET(_reg, _val)
#define	GRIOMMU_CAP0_GRPS(_val)
#define	GRIOMMU_CAP0_MSTS_SHIFT   0
#define	GRIOMMU_CAP0_MSTS_MASK   0xfU
#define	GRIOMMU_CAP0_MSTS_GET(_reg)
#define	GRIOMMU_CAP0_MSTS_SET(_reg, _val)
#define	GRIOMMU_CAP0_MSTS(_val)

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

GRIOMMU_CAP0_FT

#define GRIOMMU_CAP0_FT

(

_val

)

Value:

  ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & \
    GRIOMMU_CAP0_FT_MASK )

GRIOMMU_CAP0_FT_GET

#define GRIOMMU_CAP0_FT_GET

(

_reg

)

Value:

  ( ( ( _reg ) & GRIOMMU_CAP0_FT_MASK ) >> \
    GRIOMMU_CAP0_FT_SHIFT )

GRIOMMU_CAP0_FT_SET

#define GRIOMMU_CAP0_FT_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~GRIOMMU_CAP0_FT_MASK ) | \
    ( ( ( _val ) << GRIOMMU_CAP0_FT_SHIFT ) & \
      GRIOMMU_CAP0_FT_MASK ) )

GRIOMMU_CAP0_GRPS

#define GRIOMMU_CAP0_GRPS

(

_val

)

Value:

  ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & \
    GRIOMMU_CAP0_GRPS_MASK )

GRIOMMU_CAP0_GRPS_GET

#define GRIOMMU_CAP0_GRPS_GET

(

_reg

)

Value:

  ( ( ( _reg ) & GRIOMMU_CAP0_GRPS_MASK ) >> \
    GRIOMMU_CAP0_GRPS_SHIFT )

GRIOMMU_CAP0_GRPS_SET

#define GRIOMMU_CAP0_GRPS_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~GRIOMMU_CAP0_GRPS_MASK ) | \
    ( ( ( _val ) << GRIOMMU_CAP0_GRPS_SHIFT ) & \
      GRIOMMU_CAP0_GRPS_MASK ) )

GRIOMMU_CAP0_MSTS

#define GRIOMMU_CAP0_MSTS

(

_val

)

Value:

  ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & \
    GRIOMMU_CAP0_MSTS_MASK )

GRIOMMU_CAP0_MSTS_GET

#define GRIOMMU_CAP0_MSTS_GET

(

_reg

)

Value:

  ( ( ( _reg ) & GRIOMMU_CAP0_MSTS_MASK ) >> \
    GRIOMMU_CAP0_MSTS_SHIFT )

GRIOMMU_CAP0_MSTS_SET

#define GRIOMMU_CAP0_MSTS_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~GRIOMMU_CAP0_MSTS_MASK ) | \
    ( ( ( _val ) << GRIOMMU_CAP0_MSTS_SHIFT ) & \
      GRIOMMU_CAP0_MSTS_MASK ) )

GRIOMMU_CAP0_NARB

#define GRIOMMU_CAP0_NARB

(

_val

)

Value:

  ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & \
    GRIOMMU_CAP0_NARB_MASK )

GRIOMMU_CAP0_NARB_GET

#define GRIOMMU_CAP0_NARB_GET

(

_reg

)

Value:

  ( ( ( _reg ) & GRIOMMU_CAP0_NARB_MASK ) >> \
    GRIOMMU_CAP0_NARB_SHIFT )

GRIOMMU_CAP0_NARB_SET

#define GRIOMMU_CAP0_NARB_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~GRIOMMU_CAP0_NARB_MASK ) | \
    ( ( ( _val ) << GRIOMMU_CAP0_NARB_SHIFT ) & \
      GRIOMMU_CAP0_NARB_MASK ) )