PIT Peripheral Access Layer

Modules
	PIT Register Masks

Data Structures
struct	PIT_Type

Macros
#define	PIT_BASE   (0x40084000u)
#define	PIT   ((PIT_Type *)PIT_BASE)
#define	PIT_BASE_ADDRS   { PIT_BASE }
#define	PIT_BASE_PTRS   { PIT }
#define	PIT_IRQS   { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
#define	PIT1_BASE   (0x400D8000u)
#define	PIT1   ((PIT_Type *)PIT1_BASE)
#define	PIT2_BASE   (0x40CB0000u)
#define	PIT2   ((PIT_Type *)PIT2_BASE)
#define	PIT_BASE_ADDRS   { 0u, PIT1_BASE, PIT2_BASE }
#define	PIT_BASE_PTRS   { (PIT_Type *)0u, PIT1, PIT2 }
#define	PIT_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PIT1_IRQn, PIT1_IRQn, PIT1_IRQn, PIT1_IRQn }, { PIT2_IRQn, PIT2_IRQn, PIT2_IRQn, PIT2_IRQn } }
#define	PIT1_BASE   (0x400D8000u)
#define	PIT1   ((PIT_Type *)PIT1_BASE)
#define	PIT2_BASE   (0x40CB0000u)
#define	PIT2   ((PIT_Type *)PIT2_BASE)
#define	PIT_BASE_ADDRS   { 0u, PIT1_BASE, PIT2_BASE }
#define	PIT_BASE_PTRS   { (PIT_Type *)0u, PIT1, PIT2 }
#define	PIT_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PIT1_IRQn, PIT1_IRQn, PIT1_IRQn, PIT1_IRQn }, { PIT2_IRQn, PIT2_IRQn, PIT2_IRQn, PIT2_IRQn } }

Detailed Description

Macro Definition Documentation

PIT

#define PIT   ((PIT_Type *)PIT_BASE)

Peripheral PIT base pointer

PIT1 [1/2]

#define PIT1   ((PIT_Type *)PIT1_BASE)

Peripheral PIT1 base pointer

PIT1 [2/2]

#define PIT1   ((PIT_Type *)PIT1_BASE)

Peripheral PIT1 base pointer

PIT1_BASE [1/2]

#define PIT1_BASE   (0x400D8000u)

Peripheral PIT1 base address

PIT1_BASE [2/2]

#define PIT1_BASE   (0x400D8000u)

Peripheral PIT1 base address

PIT2 [1/2]

#define PIT2   ((PIT_Type *)PIT2_BASE)

Peripheral PIT2 base pointer

PIT2 [2/2]

#define PIT2   ((PIT_Type *)PIT2_BASE)

Peripheral PIT2 base pointer

PIT2_BASE [1/2]

#define PIT2_BASE   (0x40CB0000u)

Peripheral PIT2 base address

PIT2_BASE [2/2]

#define PIT2_BASE   (0x40CB0000u)

Peripheral PIT2 base address

PIT_BASE

#define PIT_BASE   (0x40084000u)

Peripheral PIT base address

PIT_BASE_ADDRS [1/3]

#define PIT_BASE_ADDRS   { PIT_BASE }

Array initializer of PIT peripheral base addresses

PIT_BASE_ADDRS [2/3]

#define PIT_BASE_ADDRS   { 0u, PIT1_BASE, PIT2_BASE }

Array initializer of PIT peripheral base addresses

PIT_BASE_ADDRS [3/3]

#define PIT_BASE_ADDRS   { 0u, PIT1_BASE, PIT2_BASE }

Array initializer of PIT peripheral base addresses

PIT_BASE_PTRS [1/3]

#define PIT_BASE_PTRS   { PIT }

Array initializer of PIT peripheral base pointers

PIT_BASE_PTRS [2/3]

#define PIT_BASE_PTRS   { (PIT_Type *)0u, PIT1, PIT2 }

Array initializer of PIT peripheral base pointers

PIT_BASE_PTRS [3/3]

#define PIT_BASE_PTRS   { (PIT_Type *)0u, PIT1, PIT2 }

Array initializer of PIT peripheral base pointers

PIT_IRQS [1/3]

#define PIT_IRQS   { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }

Interrupt vectors for the PIT peripheral type

PIT_IRQS [2/3]

#define PIT_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PIT1_IRQn, PIT1_IRQn, PIT1_IRQn, PIT1_IRQn }, { PIT2_IRQn, PIT2_IRQn, PIT2_IRQn, PIT2_IRQn } }

Interrupt vectors for the PIT peripheral type

PIT_IRQS [3/3]

#define PIT_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PIT1_IRQn, PIT1_IRQn, PIT1_IRQn, PIT1_IRQn }, { PIT2_IRQn, PIT2_IRQn, PIT2_IRQn, PIT2_IRQn } }

Interrupt vectors for the PIT peripheral type