PGC Register Masks

MEGA_CTRL - PGC Mega Control Register
#define	PGC_MEGA_CTRL_PCR_MASK   (0x1U)
#define	PGC_MEGA_CTRL_PCR_SHIFT   (0U)
#define	PGC_MEGA_CTRL_PCR(x)   (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)

MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register
#define	PGC_MEGA_PUPSCR_SW_MASK   (0x3FU)
#define	PGC_MEGA_PUPSCR_SW_SHIFT   (0U)
#define	PGC_MEGA_PUPSCR_SW(x)   (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)
#define	PGC_MEGA_PUPSCR_SW2ISO_MASK   (0x3F00U)
#define	PGC_MEGA_PUPSCR_SW2ISO_SHIFT   (8U)
#define	PGC_MEGA_PUPSCR_SW2ISO(x)   (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)

MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register
#define	PGC_MEGA_PDNSCR_ISO_MASK   (0x3FU)
#define	PGC_MEGA_PDNSCR_ISO_SHIFT   (0U)
#define	PGC_MEGA_PDNSCR_ISO(x)   (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)
#define	PGC_MEGA_PDNSCR_ISO2SW_MASK   (0x3F00U)
#define	PGC_MEGA_PDNSCR_ISO2SW_SHIFT   (8U)
#define	PGC_MEGA_PDNSCR_ISO2SW(x)   (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)

MEGA_SR - PGC Mega Power Gating Controller Status Register
#define	PGC_MEGA_SR_PSR_MASK   (0x1U)
#define	PGC_MEGA_SR_PSR_SHIFT   (0U)
#define	PGC_MEGA_SR_PSR(x)   (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)

CPU_CTRL - PGC CPU Control Register
#define	PGC_CPU_CTRL_PCR_MASK   (0x1U)
#define	PGC_CPU_CTRL_PCR_SHIFT   (0U)
#define	PGC_CPU_CTRL_PCR(x)   (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)

CPU_PUPSCR - PGC CPU Power Up Sequence Control Register
#define	PGC_CPU_PUPSCR_SW_MASK   (0x3FU)
#define	PGC_CPU_PUPSCR_SW_SHIFT   (0U)
#define	PGC_CPU_PUPSCR_SW(x)   (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)
#define	PGC_CPU_PUPSCR_SW2ISO_MASK   (0x3F00U)
#define	PGC_CPU_PUPSCR_SW2ISO_SHIFT   (8U)
#define	PGC_CPU_PUPSCR_SW2ISO(x)   (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)

CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register
#define	PGC_CPU_PDNSCR_ISO_MASK   (0x3FU)
#define	PGC_CPU_PDNSCR_ISO_SHIFT   (0U)
#define	PGC_CPU_PDNSCR_ISO(x)   (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)
#define	PGC_CPU_PDNSCR_ISO2SW_MASK   (0x3F00U)
#define	PGC_CPU_PDNSCR_ISO2SW_SHIFT   (8U)
#define	PGC_CPU_PDNSCR_ISO2SW(x)   (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)

CPU_SR - PGC CPU Power Gating Controller Status Register
#define	PGC_CPU_SR_PSR_MASK   (0x1U)
#define	PGC_CPU_SR_PSR_SHIFT   (0U)
#define	PGC_CPU_SR_PSR(x)   (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)

Detailed Description

Macro Definition Documentation

PGC_CPU_CTRL_PCR

#define PGC_CPU_CTRL_PCR

(

x

)

(((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)

PCR 0b0..Do not switch off power even if pdn_req is asserted. 0b1..Switch off power when pdn_req is asserted.

PGC_CPU_SR_PSR

#define PGC_CPU_SR_PSR

(

x

)

(((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)

PSR 0b0..The target subsystem was not powered down for the previous power-down request. 0b1..The target subsystem was powered down for the previous power-down request.

PGC_MEGA_CTRL_PCR

#define PGC_MEGA_CTRL_PCR

(

x

)

(((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)

PCR 0b0..Do not switch off power even if pdn_req is asserted. 0b1..Switch off power when pdn_req is asserted.

PGC_MEGA_SR_PSR

#define PGC_MEGA_SR_PSR

(

x

)

(((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)

PSR 0b0..The target subsystem was not powered down for the previous power-down request. 0b1..The target subsystem was powered down for the previous power-down request.