RTEMS 6.1-rc6
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Macros
PDM Register Masks
Mapping Information » Iomuxc_pads » Device Peripheral Access Layer » PDM Peripheral Access Layer

Macros

#define PDM_DATACH_COUNT   (8U)
 
#define PDM_DATACH_COUNT   (8U)
 

CTRL_1 - PDM Control register 1

#define PDM_CTRL_1_CH0EN_MASK   (0x1U)
 
#define PDM_CTRL_1_CH0EN_SHIFT   (0U)
 
#define PDM_CTRL_1_CH0EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
 
#define PDM_CTRL_1_CH1EN_MASK   (0x2U)
 
#define PDM_CTRL_1_CH1EN_SHIFT   (1U)
 
#define PDM_CTRL_1_CH1EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
 
#define PDM_CTRL_1_CH2EN_MASK   (0x4U)
 
#define PDM_CTRL_1_CH2EN_SHIFT   (2U)
 
#define PDM_CTRL_1_CH2EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
 
#define PDM_CTRL_1_CH3EN_MASK   (0x8U)
 
#define PDM_CTRL_1_CH3EN_SHIFT   (3U)
 
#define PDM_CTRL_1_CH3EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
 
#define PDM_CTRL_1_CH4EN_MASK   (0x10U)
 
#define PDM_CTRL_1_CH4EN_SHIFT   (4U)
 
#define PDM_CTRL_1_CH4EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)
 
#define PDM_CTRL_1_CH5EN_MASK   (0x20U)
 
#define PDM_CTRL_1_CH5EN_SHIFT   (5U)
 
#define PDM_CTRL_1_CH5EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)
 
#define PDM_CTRL_1_CH6EN_MASK   (0x40U)
 
#define PDM_CTRL_1_CH6EN_SHIFT   (6U)
 
#define PDM_CTRL_1_CH6EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)
 
#define PDM_CTRL_1_CH7EN_MASK   (0x80U)
 
#define PDM_CTRL_1_CH7EN_SHIFT   (7U)
 
#define PDM_CTRL_1_CH7EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)
 
#define PDM_CTRL_1_ERREN_MASK   (0x800000U)
 
#define PDM_CTRL_1_ERREN_SHIFT   (23U)
 
#define PDM_CTRL_1_ERREN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
 
#define PDM_CTRL_1_DISEL_MASK   (0x3000000U)
 
#define PDM_CTRL_1_DISEL_SHIFT   (24U)
 
#define PDM_CTRL_1_DISEL(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
 
#define PDM_CTRL_1_DBGE_MASK   (0x4000000U)
 
#define PDM_CTRL_1_DBGE_SHIFT   (26U)
 
#define PDM_CTRL_1_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
 
#define PDM_CTRL_1_SRES_MASK   (0x8000000U)
 
#define PDM_CTRL_1_SRES_SHIFT   (27U)
 
#define PDM_CTRL_1_SRES(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
 
#define PDM_CTRL_1_DBG_MASK   (0x10000000U)
 
#define PDM_CTRL_1_DBG_SHIFT   (28U)
 
#define PDM_CTRL_1_DBG(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
 
#define PDM_CTRL_1_PDMIEN_MASK   (0x20000000U)
 
#define PDM_CTRL_1_PDMIEN_SHIFT   (29U)
 
#define PDM_CTRL_1_PDMIEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
 
#define PDM_CTRL_1_DOZEN_MASK   (0x40000000U)
 
#define PDM_CTRL_1_DOZEN_SHIFT   (30U)
 
#define PDM_CTRL_1_DOZEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
 
#define PDM_CTRL_1_MDIS_MASK   (0x80000000U)
 
#define PDM_CTRL_1_MDIS_SHIFT   (31U)
 
#define PDM_CTRL_1_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
 

CTRL_2 - PDM Control register 2

#define PDM_CTRL_2_CLKDIV_MASK   (0xFFU)
 
#define PDM_CTRL_2_CLKDIV_SHIFT   (0U)
 
#define PDM_CTRL_2_CLKDIV(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
 
#define PDM_CTRL_2_CICOSR_MASK   (0xF0000U)
 
#define PDM_CTRL_2_CICOSR_SHIFT   (16U)
 
#define PDM_CTRL_2_CICOSR(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
 
#define PDM_CTRL_2_QSEL_MASK   (0xE000000U)
 
#define PDM_CTRL_2_QSEL_SHIFT   (25U)
 
#define PDM_CTRL_2_QSEL(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
 

STAT - PDM Status register

#define PDM_STAT_CH0F_MASK   (0x1U)
 
#define PDM_STAT_CH0F_SHIFT   (0U)
 
#define PDM_STAT_CH0F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
 
#define PDM_STAT_CH1F_MASK   (0x2U)
 
#define PDM_STAT_CH1F_SHIFT   (1U)
 
#define PDM_STAT_CH1F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
 
#define PDM_STAT_CH2F_MASK   (0x4U)
 
#define PDM_STAT_CH2F_SHIFT   (2U)
 
#define PDM_STAT_CH2F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
 
#define PDM_STAT_CH3F_MASK   (0x8U)
 
#define PDM_STAT_CH3F_SHIFT   (3U)
 
#define PDM_STAT_CH3F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
 
#define PDM_STAT_CH4F_MASK   (0x10U)
 
#define PDM_STAT_CH4F_SHIFT   (4U)
 
#define PDM_STAT_CH4F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)
 
#define PDM_STAT_CH5F_MASK   (0x20U)
 
#define PDM_STAT_CH5F_SHIFT   (5U)
 
#define PDM_STAT_CH5F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)
 
#define PDM_STAT_CH6F_MASK   (0x40U)
 
#define PDM_STAT_CH6F_SHIFT   (6U)
 
#define PDM_STAT_CH6F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)
 
#define PDM_STAT_CH7F_MASK   (0x80U)
 
#define PDM_STAT_CH7F_SHIFT   (7U)
 
#define PDM_STAT_CH7F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)
 
#define PDM_STAT_LOWFREQF_MASK   (0x20000000U)
 
#define PDM_STAT_LOWFREQF_SHIFT   (29U)
 
#define PDM_STAT_LOWFREQF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)
 
#define PDM_STAT_FIR_RDY_MASK   (0x40000000U)
 
#define PDM_STAT_FIR_RDY_SHIFT   (30U)
 
#define PDM_STAT_FIR_RDY(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)
 
#define PDM_STAT_BSY_FIL_MASK   (0x80000000U)
 
#define PDM_STAT_BSY_FIL_SHIFT   (31U)
 
#define PDM_STAT_BSY_FIL(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
 

FIFO_CTRL - PDM FIFO Control register

#define PDM_FIFO_CTRL_FIFOWMK_MASK   (0x7U)
 
#define PDM_FIFO_CTRL_FIFOWMK_SHIFT   (0U)
 
#define PDM_FIFO_CTRL_FIFOWMK(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
 

FIFO_STAT - PDM FIFO Status register

#define PDM_FIFO_STAT_FIFOOVF0_MASK   (0x1U)
 
#define PDM_FIFO_STAT_FIFOOVF0_SHIFT   (0U)
 
#define PDM_FIFO_STAT_FIFOOVF0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF1_MASK   (0x2U)
 
#define PDM_FIFO_STAT_FIFOOVF1_SHIFT   (1U)
 
#define PDM_FIFO_STAT_FIFOOVF1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF2_MASK   (0x4U)
 
#define PDM_FIFO_STAT_FIFOOVF2_SHIFT   (2U)
 
#define PDM_FIFO_STAT_FIFOOVF2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF3_MASK   (0x8U)
 
#define PDM_FIFO_STAT_FIFOOVF3_SHIFT   (3U)
 
#define PDM_FIFO_STAT_FIFOOVF3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF4_MASK   (0x10U)
 
#define PDM_FIFO_STAT_FIFOOVF4_SHIFT   (4U)
 
#define PDM_FIFO_STAT_FIFOOVF4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF5_MASK   (0x20U)
 
#define PDM_FIFO_STAT_FIFOOVF5_SHIFT   (5U)
 
#define PDM_FIFO_STAT_FIFOOVF5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF6_MASK   (0x40U)
 
#define PDM_FIFO_STAT_FIFOOVF6_SHIFT   (6U)
 
#define PDM_FIFO_STAT_FIFOOVF6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF7_MASK   (0x80U)
 
#define PDM_FIFO_STAT_FIFOOVF7_SHIFT   (7U)
 
#define PDM_FIFO_STAT_FIFOOVF7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)
 
#define PDM_FIFO_STAT_FIFOUND0_MASK   (0x100U)
 
#define PDM_FIFO_STAT_FIFOUND0_SHIFT   (8U)
 
#define PDM_FIFO_STAT_FIFOUND0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
 
#define PDM_FIFO_STAT_FIFOUND1_MASK   (0x200U)
 
#define PDM_FIFO_STAT_FIFOUND1_SHIFT   (9U)
 
#define PDM_FIFO_STAT_FIFOUND1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
 
#define PDM_FIFO_STAT_FIFOUND2_MASK   (0x400U)
 
#define PDM_FIFO_STAT_FIFOUND2_SHIFT   (10U)
 
#define PDM_FIFO_STAT_FIFOUND2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
 
#define PDM_FIFO_STAT_FIFOUND3_MASK   (0x800U)
 
#define PDM_FIFO_STAT_FIFOUND3_SHIFT   (11U)
 
#define PDM_FIFO_STAT_FIFOUND3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
 
#define PDM_FIFO_STAT_FIFOUND4_MASK   (0x1000U)
 
#define PDM_FIFO_STAT_FIFOUND4_SHIFT   (12U)
 
#define PDM_FIFO_STAT_FIFOUND4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)
 
#define PDM_FIFO_STAT_FIFOUND5_MASK   (0x2000U)
 
#define PDM_FIFO_STAT_FIFOUND5_SHIFT   (13U)
 
#define PDM_FIFO_STAT_FIFOUND5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)
 
#define PDM_FIFO_STAT_FIFOUND6_MASK   (0x4000U)
 
#define PDM_FIFO_STAT_FIFOUND6_SHIFT   (14U)
 
#define PDM_FIFO_STAT_FIFOUND6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)
 
#define PDM_FIFO_STAT_FIFOUND7_MASK   (0x8000U)
 
#define PDM_FIFO_STAT_FIFOUND7_SHIFT   (15U)
 
#define PDM_FIFO_STAT_FIFOUND7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
 

DATACH - PDM Output Result Register

#define PDM_DATACH_DATA_MASK   (0xFFFFFFFFU)
 
#define PDM_DATACH_DATA_SHIFT   (0U)
 
#define PDM_DATACH_DATA(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
 

DC_CTRL - PDM DC Remover Control register

#define PDM_DC_CTRL_DCCONFIG0_MASK   (0x3U)
 
#define PDM_DC_CTRL_DCCONFIG0_SHIFT   (0U)
 
#define PDM_DC_CTRL_DCCONFIG0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
 
#define PDM_DC_CTRL_DCCONFIG1_MASK   (0xCU)
 
#define PDM_DC_CTRL_DCCONFIG1_SHIFT   (2U)
 
#define PDM_DC_CTRL_DCCONFIG1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
 
#define PDM_DC_CTRL_DCCONFIG2_MASK   (0x30U)
 
#define PDM_DC_CTRL_DCCONFIG2_SHIFT   (4U)
 
#define PDM_DC_CTRL_DCCONFIG2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
 
#define PDM_DC_CTRL_DCCONFIG3_MASK   (0xC0U)
 
#define PDM_DC_CTRL_DCCONFIG3_SHIFT   (6U)
 
#define PDM_DC_CTRL_DCCONFIG3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
 
#define PDM_DC_CTRL_DCCONFIG4_MASK   (0x300U)
 
#define PDM_DC_CTRL_DCCONFIG4_SHIFT   (8U)
 
#define PDM_DC_CTRL_DCCONFIG4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)
 
#define PDM_DC_CTRL_DCCONFIG5_MASK   (0xC00U)
 
#define PDM_DC_CTRL_DCCONFIG5_SHIFT   (10U)
 
#define PDM_DC_CTRL_DCCONFIG5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)
 
#define PDM_DC_CTRL_DCCONFIG6_MASK   (0x3000U)
 
#define PDM_DC_CTRL_DCCONFIG6_SHIFT   (12U)
 
#define PDM_DC_CTRL_DCCONFIG6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)
 
#define PDM_DC_CTRL_DCCONFIG7_MASK   (0xC000U)
 
#define PDM_DC_CTRL_DCCONFIG7_SHIFT   (14U)
 
#define PDM_DC_CTRL_DCCONFIG7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
 

RANGE_CTRL - PDM Range Control register

#define PDM_RANGE_CTRL_RANGEADJ0_MASK   (0xFU)
 
#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT   (0U)
 
#define PDM_RANGE_CTRL_RANGEADJ0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ1_MASK   (0xF0U)
 
#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT   (4U)
 
#define PDM_RANGE_CTRL_RANGEADJ1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ2_MASK   (0xF00U)
 
#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT   (8U)
 
#define PDM_RANGE_CTRL_RANGEADJ2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ3_MASK   (0xF000U)
 
#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT   (12U)
 
#define PDM_RANGE_CTRL_RANGEADJ3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ4_MASK   (0xF0000U)
 
#define PDM_RANGE_CTRL_RANGEADJ4_SHIFT   (16U)
 
#define PDM_RANGE_CTRL_RANGEADJ4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ5_MASK   (0xF00000U)
 
#define PDM_RANGE_CTRL_RANGEADJ5_SHIFT   (20U)
 
#define PDM_RANGE_CTRL_RANGEADJ5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ6_MASK   (0xF000000U)
 
#define PDM_RANGE_CTRL_RANGEADJ6_SHIFT   (24U)
 
#define PDM_RANGE_CTRL_RANGEADJ6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ7_MASK   (0xF0000000U)
 
#define PDM_RANGE_CTRL_RANGEADJ7_SHIFT   (28U)
 
#define PDM_RANGE_CTRL_RANGEADJ7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
 

RANGE_STAT - PDM Range Status register

#define PDM_RANGE_STAT_RANGEOVF0_MASK   (0x1U)
 
#define PDM_RANGE_STAT_RANGEOVF0_SHIFT   (0U)
 
#define PDM_RANGE_STAT_RANGEOVF0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF1_MASK   (0x2U)
 
#define PDM_RANGE_STAT_RANGEOVF1_SHIFT   (1U)
 
#define PDM_RANGE_STAT_RANGEOVF1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF2_MASK   (0x4U)
 
#define PDM_RANGE_STAT_RANGEOVF2_SHIFT   (2U)
 
#define PDM_RANGE_STAT_RANGEOVF2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF3_MASK   (0x8U)
 
#define PDM_RANGE_STAT_RANGEOVF3_SHIFT   (3U)
 
#define PDM_RANGE_STAT_RANGEOVF3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF4_MASK   (0x10U)
 
#define PDM_RANGE_STAT_RANGEOVF4_SHIFT   (4U)
 
#define PDM_RANGE_STAT_RANGEOVF4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF5_MASK   (0x20U)
 
#define PDM_RANGE_STAT_RANGEOVF5_SHIFT   (5U)
 
#define PDM_RANGE_STAT_RANGEOVF5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF6_MASK   (0x40U)
 
#define PDM_RANGE_STAT_RANGEOVF6_SHIFT   (6U)
 
#define PDM_RANGE_STAT_RANGEOVF6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF7_MASK   (0x80U)
 
#define PDM_RANGE_STAT_RANGEOVF7_SHIFT   (7U)
 
#define PDM_RANGE_STAT_RANGEOVF7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF0_MASK   (0x10000U)
 
#define PDM_RANGE_STAT_RANGEUNF0_SHIFT   (16U)
 
#define PDM_RANGE_STAT_RANGEUNF0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF1_MASK   (0x20000U)
 
#define PDM_RANGE_STAT_RANGEUNF1_SHIFT   (17U)
 
#define PDM_RANGE_STAT_RANGEUNF1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF2_MASK   (0x40000U)
 
#define PDM_RANGE_STAT_RANGEUNF2_SHIFT   (18U)
 
#define PDM_RANGE_STAT_RANGEUNF2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF3_MASK   (0x80000U)
 
#define PDM_RANGE_STAT_RANGEUNF3_SHIFT   (19U)
 
#define PDM_RANGE_STAT_RANGEUNF3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF4_MASK   (0x100000U)
 
#define PDM_RANGE_STAT_RANGEUNF4_SHIFT   (20U)
 
#define PDM_RANGE_STAT_RANGEUNF4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF5_MASK   (0x200000U)
 
#define PDM_RANGE_STAT_RANGEUNF5_SHIFT   (21U)
 
#define PDM_RANGE_STAT_RANGEUNF5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF6_MASK   (0x400000U)
 
#define PDM_RANGE_STAT_RANGEUNF6_SHIFT   (22U)
 
#define PDM_RANGE_STAT_RANGEUNF6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF7_MASK   (0x800000U)
 
#define PDM_RANGE_STAT_RANGEUNF7_SHIFT   (23U)
 
#define PDM_RANGE_STAT_RANGEUNF7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
 

VAD0_CTRL_1 - Voice Activity Detector 0 Control register

#define PDM_VAD0_CTRL_1_VADEN_MASK   (0x1U)
 
#define PDM_VAD0_CTRL_1_VADEN_SHIFT   (0U)
 
#define PDM_VAD0_CTRL_1_VADEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)
 
#define PDM_VAD0_CTRL_1_VADRST_MASK   (0x2U)
 
#define PDM_VAD0_CTRL_1_VADRST_SHIFT   (1U)
 
#define PDM_VAD0_CTRL_1_VADRST(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)
 
#define PDM_VAD0_CTRL_1_VADIE_MASK   (0x4U)
 
#define PDM_VAD0_CTRL_1_VADIE_SHIFT   (2U)
 
#define PDM_VAD0_CTRL_1_VADIE(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)
 
#define PDM_VAD0_CTRL_1_VADERIE_MASK   (0x8U)
 
#define PDM_VAD0_CTRL_1_VADERIE_SHIFT   (3U)
 
#define PDM_VAD0_CTRL_1_VADERIE(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)
 
#define PDM_VAD0_CTRL_1_VADST10_MASK   (0x10U)
 
#define PDM_VAD0_CTRL_1_VADST10_SHIFT   (4U)
 
#define PDM_VAD0_CTRL_1_VADST10(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)
 
#define PDM_VAD0_CTRL_1_VADINITT_MASK   (0x1F00U)
 
#define PDM_VAD0_CTRL_1_VADINITT_SHIFT   (8U)
 
#define PDM_VAD0_CTRL_1_VADINITT(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)
 
#define PDM_VAD0_CTRL_1_VADCICOSR_MASK   (0xF0000U)
 
#define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT   (16U)
 
#define PDM_VAD0_CTRL_1_VADCICOSR(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)
 
#define PDM_VAD0_CTRL_1_VADCHSEL_MASK   (0x7000000U)
 
#define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT   (24U)
 
#define PDM_VAD0_CTRL_1_VADCHSEL(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
 

VAD0_CTRL_2 - Voice Activity Detector 0 Control register

#define PDM_VAD0_CTRL_2_VADHPF_MASK   (0x3U)
 
#define PDM_VAD0_CTRL_2_VADHPF_SHIFT   (0U)
 
#define PDM_VAD0_CTRL_2_VADHPF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)
 
#define PDM_VAD0_CTRL_2_VADINPGAIN_MASK   (0xF00U)
 
#define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT   (8U)
 
#define PDM_VAD0_CTRL_2_VADINPGAIN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)
 
#define PDM_VAD0_CTRL_2_VADFRAMET_MASK   (0x3F0000U)
 
#define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT   (16U)
 
#define PDM_VAD0_CTRL_2_VADFRAMET(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)
 
#define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK   (0x10000000U)
 
#define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT   (28U)
 
#define PDM_VAD0_CTRL_2_VADFOUTDIS(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)
 
#define PDM_VAD0_CTRL_2_VADPREFEN_MASK   (0x40000000U)
 
#define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT   (30U)
 
#define PDM_VAD0_CTRL_2_VADPREFEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)
 
#define PDM_VAD0_CTRL_2_VADFRENDIS_MASK   (0x80000000U)
 
#define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT   (31U)
 
#define PDM_VAD0_CTRL_2_VADFRENDIS(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
 

VAD0_STAT - Voice Activity Detector 0 Status register

#define PDM_VAD0_STAT_VADIF_MASK   (0x1U)
 
#define PDM_VAD0_STAT_VADIF_SHIFT   (0U)
 
#define PDM_VAD0_STAT_VADIF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)
 
#define PDM_VAD0_STAT_VADEF_MASK   (0x8000U)
 
#define PDM_VAD0_STAT_VADEF_SHIFT   (15U)
 
#define PDM_VAD0_STAT_VADEF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)
 
#define PDM_VAD0_STAT_VADINSATF_MASK   (0x10000U)
 
#define PDM_VAD0_STAT_VADINSATF_SHIFT   (16U)
 
#define PDM_VAD0_STAT_VADINSATF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)
 
#define PDM_VAD0_STAT_VADINITF_MASK   (0x80000000U)
 
#define PDM_VAD0_STAT_VADINITF_SHIFT   (31U)
 
#define PDM_VAD0_STAT_VADINITF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
 

VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration

#define PDM_VAD0_SCONFIG_VADSGAIN_MASK   (0xFU)
 
#define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT   (0U)
 
#define PDM_VAD0_SCONFIG_VADSGAIN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)
 
#define PDM_VAD0_SCONFIG_VADSMAXEN_MASK   (0x40000000U)
 
#define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT   (30U)
 
#define PDM_VAD0_SCONFIG_VADSMAXEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)
 
#define PDM_VAD0_SCONFIG_VADSFILEN_MASK   (0x80000000U)
 
#define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT   (31U)
 
#define PDM_VAD0_SCONFIG_VADSFILEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
 

VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration

#define PDM_VAD0_NCONFIG_VADNGAIN_MASK   (0xFU)
 
#define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT   (0U)
 
#define PDM_VAD0_NCONFIG_VADNGAIN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)
 
#define PDM_VAD0_NCONFIG_VADNFILADJ_MASK   (0x1F00U)
 
#define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT   (8U)
 
#define PDM_VAD0_NCONFIG_VADNFILADJ(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)
 
#define PDM_VAD0_NCONFIG_VADNOREN_MASK   (0x10000000U)
 
#define PDM_VAD0_NCONFIG_VADNOREN_SHIFT   (28U)
 
#define PDM_VAD0_NCONFIG_VADNOREN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)
 
#define PDM_VAD0_NCONFIG_VADNDECEN_MASK   (0x20000000U)
 
#define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT   (29U)
 
#define PDM_VAD0_NCONFIG_VADNDECEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)
 
#define PDM_VAD0_NCONFIG_VADNMINEN_MASK   (0x40000000U)
 
#define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT   (30U)
 
#define PDM_VAD0_NCONFIG_VADNMINEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)
 
#define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK   (0x80000000U)
 
#define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT   (31U)
 
#define PDM_VAD0_NCONFIG_VADNFILAUTO(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
 

VAD0_NDATA - Voice Activity Detector 0 Noise Data

#define PDM_VAD0_NDATA_VADNDATA_MASK   (0xFFFFU)
 
#define PDM_VAD0_NDATA_VADNDATA_SHIFT   (0U)
 
#define PDM_VAD0_NDATA_VADNDATA(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
 

VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector

#define PDM_VAD0_ZCD_VADZCDEN_MASK   (0x1U)
 
#define PDM_VAD0_ZCD_VADZCDEN_SHIFT   (0U)
 
#define PDM_VAD0_ZCD_VADZCDEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)
 
#define PDM_VAD0_ZCD_VADZCDAUTO_MASK   (0x4U)
 
#define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT   (2U)
 
#define PDM_VAD0_ZCD_VADZCDAUTO(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)
 
#define PDM_VAD0_ZCD_VADZCDAND_MASK   (0x10U)
 
#define PDM_VAD0_ZCD_VADZCDAND_SHIFT   (4U)
 
#define PDM_VAD0_ZCD_VADZCDAND(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
 
#define PDM_VAD0_ZCD_VADZCDADJ_MASK   (0xF00U)
 
#define PDM_VAD0_ZCD_VADZCDADJ_SHIFT   (8U)
 
#define PDM_VAD0_ZCD_VADZCDADJ(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)
 
#define PDM_VAD0_ZCD_VADZCDTH_MASK   (0x3FF0000U)
 
#define PDM_VAD0_ZCD_VADZCDTH_SHIFT   (16U)
 
#define PDM_VAD0_ZCD_VADZCDTH(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
 

CTRL_1 - PDM Control register 1

#define PDM_CTRL_1_CH0EN_MASK   (0x1U)
 
#define PDM_CTRL_1_CH0EN_SHIFT   (0U)
 
#define PDM_CTRL_1_CH0EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
 
#define PDM_CTRL_1_CH1EN_MASK   (0x2U)
 
#define PDM_CTRL_1_CH1EN_SHIFT   (1U)
 
#define PDM_CTRL_1_CH1EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
 
#define PDM_CTRL_1_CH2EN_MASK   (0x4U)
 
#define PDM_CTRL_1_CH2EN_SHIFT   (2U)
 
#define PDM_CTRL_1_CH2EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
 
#define PDM_CTRL_1_CH3EN_MASK   (0x8U)
 
#define PDM_CTRL_1_CH3EN_SHIFT   (3U)
 
#define PDM_CTRL_1_CH3EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
 
#define PDM_CTRL_1_CH4EN_MASK   (0x10U)
 
#define PDM_CTRL_1_CH4EN_SHIFT   (4U)
 
#define PDM_CTRL_1_CH4EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)
 
#define PDM_CTRL_1_CH5EN_MASK   (0x20U)
 
#define PDM_CTRL_1_CH5EN_SHIFT   (5U)
 
#define PDM_CTRL_1_CH5EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)
 
#define PDM_CTRL_1_CH6EN_MASK   (0x40U)
 
#define PDM_CTRL_1_CH6EN_SHIFT   (6U)
 
#define PDM_CTRL_1_CH6EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)
 
#define PDM_CTRL_1_CH7EN_MASK   (0x80U)
 
#define PDM_CTRL_1_CH7EN_SHIFT   (7U)
 
#define PDM_CTRL_1_CH7EN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)
 
#define PDM_CTRL_1_ERREN_MASK   (0x800000U)
 
#define PDM_CTRL_1_ERREN_SHIFT   (23U)
 
#define PDM_CTRL_1_ERREN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
 
#define PDM_CTRL_1_DISEL_MASK   (0x3000000U)
 
#define PDM_CTRL_1_DISEL_SHIFT   (24U)
 
#define PDM_CTRL_1_DISEL(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
 
#define PDM_CTRL_1_DBGE_MASK   (0x4000000U)
 
#define PDM_CTRL_1_DBGE_SHIFT   (26U)
 
#define PDM_CTRL_1_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
 
#define PDM_CTRL_1_SRES_MASK   (0x8000000U)
 
#define PDM_CTRL_1_SRES_SHIFT   (27U)
 
#define PDM_CTRL_1_SRES(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
 
#define PDM_CTRL_1_DBG_MASK   (0x10000000U)
 
#define PDM_CTRL_1_DBG_SHIFT   (28U)
 
#define PDM_CTRL_1_DBG(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
 
#define PDM_CTRL_1_PDMIEN_MASK   (0x20000000U)
 
#define PDM_CTRL_1_PDMIEN_SHIFT   (29U)
 
#define PDM_CTRL_1_PDMIEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
 
#define PDM_CTRL_1_DOZEN_MASK   (0x40000000U)
 
#define PDM_CTRL_1_DOZEN_SHIFT   (30U)
 
#define PDM_CTRL_1_DOZEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
 
#define PDM_CTRL_1_MDIS_MASK   (0x80000000U)
 
#define PDM_CTRL_1_MDIS_SHIFT   (31U)
 
#define PDM_CTRL_1_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
 

CTRL_2 - PDM Control register 2

#define PDM_CTRL_2_CLKDIV_MASK   (0xFFU)
 
#define PDM_CTRL_2_CLKDIV_SHIFT   (0U)
 
#define PDM_CTRL_2_CLKDIV(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
 
#define PDM_CTRL_2_CICOSR_MASK   (0xF0000U)
 
#define PDM_CTRL_2_CICOSR_SHIFT   (16U)
 
#define PDM_CTRL_2_CICOSR(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
 
#define PDM_CTRL_2_QSEL_MASK   (0xE000000U)
 
#define PDM_CTRL_2_QSEL_SHIFT   (25U)
 
#define PDM_CTRL_2_QSEL(x)   (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
 

STAT - PDM Status register

#define PDM_STAT_CH0F_MASK   (0x1U)
 
#define PDM_STAT_CH0F_SHIFT   (0U)
 
#define PDM_STAT_CH0F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
 
#define PDM_STAT_CH1F_MASK   (0x2U)
 
#define PDM_STAT_CH1F_SHIFT   (1U)
 
#define PDM_STAT_CH1F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
 
#define PDM_STAT_CH2F_MASK   (0x4U)
 
#define PDM_STAT_CH2F_SHIFT   (2U)
 
#define PDM_STAT_CH2F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
 
#define PDM_STAT_CH3F_MASK   (0x8U)
 
#define PDM_STAT_CH3F_SHIFT   (3U)
 
#define PDM_STAT_CH3F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
 
#define PDM_STAT_CH4F_MASK   (0x10U)
 
#define PDM_STAT_CH4F_SHIFT   (4U)
 
#define PDM_STAT_CH4F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)
 
#define PDM_STAT_CH5F_MASK   (0x20U)
 
#define PDM_STAT_CH5F_SHIFT   (5U)
 
#define PDM_STAT_CH5F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)
 
#define PDM_STAT_CH6F_MASK   (0x40U)
 
#define PDM_STAT_CH6F_SHIFT   (6U)
 
#define PDM_STAT_CH6F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)
 
#define PDM_STAT_CH7F_MASK   (0x80U)
 
#define PDM_STAT_CH7F_SHIFT   (7U)
 
#define PDM_STAT_CH7F(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)
 
#define PDM_STAT_LOWFREQF_MASK   (0x20000000U)
 
#define PDM_STAT_LOWFREQF_SHIFT   (29U)
 
#define PDM_STAT_LOWFREQF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)
 
#define PDM_STAT_FIR_RDY_MASK   (0x40000000U)
 
#define PDM_STAT_FIR_RDY_SHIFT   (30U)
 
#define PDM_STAT_FIR_RDY(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)
 
#define PDM_STAT_BSY_FIL_MASK   (0x80000000U)
 
#define PDM_STAT_BSY_FIL_SHIFT   (31U)
 
#define PDM_STAT_BSY_FIL(x)   (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
 

FIFO_CTRL - PDM FIFO Control register

#define PDM_FIFO_CTRL_FIFOWMK_MASK   (0x7U)
 
#define PDM_FIFO_CTRL_FIFOWMK_SHIFT   (0U)
 
#define PDM_FIFO_CTRL_FIFOWMK(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
 

FIFO_STAT - PDM FIFO Status register

#define PDM_FIFO_STAT_FIFOOVF0_MASK   (0x1U)
 
#define PDM_FIFO_STAT_FIFOOVF0_SHIFT   (0U)
 
#define PDM_FIFO_STAT_FIFOOVF0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF1_MASK   (0x2U)
 
#define PDM_FIFO_STAT_FIFOOVF1_SHIFT   (1U)
 
#define PDM_FIFO_STAT_FIFOOVF1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF2_MASK   (0x4U)
 
#define PDM_FIFO_STAT_FIFOOVF2_SHIFT   (2U)
 
#define PDM_FIFO_STAT_FIFOOVF2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF3_MASK   (0x8U)
 
#define PDM_FIFO_STAT_FIFOOVF3_SHIFT   (3U)
 
#define PDM_FIFO_STAT_FIFOOVF3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF4_MASK   (0x10U)
 
#define PDM_FIFO_STAT_FIFOOVF4_SHIFT   (4U)
 
#define PDM_FIFO_STAT_FIFOOVF4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF5_MASK   (0x20U)
 
#define PDM_FIFO_STAT_FIFOOVF5_SHIFT   (5U)
 
#define PDM_FIFO_STAT_FIFOOVF5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF6_MASK   (0x40U)
 
#define PDM_FIFO_STAT_FIFOOVF6_SHIFT   (6U)
 
#define PDM_FIFO_STAT_FIFOOVF6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
 
#define PDM_FIFO_STAT_FIFOOVF7_MASK   (0x80U)
 
#define PDM_FIFO_STAT_FIFOOVF7_SHIFT   (7U)
 
#define PDM_FIFO_STAT_FIFOOVF7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)
 
#define PDM_FIFO_STAT_FIFOUND0_MASK   (0x100U)
 
#define PDM_FIFO_STAT_FIFOUND0_SHIFT   (8U)
 
#define PDM_FIFO_STAT_FIFOUND0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
 
#define PDM_FIFO_STAT_FIFOUND1_MASK   (0x200U)
 
#define PDM_FIFO_STAT_FIFOUND1_SHIFT   (9U)
 
#define PDM_FIFO_STAT_FIFOUND1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
 
#define PDM_FIFO_STAT_FIFOUND2_MASK   (0x400U)
 
#define PDM_FIFO_STAT_FIFOUND2_SHIFT   (10U)
 
#define PDM_FIFO_STAT_FIFOUND2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
 
#define PDM_FIFO_STAT_FIFOUND3_MASK   (0x800U)
 
#define PDM_FIFO_STAT_FIFOUND3_SHIFT   (11U)
 
#define PDM_FIFO_STAT_FIFOUND3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
 
#define PDM_FIFO_STAT_FIFOUND4_MASK   (0x1000U)
 
#define PDM_FIFO_STAT_FIFOUND4_SHIFT   (12U)
 
#define PDM_FIFO_STAT_FIFOUND4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)
 
#define PDM_FIFO_STAT_FIFOUND5_MASK   (0x2000U)
 
#define PDM_FIFO_STAT_FIFOUND5_SHIFT   (13U)
 
#define PDM_FIFO_STAT_FIFOUND5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)
 
#define PDM_FIFO_STAT_FIFOUND6_MASK   (0x4000U)
 
#define PDM_FIFO_STAT_FIFOUND6_SHIFT   (14U)
 
#define PDM_FIFO_STAT_FIFOUND6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)
 
#define PDM_FIFO_STAT_FIFOUND7_MASK   (0x8000U)
 
#define PDM_FIFO_STAT_FIFOUND7_SHIFT   (15U)
 
#define PDM_FIFO_STAT_FIFOUND7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
 

DATACH - PDM Output Result Register

#define PDM_DATACH_DATA_MASK   (0xFFFFFFFFU)
 
#define PDM_DATACH_DATA_SHIFT   (0U)
 
#define PDM_DATACH_DATA(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
 

DC_CTRL - PDM DC Remover Control register

#define PDM_DC_CTRL_DCCONFIG0_MASK   (0x3U)
 
#define PDM_DC_CTRL_DCCONFIG0_SHIFT   (0U)
 
#define PDM_DC_CTRL_DCCONFIG0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
 
#define PDM_DC_CTRL_DCCONFIG1_MASK   (0xCU)
 
#define PDM_DC_CTRL_DCCONFIG1_SHIFT   (2U)
 
#define PDM_DC_CTRL_DCCONFIG1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
 
#define PDM_DC_CTRL_DCCONFIG2_MASK   (0x30U)
 
#define PDM_DC_CTRL_DCCONFIG2_SHIFT   (4U)
 
#define PDM_DC_CTRL_DCCONFIG2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
 
#define PDM_DC_CTRL_DCCONFIG3_MASK   (0xC0U)
 
#define PDM_DC_CTRL_DCCONFIG3_SHIFT   (6U)
 
#define PDM_DC_CTRL_DCCONFIG3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
 
#define PDM_DC_CTRL_DCCONFIG4_MASK   (0x300U)
 
#define PDM_DC_CTRL_DCCONFIG4_SHIFT   (8U)
 
#define PDM_DC_CTRL_DCCONFIG4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)
 
#define PDM_DC_CTRL_DCCONFIG5_MASK   (0xC00U)
 
#define PDM_DC_CTRL_DCCONFIG5_SHIFT   (10U)
 
#define PDM_DC_CTRL_DCCONFIG5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)
 
#define PDM_DC_CTRL_DCCONFIG6_MASK   (0x3000U)
 
#define PDM_DC_CTRL_DCCONFIG6_SHIFT   (12U)
 
#define PDM_DC_CTRL_DCCONFIG6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)
 
#define PDM_DC_CTRL_DCCONFIG7_MASK   (0xC000U)
 
#define PDM_DC_CTRL_DCCONFIG7_SHIFT   (14U)
 
#define PDM_DC_CTRL_DCCONFIG7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
 

RANGE_CTRL - PDM Range Control register

#define PDM_RANGE_CTRL_RANGEADJ0_MASK   (0xFU)
 
#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT   (0U)
 
#define PDM_RANGE_CTRL_RANGEADJ0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ1_MASK   (0xF0U)
 
#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT   (4U)
 
#define PDM_RANGE_CTRL_RANGEADJ1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ2_MASK   (0xF00U)
 
#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT   (8U)
 
#define PDM_RANGE_CTRL_RANGEADJ2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ3_MASK   (0xF000U)
 
#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT   (12U)
 
#define PDM_RANGE_CTRL_RANGEADJ3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ4_MASK   (0xF0000U)
 
#define PDM_RANGE_CTRL_RANGEADJ4_SHIFT   (16U)
 
#define PDM_RANGE_CTRL_RANGEADJ4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ5_MASK   (0xF00000U)
 
#define PDM_RANGE_CTRL_RANGEADJ5_SHIFT   (20U)
 
#define PDM_RANGE_CTRL_RANGEADJ5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ6_MASK   (0xF000000U)
 
#define PDM_RANGE_CTRL_RANGEADJ6_SHIFT   (24U)
 
#define PDM_RANGE_CTRL_RANGEADJ6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)
 
#define PDM_RANGE_CTRL_RANGEADJ7_MASK   (0xF0000000U)
 
#define PDM_RANGE_CTRL_RANGEADJ7_SHIFT   (28U)
 
#define PDM_RANGE_CTRL_RANGEADJ7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
 

RANGE_STAT - PDM Range Status register

#define PDM_RANGE_STAT_RANGEOVF0_MASK   (0x1U)
 
#define PDM_RANGE_STAT_RANGEOVF0_SHIFT   (0U)
 
#define PDM_RANGE_STAT_RANGEOVF0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF1_MASK   (0x2U)
 
#define PDM_RANGE_STAT_RANGEOVF1_SHIFT   (1U)
 
#define PDM_RANGE_STAT_RANGEOVF1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF2_MASK   (0x4U)
 
#define PDM_RANGE_STAT_RANGEOVF2_SHIFT   (2U)
 
#define PDM_RANGE_STAT_RANGEOVF2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF3_MASK   (0x8U)
 
#define PDM_RANGE_STAT_RANGEOVF3_SHIFT   (3U)
 
#define PDM_RANGE_STAT_RANGEOVF3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF4_MASK   (0x10U)
 
#define PDM_RANGE_STAT_RANGEOVF4_SHIFT   (4U)
 
#define PDM_RANGE_STAT_RANGEOVF4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF5_MASK   (0x20U)
 
#define PDM_RANGE_STAT_RANGEOVF5_SHIFT   (5U)
 
#define PDM_RANGE_STAT_RANGEOVF5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF6_MASK   (0x40U)
 
#define PDM_RANGE_STAT_RANGEOVF6_SHIFT   (6U)
 
#define PDM_RANGE_STAT_RANGEOVF6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)
 
#define PDM_RANGE_STAT_RANGEOVF7_MASK   (0x80U)
 
#define PDM_RANGE_STAT_RANGEOVF7_SHIFT   (7U)
 
#define PDM_RANGE_STAT_RANGEOVF7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF0_MASK   (0x10000U)
 
#define PDM_RANGE_STAT_RANGEUNF0_SHIFT   (16U)
 
#define PDM_RANGE_STAT_RANGEUNF0(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF1_MASK   (0x20000U)
 
#define PDM_RANGE_STAT_RANGEUNF1_SHIFT   (17U)
 
#define PDM_RANGE_STAT_RANGEUNF1(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF2_MASK   (0x40000U)
 
#define PDM_RANGE_STAT_RANGEUNF2_SHIFT   (18U)
 
#define PDM_RANGE_STAT_RANGEUNF2(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF3_MASK   (0x80000U)
 
#define PDM_RANGE_STAT_RANGEUNF3_SHIFT   (19U)
 
#define PDM_RANGE_STAT_RANGEUNF3(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF4_MASK   (0x100000U)
 
#define PDM_RANGE_STAT_RANGEUNF4_SHIFT   (20U)
 
#define PDM_RANGE_STAT_RANGEUNF4(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF5_MASK   (0x200000U)
 
#define PDM_RANGE_STAT_RANGEUNF5_SHIFT   (21U)
 
#define PDM_RANGE_STAT_RANGEUNF5(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF6_MASK   (0x400000U)
 
#define PDM_RANGE_STAT_RANGEUNF6_SHIFT   (22U)
 
#define PDM_RANGE_STAT_RANGEUNF6(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)
 
#define PDM_RANGE_STAT_RANGEUNF7_MASK   (0x800000U)
 
#define PDM_RANGE_STAT_RANGEUNF7_SHIFT   (23U)
 
#define PDM_RANGE_STAT_RANGEUNF7(x)   (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
 

VAD0_CTRL_1 - Voice Activity Detector 0 Control register

#define PDM_VAD0_CTRL_1_VADEN_MASK   (0x1U)
 
#define PDM_VAD0_CTRL_1_VADEN_SHIFT   (0U)
 
#define PDM_VAD0_CTRL_1_VADEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)
 
#define PDM_VAD0_CTRL_1_VADRST_MASK   (0x2U)
 
#define PDM_VAD0_CTRL_1_VADRST_SHIFT   (1U)
 
#define PDM_VAD0_CTRL_1_VADRST(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)
 
#define PDM_VAD0_CTRL_1_VADIE_MASK   (0x4U)
 
#define PDM_VAD0_CTRL_1_VADIE_SHIFT   (2U)
 
#define PDM_VAD0_CTRL_1_VADIE(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)
 
#define PDM_VAD0_CTRL_1_VADERIE_MASK   (0x8U)
 
#define PDM_VAD0_CTRL_1_VADERIE_SHIFT   (3U)
 
#define PDM_VAD0_CTRL_1_VADERIE(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)
 
#define PDM_VAD0_CTRL_1_VADST10_MASK   (0x10U)
 
#define PDM_VAD0_CTRL_1_VADST10_SHIFT   (4U)
 
#define PDM_VAD0_CTRL_1_VADST10(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)
 
#define PDM_VAD0_CTRL_1_VADINITT_MASK   (0x1F00U)
 
#define PDM_VAD0_CTRL_1_VADINITT_SHIFT   (8U)
 
#define PDM_VAD0_CTRL_1_VADINITT(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)
 
#define PDM_VAD0_CTRL_1_VADCICOSR_MASK   (0xF0000U)
 
#define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT   (16U)
 
#define PDM_VAD0_CTRL_1_VADCICOSR(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)
 
#define PDM_VAD0_CTRL_1_VADCHSEL_MASK   (0x7000000U)
 
#define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT   (24U)
 
#define PDM_VAD0_CTRL_1_VADCHSEL(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
 

VAD0_CTRL_2 - Voice Activity Detector 0 Control register

#define PDM_VAD0_CTRL_2_VADHPF_MASK   (0x3U)
 
#define PDM_VAD0_CTRL_2_VADHPF_SHIFT   (0U)
 
#define PDM_VAD0_CTRL_2_VADHPF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)
 
#define PDM_VAD0_CTRL_2_VADINPGAIN_MASK   (0xF00U)
 
#define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT   (8U)
 
#define PDM_VAD0_CTRL_2_VADINPGAIN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)
 
#define PDM_VAD0_CTRL_2_VADFRAMET_MASK   (0x3F0000U)
 
#define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT   (16U)
 
#define PDM_VAD0_CTRL_2_VADFRAMET(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)
 
#define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK   (0x10000000U)
 
#define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT   (28U)
 
#define PDM_VAD0_CTRL_2_VADFOUTDIS(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)
 
#define PDM_VAD0_CTRL_2_VADPREFEN_MASK   (0x40000000U)
 
#define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT   (30U)
 
#define PDM_VAD0_CTRL_2_VADPREFEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)
 
#define PDM_VAD0_CTRL_2_VADFRENDIS_MASK   (0x80000000U)
 
#define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT   (31U)
 
#define PDM_VAD0_CTRL_2_VADFRENDIS(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
 

VAD0_STAT - Voice Activity Detector 0 Status register

#define PDM_VAD0_STAT_VADIF_MASK   (0x1U)
 
#define PDM_VAD0_STAT_VADIF_SHIFT   (0U)
 
#define PDM_VAD0_STAT_VADIF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)
 
#define PDM_VAD0_STAT_VADEF_MASK   (0x8000U)
 
#define PDM_VAD0_STAT_VADEF_SHIFT   (15U)
 
#define PDM_VAD0_STAT_VADEF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)
 
#define PDM_VAD0_STAT_VADINSATF_MASK   (0x10000U)
 
#define PDM_VAD0_STAT_VADINSATF_SHIFT   (16U)
 
#define PDM_VAD0_STAT_VADINSATF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)
 
#define PDM_VAD0_STAT_VADINITF_MASK   (0x80000000U)
 
#define PDM_VAD0_STAT_VADINITF_SHIFT   (31U)
 
#define PDM_VAD0_STAT_VADINITF(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
 

VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration

#define PDM_VAD0_SCONFIG_VADSGAIN_MASK   (0xFU)
 
#define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT   (0U)
 
#define PDM_VAD0_SCONFIG_VADSGAIN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)
 
#define PDM_VAD0_SCONFIG_VADSMAXEN_MASK   (0x40000000U)
 
#define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT   (30U)
 
#define PDM_VAD0_SCONFIG_VADSMAXEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)
 
#define PDM_VAD0_SCONFIG_VADSFILEN_MASK   (0x80000000U)
 
#define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT   (31U)
 
#define PDM_VAD0_SCONFIG_VADSFILEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
 

VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration

#define PDM_VAD0_NCONFIG_VADNGAIN_MASK   (0xFU)
 
#define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT   (0U)
 
#define PDM_VAD0_NCONFIG_VADNGAIN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)
 
#define PDM_VAD0_NCONFIG_VADNFILADJ_MASK   (0x1F00U)
 
#define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT   (8U)
 
#define PDM_VAD0_NCONFIG_VADNFILADJ(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)
 
#define PDM_VAD0_NCONFIG_VADNOREN_MASK   (0x10000000U)
 
#define PDM_VAD0_NCONFIG_VADNOREN_SHIFT   (28U)
 
#define PDM_VAD0_NCONFIG_VADNOREN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)
 
#define PDM_VAD0_NCONFIG_VADNDECEN_MASK   (0x20000000U)
 
#define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT   (29U)
 
#define PDM_VAD0_NCONFIG_VADNDECEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)
 
#define PDM_VAD0_NCONFIG_VADNMINEN_MASK   (0x40000000U)
 
#define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT   (30U)
 
#define PDM_VAD0_NCONFIG_VADNMINEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)
 
#define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK   (0x80000000U)
 
#define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT   (31U)
 
#define PDM_VAD0_NCONFIG_VADNFILAUTO(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
 

VAD0_NDATA - Voice Activity Detector 0 Noise Data

#define PDM_VAD0_NDATA_VADNDATA_MASK   (0xFFFFU)
 
#define PDM_VAD0_NDATA_VADNDATA_SHIFT   (0U)
 
#define PDM_VAD0_NDATA_VADNDATA(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
 

VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector

#define PDM_VAD0_ZCD_VADZCDEN_MASK   (0x1U)
 
#define PDM_VAD0_ZCD_VADZCDEN_SHIFT   (0U)
 
#define PDM_VAD0_ZCD_VADZCDEN(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)
 
#define PDM_VAD0_ZCD_VADZCDAUTO_MASK   (0x4U)
 
#define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT   (2U)
 
#define PDM_VAD0_ZCD_VADZCDAUTO(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)
 
#define PDM_VAD0_ZCD_VADZCDAND_MASK   (0x10U)
 
#define PDM_VAD0_ZCD_VADZCDAND_SHIFT   (4U)
 
#define PDM_VAD0_ZCD_VADZCDAND(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
 
#define PDM_VAD0_ZCD_VADZCDADJ_MASK   (0xF00U)
 
#define PDM_VAD0_ZCD_VADZCDADJ_SHIFT   (8U)
 
#define PDM_VAD0_ZCD_VADZCDADJ(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)
 
#define PDM_VAD0_ZCD_VADZCDTH_MASK   (0x3FF0000U)
 
#define PDM_VAD0_ZCD_VADZCDTH_SHIFT   (16U)
 
#define PDM_VAD0_ZCD_VADZCDTH(x)   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
 

Detailed Description

Macro Definition Documentation

◆ PDM_CTRL_1_CH0EN [1/2]

#define PDM_CTRL_1_CH0EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)

CH0EN - Channel 0 Enable

◆ PDM_CTRL_1_CH0EN [2/2]

#define PDM_CTRL_1_CH0EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)

CH0EN - Channel 0 Enable

◆ PDM_CTRL_1_CH1EN [1/2]

#define PDM_CTRL_1_CH1EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)

CH1EN - Channel 1 Enable

◆ PDM_CTRL_1_CH1EN [2/2]

#define PDM_CTRL_1_CH1EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)

CH1EN - Channel 1 Enable

◆ PDM_CTRL_1_CH2EN [1/2]

#define PDM_CTRL_1_CH2EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)

CH2EN - Channel 2 Enable

◆ PDM_CTRL_1_CH2EN [2/2]

#define PDM_CTRL_1_CH2EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)

CH2EN - Channel 2 Enable

◆ PDM_CTRL_1_CH3EN [1/2]

#define PDM_CTRL_1_CH3EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)

CH3EN - Channel 3 Enable

◆ PDM_CTRL_1_CH3EN [2/2]

#define PDM_CTRL_1_CH3EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)

CH3EN - Channel 3 Enable

◆ PDM_CTRL_1_CH4EN [1/2]

#define PDM_CTRL_1_CH4EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)

CH4EN - Channel 4 Enable

◆ PDM_CTRL_1_CH4EN [2/2]

#define PDM_CTRL_1_CH4EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)

CH4EN - Channel 4 Enable

◆ PDM_CTRL_1_CH5EN [1/2]

#define PDM_CTRL_1_CH5EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)

CH5EN - Channel 5 Enable

◆ PDM_CTRL_1_CH5EN [2/2]

#define PDM_CTRL_1_CH5EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)

CH5EN - Channel 5 Enable

◆ PDM_CTRL_1_CH6EN [1/2]

#define PDM_CTRL_1_CH6EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)

CH6EN - Channel 6 Enable

◆ PDM_CTRL_1_CH6EN [2/2]

#define PDM_CTRL_1_CH6EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)

CH6EN - Channel 6 Enable

◆ PDM_CTRL_1_CH7EN [1/2]

#define PDM_CTRL_1_CH7EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)

CH7EN - Channel 7 Enable

◆ PDM_CTRL_1_CH7EN [2/2]

#define PDM_CTRL_1_CH7EN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)

CH7EN - Channel 7 Enable

◆ PDM_CTRL_1_DBG [1/2]

#define PDM_CTRL_1_DBG (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)

DBG - Debug Mode 0b0..Normal Mode 0b1..Debug Mode

◆ PDM_CTRL_1_DBG [2/2]

#define PDM_CTRL_1_DBG (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)

DBG - Debug Mode 0b0..Normal Mode 0b1..Debug Mode

◆ PDM_CTRL_1_DBGE [1/2]

#define PDM_CTRL_1_DBGE (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)

DBGE - Module Enable in Debug 0b0..Disabled after completing the current frame 0b1..Enabled

◆ PDM_CTRL_1_DBGE [2/2]

#define PDM_CTRL_1_DBGE (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)

DBGE - Module Enable in Debug 0b0..Disabled after completing the current frame 0b1..Enabled

◆ PDM_CTRL_1_DISEL [1/2]

#define PDM_CTRL_1_DISEL (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)

DISEL - DMA Interrupt Selection 0b00..DMA and interrupt requests disabled 0b01..DMA requests enabled 0b10..Interrupt requests enabled 0b11..Reserved

◆ PDM_CTRL_1_DISEL [2/2]

#define PDM_CTRL_1_DISEL (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)

DISEL - DMA Interrupt Selection 0b00..DMA and interrupt requests disabled 0b01..DMA requests enabled 0b10..Interrupt requests enabled 0b11..Reserved

◆ PDM_CTRL_1_DOZEN [1/2]

#define PDM_CTRL_1_DOZEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)

DOZEN - DOZE enable

◆ PDM_CTRL_1_DOZEN [2/2]

#define PDM_CTRL_1_DOZEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)

DOZEN - DOZE enable

◆ PDM_CTRL_1_ERREN [1/2]

#define PDM_CTRL_1_ERREN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)

ERREN - Error Interruption Enable 0b0..Error Interrupts disabled 0b1..Error Interrupts enabled

◆ PDM_CTRL_1_ERREN [2/2]

#define PDM_CTRL_1_ERREN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)

ERREN - Error Interruption Enable 0b0..Error Interrupts disabled 0b1..Error Interrupts enabled

◆ PDM_CTRL_1_MDIS [1/2]

#define PDM_CTRL_1_MDIS (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)

MDIS - Module Disable 0b0..Normal Mode 0b1..Disable/Low Leakage Mode

◆ PDM_CTRL_1_MDIS [2/2]

#define PDM_CTRL_1_MDIS (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)

MDIS - Module Disable 0b0..Normal Mode 0b1..Disable/Low Leakage Mode

◆ PDM_CTRL_1_PDMIEN [1/2]

#define PDM_CTRL_1_PDMIEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)

PDMIEN - PDM Enable 0b0..PDM stopped 0b1..PDM operation started

◆ PDM_CTRL_1_PDMIEN [2/2]

#define PDM_CTRL_1_PDMIEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)

PDMIEN - PDM Enable 0b0..PDM stopped 0b1..PDM operation started

◆ PDM_CTRL_1_SRES [1/2]

#define PDM_CTRL_1_SRES (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)

SRES - Software-reset bit 0b0..No action 0b1..Software reset

◆ PDM_CTRL_1_SRES [2/2]

#define PDM_CTRL_1_SRES (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)

SRES - Software-reset bit 0b0..No action 0b1..Software reset

◆ PDM_CTRL_2_CICOSR [1/2]

#define PDM_CTRL_2_CICOSR (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)

CICOSR - CIC Decimation Rate

◆ PDM_CTRL_2_CICOSR [2/2]

#define PDM_CTRL_2_CICOSR (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)

CICOSR - CIC Decimation Rate

◆ PDM_CTRL_2_CLKDIV [1/2]

#define PDM_CTRL_2_CLKDIV (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)

CLKDIV - Clock Divider

◆ PDM_CTRL_2_CLKDIV [2/2]

#define PDM_CTRL_2_CLKDIV (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)

CLKDIV - Clock Divider

◆ PDM_CTRL_2_QSEL [1/2]

#define PDM_CTRL_2_QSEL (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)

QSEL - Quality Mode 0b001..High quality mode 0b000..Medium quality mode 0b111..Low quality mode 0b110..Very low quality 0 mode 0b101..Very low quality 1 mode 0b100..Very low quality 2 mode

◆ PDM_CTRL_2_QSEL [2/2]

#define PDM_CTRL_2_QSEL (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)

QSEL - Quality Mode 0b001..High quality mode 0b000..Medium quality mode 0b111..Low quality mode 0b110..Very low quality 0 mode 0b101..Very low quality 1 mode 0b100..Very low quality 2 mode

◆ PDM_DATACH_DATA [1/2]

#define PDM_DATACH_DATA (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)

DATA - Channel n Data

◆ PDM_DATACH_DATA [2/2]

#define PDM_DATACH_DATA (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)

DATA - Channel n Data

◆ PDM_DC_CTRL_DCCONFIG0 [1/2]

#define PDM_DC_CTRL_DCCONFIG0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)

DCCONFIG0 - Channel 0 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG0 [2/2]

#define PDM_DC_CTRL_DCCONFIG0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)

DCCONFIG0 - Channel 0 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG1 [1/2]

#define PDM_DC_CTRL_DCCONFIG1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)

DCCONFIG1 - Channel 1 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG1 [2/2]

#define PDM_DC_CTRL_DCCONFIG1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)

DCCONFIG1 - Channel 1 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG2 [1/2]

#define PDM_DC_CTRL_DCCONFIG2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)

DCCONFIG2 - Channel 2 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG2 [2/2]

#define PDM_DC_CTRL_DCCONFIG2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)

DCCONFIG2 - Channel 2 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG3 [1/2]

#define PDM_DC_CTRL_DCCONFIG3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)

DCCONFIG3 - Channel 3 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG3 [2/2]

#define PDM_DC_CTRL_DCCONFIG3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)

DCCONFIG3 - Channel 3 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG4 [1/2]

#define PDM_DC_CTRL_DCCONFIG4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)

DCCONFIG4 - Channel 4 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG4 [2/2]

#define PDM_DC_CTRL_DCCONFIG4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)

DCCONFIG4 - Channel 4 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG5 [1/2]

#define PDM_DC_CTRL_DCCONFIG5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)

DCCONFIG5 - Channel 5 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG5 [2/2]

#define PDM_DC_CTRL_DCCONFIG5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)

DCCONFIG5 - Channel 5 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG6 [1/2]

#define PDM_DC_CTRL_DCCONFIG6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)

DCCONFIG6 - Channel 6 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG6 [2/2]

#define PDM_DC_CTRL_DCCONFIG6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)

DCCONFIG6 - Channel 6 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG7 [1/2]

#define PDM_DC_CTRL_DCCONFIG7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)

DCCONFIG7 - Channel 7 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_DC_CTRL_DCCONFIG7 [2/2]

#define PDM_DC_CTRL_DCCONFIG7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)

DCCONFIG7 - Channel 7 DC Remover Configuration 0b11..DC Remover is bypassed 0b00..DC Remover cut-off at 21Hz 0b01..DC Remover cut-off at 83Hz 0b10..DC Remover cut-off at 152Hz

◆ PDM_FIFO_CTRL_FIFOWMK [1/2]

#define PDM_FIFO_CTRL_FIFOWMK (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)

FIFOWMK - FIFO Watermark Control

◆ PDM_FIFO_CTRL_FIFOWMK [2/2]

#define PDM_FIFO_CTRL_FIFOWMK (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)

FIFOWMK - FIFO Watermark Control

◆ PDM_FIFO_STAT_FIFOOVF0 [1/2]

#define PDM_FIFO_STAT_FIFOOVF0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)

FIFOOVF0 - FIFO Overflow Exception flag for Channel 0 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF0 [2/2]

#define PDM_FIFO_STAT_FIFOOVF0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)

FIFOOVF0 - FIFO Overflow Exception flag for Channel 0 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF1 [1/2]

#define PDM_FIFO_STAT_FIFOOVF1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)

FIFOOVF1 - FIFO Overflow Exception flag for Channel 1 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF1 [2/2]

#define PDM_FIFO_STAT_FIFOOVF1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)

FIFOOVF1 - FIFO Overflow Exception flag for Channel 1 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF2 [1/2]

#define PDM_FIFO_STAT_FIFOOVF2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)

FIFOOVF2 - FIFO Overflow Exception flag for Channel 2 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF2 [2/2]

#define PDM_FIFO_STAT_FIFOOVF2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)

FIFOOVF2 - FIFO Overflow Exception flag for Channel 2 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF3 [1/2]

#define PDM_FIFO_STAT_FIFOOVF3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)

FIFOOVF3 - FIFO Overflow Exception flag for Channel 3 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF3 [2/2]

#define PDM_FIFO_STAT_FIFOOVF3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)

FIFOOVF3 - FIFO Overflow Exception flag for Channel 3 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF4 [1/2]

#define PDM_FIFO_STAT_FIFOOVF4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)

FIFOOVF4 - FIFO Overflow Exception flag for Channel 4 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF4 [2/2]

#define PDM_FIFO_STAT_FIFOOVF4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)

FIFOOVF4 - FIFO Overflow Exception flag for Channel 4 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF5 [1/2]

#define PDM_FIFO_STAT_FIFOOVF5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)

FIFOOVF5 - FIFO Overflow Exception flag for Channel 5 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF5 [2/2]

#define PDM_FIFO_STAT_FIFOOVF5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)

FIFOOVF5 - FIFO Overflow Exception flag for Channel 5 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF6 [1/2]

#define PDM_FIFO_STAT_FIFOOVF6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)

FIFOOVF6 - FIFO Overflow Exception flag for Channel 6 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF6 [2/2]

#define PDM_FIFO_STAT_FIFOOVF6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)

FIFOOVF6 - FIFO Overflow Exception flag for Channel 6 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF7 [1/2]

#define PDM_FIFO_STAT_FIFOOVF7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)

FIFOOVF7 - FIFO Overflow Exception flag for Channel 7 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOOVF7 [2/2]

#define PDM_FIFO_STAT_FIFOOVF7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)

FIFOOVF7 - FIFO Overflow Exception flag for Channel 7 0b0..No exception by FIFO overflow 0b1..Exception by FIFO overflow

◆ PDM_FIFO_STAT_FIFOUND0 [1/2]

#define PDM_FIFO_STAT_FIFOUND0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)

FIFOUND0 - FIFO Underflow Exception flag for Channel 0 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND0 [2/2]

#define PDM_FIFO_STAT_FIFOUND0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)

FIFOUND0 - FIFO Underflow Exception flag for Channel 0 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND1 [1/2]

#define PDM_FIFO_STAT_FIFOUND1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)

FIFOUND1 - FIFO Underflow Exception flag for Channel 1 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND1 [2/2]

#define PDM_FIFO_STAT_FIFOUND1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)

FIFOUND1 - FIFO Underflow Exception flag for Channel 1 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND2 [1/2]

#define PDM_FIFO_STAT_FIFOUND2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)

FIFOUND2 - FIFO Underflow Exception flag for Channel 2 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND2 [2/2]

#define PDM_FIFO_STAT_FIFOUND2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)

FIFOUND2 - FIFO Underflow Exception flag for Channel 2 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND3 [1/2]

#define PDM_FIFO_STAT_FIFOUND3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)

FIFOUND3 - FIFO Underflow Exception flag for Channel 3 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND3 [2/2]

#define PDM_FIFO_STAT_FIFOUND3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)

FIFOUND3 - FIFO Underflow Exception flag for Channel 3 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND4 [1/2]

#define PDM_FIFO_STAT_FIFOUND4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)

FIFOUND4 - FIFO Underflow Exception flag for Channel 4 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND4 [2/2]

#define PDM_FIFO_STAT_FIFOUND4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)

FIFOUND4 - FIFO Underflow Exception flag for Channel 4 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND5 [1/2]

#define PDM_FIFO_STAT_FIFOUND5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)

FIFOUND5 - FIFO Underflow Exception flag for Channel 5 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND5 [2/2]

#define PDM_FIFO_STAT_FIFOUND5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)

FIFOUND5 - FIFO Underflow Exception flag for Channel 5 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND6 [1/2]

#define PDM_FIFO_STAT_FIFOUND6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)

FIFOUND6 - FIFO Underflow Exception flag for Channel 6 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND6 [2/2]

#define PDM_FIFO_STAT_FIFOUND6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)

FIFOUND6 - FIFO Underflow Exception flag for Channel 6 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND7 [1/2]

#define PDM_FIFO_STAT_FIFOUND7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)

FIFOUND7 - FIFO Underflow Exception flag for Channel 7 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_FIFO_STAT_FIFOUND7 [2/2]

#define PDM_FIFO_STAT_FIFOUND7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)

FIFOUND7 - FIFO Underflow Exception flag for Channel 7 0b0..No exception by FIFO Underflow 0b1..Exception by FIFO underflow

◆ PDM_RANGE_CTRL_RANGEADJ0 [1/2]

#define PDM_RANGE_CTRL_RANGEADJ0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)

RANGEADJ0 - Channel 0 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ0 [2/2]

#define PDM_RANGE_CTRL_RANGEADJ0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)

RANGEADJ0 - Channel 0 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ1 [1/2]

#define PDM_RANGE_CTRL_RANGEADJ1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)

RANGEADJ1 - Channel 1 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ1 [2/2]

#define PDM_RANGE_CTRL_RANGEADJ1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)

RANGEADJ1 - Channel 1 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ2 [1/2]

#define PDM_RANGE_CTRL_RANGEADJ2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)

RANGEADJ2 - Channel 2 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ2 [2/2]

#define PDM_RANGE_CTRL_RANGEADJ2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)

RANGEADJ2 - Channel 2 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ3 [1/2]

#define PDM_RANGE_CTRL_RANGEADJ3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)

RANGEADJ3 - Channel 3 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ3 [2/2]

#define PDM_RANGE_CTRL_RANGEADJ3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)

RANGEADJ3 - Channel 3 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ4 [1/2]

#define PDM_RANGE_CTRL_RANGEADJ4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)

RANGEADJ4 - Channel 4 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ4 [2/2]

#define PDM_RANGE_CTRL_RANGEADJ4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)

RANGEADJ4 - Channel 4 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ5 [1/2]

#define PDM_RANGE_CTRL_RANGEADJ5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)

RANGEADJ5 - Channel 5 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ5 [2/2]

#define PDM_RANGE_CTRL_RANGEADJ5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)

RANGEADJ5 - Channel 5 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ6 [1/2]

#define PDM_RANGE_CTRL_RANGEADJ6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)

RANGEADJ6 - Channel 6 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ6 [2/2]

#define PDM_RANGE_CTRL_RANGEADJ6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)

RANGEADJ6 - Channel 6 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ7 [1/2]

#define PDM_RANGE_CTRL_RANGEADJ7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)

RANGEADJ7 - Channel 7 Range Adjustment

◆ PDM_RANGE_CTRL_RANGEADJ7 [2/2]

#define PDM_RANGE_CTRL_RANGEADJ7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)

RANGEADJ7 - Channel 7 Range Adjustment

◆ PDM_RANGE_STAT_RANGEOVF0 [1/2]

#define PDM_RANGE_STAT_RANGEOVF0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)

RANGEOVF0 - Channel 0 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF0 [2/2]

#define PDM_RANGE_STAT_RANGEOVF0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)

RANGEOVF0 - Channel 0 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF1 [1/2]

#define PDM_RANGE_STAT_RANGEOVF1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)

RANGEOVF1 - Channel 1 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF1 [2/2]

#define PDM_RANGE_STAT_RANGEOVF1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)

RANGEOVF1 - Channel 1 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF2 [1/2]

#define PDM_RANGE_STAT_RANGEOVF2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)

RANGEOVF2 - Channel 2 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF2 [2/2]

#define PDM_RANGE_STAT_RANGEOVF2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)

RANGEOVF2 - Channel 2 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF3 [1/2]

#define PDM_RANGE_STAT_RANGEOVF3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)

RANGEOVF3 - Channel 3 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF3 [2/2]

#define PDM_RANGE_STAT_RANGEOVF3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)

RANGEOVF3 - Channel 3 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF4 [1/2]

#define PDM_RANGE_STAT_RANGEOVF4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)

RANGEOVF4 - Channel 4 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF4 [2/2]

#define PDM_RANGE_STAT_RANGEOVF4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)

RANGEOVF4 - Channel 4 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF5 [1/2]

#define PDM_RANGE_STAT_RANGEOVF5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)

RANGEOVF5 - Channel 5 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF5 [2/2]

#define PDM_RANGE_STAT_RANGEOVF5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)

RANGEOVF5 - Channel 5 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF6 [1/2]

#define PDM_RANGE_STAT_RANGEOVF6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)

RANGEOVF6 - Channel 6 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF6 [2/2]

#define PDM_RANGE_STAT_RANGEOVF6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)

RANGEOVF6 - Channel 6 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF7 [1/2]

#define PDM_RANGE_STAT_RANGEOVF7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)

RANGEOVF7 - Channel 7 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEOVF7 [2/2]

#define PDM_RANGE_STAT_RANGEOVF7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)

RANGEOVF7 - Channel 7 Range Overflow Error Flag 0b0..No exception by range overflow 0b1..Exception by range overflow

◆ PDM_RANGE_STAT_RANGEUNF0 [1/2]

#define PDM_RANGE_STAT_RANGEUNF0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)

RANGEUNF0 - Channel 0 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF0 [2/2]

#define PDM_RANGE_STAT_RANGEUNF0 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)

RANGEUNF0 - Channel 0 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF1 [1/2]

#define PDM_RANGE_STAT_RANGEUNF1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)

RANGEUNF1 - Channel 1 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF1 [2/2]

#define PDM_RANGE_STAT_RANGEUNF1 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)

RANGEUNF1 - Channel 1 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF2 [1/2]

#define PDM_RANGE_STAT_RANGEUNF2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)

RANGEUNF2 - Channel 2 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF2 [2/2]

#define PDM_RANGE_STAT_RANGEUNF2 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)

RANGEUNF2 - Channel 2 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF3 [1/2]

#define PDM_RANGE_STAT_RANGEUNF3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)

RANGEUNF3 - Channel 3 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF3 [2/2]

#define PDM_RANGE_STAT_RANGEUNF3 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)

RANGEUNF3 - Channel 3 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF4 [1/2]

#define PDM_RANGE_STAT_RANGEUNF4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)

RANGEUNF4 - Channel 4 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF4 [2/2]

#define PDM_RANGE_STAT_RANGEUNF4 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)

RANGEUNF4 - Channel 4 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF5 [1/2]

#define PDM_RANGE_STAT_RANGEUNF5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)

RANGEUNF5 - Channel 5 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF5 [2/2]

#define PDM_RANGE_STAT_RANGEUNF5 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)

RANGEUNF5 - Channel 5 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF6 [1/2]

#define PDM_RANGE_STAT_RANGEUNF6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)

RANGEUNF6 - Channel 6 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF6 [2/2]

#define PDM_RANGE_STAT_RANGEUNF6 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)

RANGEUNF6 - Channel 6 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF7 [1/2]

#define PDM_RANGE_STAT_RANGEUNF7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)

RANGEUNF7 - Channel 7 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_RANGE_STAT_RANGEUNF7 [2/2]

#define PDM_RANGE_STAT_RANGEUNF7 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)

RANGEUNF7 - Channel 7 Range Underflow Error Flag 0b0..No exception by range underflow 0b1..Exception by range underflow

◆ PDM_STAT_BSY_FIL [1/2]

#define PDM_STAT_BSY_FIL (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)

BSY_FIL - Busy Flag 0b1..PDM is running 0b0..PDM is stopped

◆ PDM_STAT_BSY_FIL [2/2]

#define PDM_STAT_BSY_FIL (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)

BSY_FIL - Busy Flag 0b1..PDM is running 0b0..PDM is stopped

◆ PDM_STAT_CH0F [1/2]

#define PDM_STAT_CH0F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)

CH0F - Channel 0 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH0F [2/2]

#define PDM_STAT_CH0F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)

CH0F - Channel 0 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH1F [1/2]

#define PDM_STAT_CH1F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)

CH1F - Channel 1 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH1F [2/2]

#define PDM_STAT_CH1F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)

CH1F - Channel 1 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH2F [1/2]

#define PDM_STAT_CH2F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)

CH2F - Channel 2 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH2F [2/2]

#define PDM_STAT_CH2F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)

CH2F - Channel 2 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH3F [1/2]

#define PDM_STAT_CH3F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)

CH3F - Channel 3 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH3F [2/2]

#define PDM_STAT_CH3F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)

CH3F - Channel 3 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH4F [1/2]

#define PDM_STAT_CH4F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)

CH4F - Channel 4 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH4F [2/2]

#define PDM_STAT_CH4F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)

CH4F - Channel 4 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH5F [1/2]

#define PDM_STAT_CH5F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)

CH5F - Channel 5 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH5F [2/2]

#define PDM_STAT_CH5F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)

CH5F - Channel 5 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH6F [1/2]

#define PDM_STAT_CH6F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)

CH6F - Channel 6 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH6F [2/2]

#define PDM_STAT_CH6F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)

CH6F - Channel 6 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH7F [1/2]

#define PDM_STAT_CH7F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)

CH7F - Channel 7 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_CH7F [2/2]

#define PDM_STAT_CH7F (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)

CH7F - Channel 7 Output Data Flag 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field

◆ PDM_STAT_FIR_RDY [1/2]

#define PDM_STAT_FIR_RDY (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)

FIR_RDY - Filter Data Ready 0b0..Filter data is not reliable 0b1..Filter data is reliable

◆ PDM_STAT_FIR_RDY [2/2]

#define PDM_STAT_FIR_RDY (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)

FIR_RDY - Filter Data Ready 0b0..Filter data is not reliable 0b1..Filter data is reliable

◆ PDM_STAT_LOWFREQF [1/2]

#define PDM_STAT_LOWFREQF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)

LOWFREQF - Low Frequency Flag 0b0..CLKDIV value is OK 0b1..CLKDIV value is too low

◆ PDM_STAT_LOWFREQF [2/2]

#define PDM_STAT_LOWFREQF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)

LOWFREQF - Low Frequency Flag 0b0..CLKDIV value is OK 0b1..CLKDIV value is too low

◆ PDM_VAD0_CTRL_1_VADCHSEL [1/2]

#define PDM_VAD0_CTRL_1_VADCHSEL (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)

VADCHSEL - Voice Activity Detector Channel Selector

◆ PDM_VAD0_CTRL_1_VADCHSEL [2/2]

#define PDM_VAD0_CTRL_1_VADCHSEL (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)

VADCHSEL - Voice Activity Detector Channel Selector

◆ PDM_VAD0_CTRL_1_VADCICOSR [1/2]

#define PDM_VAD0_CTRL_1_VADCICOSR (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)

VADCICOSR - Voice Activity Detector CIC Oversampling Rate

◆ PDM_VAD0_CTRL_1_VADCICOSR [2/2]

#define PDM_VAD0_CTRL_1_VADCICOSR (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)

VADCICOSR - Voice Activity Detector CIC Oversampling Rate

◆ PDM_VAD0_CTRL_1_VADEN [1/2]

#define PDM_VAD0_CTRL_1_VADEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)

VADEN - Voice Activity Detector Enable 0b0..The HWVAD is disabled 0b1..The HWVAD is enabled

◆ PDM_VAD0_CTRL_1_VADEN [2/2]

#define PDM_VAD0_CTRL_1_VADEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)

VADEN - Voice Activity Detector Enable 0b0..The HWVAD is disabled 0b1..The HWVAD is enabled

◆ PDM_VAD0_CTRL_1_VADERIE [1/2]

#define PDM_VAD0_CTRL_1_VADERIE (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)

VADERIE - Voice Activity Detector Error Interruption Enable 0b0..HWVAD Error Interrupts disabled 0b1..HWVAD Error Interrupts enabled

◆ PDM_VAD0_CTRL_1_VADERIE [2/2]

#define PDM_VAD0_CTRL_1_VADERIE (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)

VADERIE - Voice Activity Detector Error Interruption Enable 0b0..HWVAD Error Interrupts disabled 0b1..HWVAD Error Interrupts enabled

◆ PDM_VAD0_CTRL_1_VADIE [1/2]

#define PDM_VAD0_CTRL_1_VADIE (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)

VADIE - Voice Activity Detector Interruption Enable 0b0..HWVAD Interrupts disabled 0b1..HWVAD Interrupts enabled

◆ PDM_VAD0_CTRL_1_VADIE [2/2]

#define PDM_VAD0_CTRL_1_VADIE (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)

VADIE - Voice Activity Detector Interruption Enable 0b0..HWVAD Interrupts disabled 0b1..HWVAD Interrupts enabled

◆ PDM_VAD0_CTRL_1_VADINITT [1/2]

#define PDM_VAD0_CTRL_1_VADINITT (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)

VADINITT - Voice Activity Detector Initialization Time

◆ PDM_VAD0_CTRL_1_VADINITT [2/2]

#define PDM_VAD0_CTRL_1_VADINITT (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)

VADINITT - Voice Activity Detector Initialization Time

◆ PDM_VAD0_CTRL_1_VADRST [1/2]

#define PDM_VAD0_CTRL_1_VADRST (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)

VADRST - Voice Activity Detector Reset

◆ PDM_VAD0_CTRL_1_VADRST [2/2]

#define PDM_VAD0_CTRL_1_VADRST (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)

VADRST - Voice Activity Detector Reset

◆ PDM_VAD0_CTRL_1_VADST10 [1/2]

#define PDM_VAD0_CTRL_1_VADST10 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)

VADST10 - Voice Activity Detector Internal Filters Initialization 0b0..Normal operation. 0b1..Filters are initialized.

◆ PDM_VAD0_CTRL_1_VADST10 [2/2]

#define PDM_VAD0_CTRL_1_VADST10 (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)

VADST10 - Voice Activity Detector Internal Filters Initialization 0b0..Normal operation. 0b1..Filters are initialized.

◆ PDM_VAD0_CTRL_2_VADFOUTDIS [1/2]

#define PDM_VAD0_CTRL_2_VADFOUTDIS (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)

VADFOUTDIS - Voice Activity Detector Force Output Disable 0b0..Output is enabled. 0b1..Output is disabled.

◆ PDM_VAD0_CTRL_2_VADFOUTDIS [2/2]

#define PDM_VAD0_CTRL_2_VADFOUTDIS (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)

VADFOUTDIS - Voice Activity Detector Force Output Disable 0b0..Output is enabled. 0b1..Output is disabled.

◆ PDM_VAD0_CTRL_2_VADFRAMET [1/2]

#define PDM_VAD0_CTRL_2_VADFRAMET (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)

VADFRAMET - Voice Activity Detector Frame Time

◆ PDM_VAD0_CTRL_2_VADFRAMET [2/2]

#define PDM_VAD0_CTRL_2_VADFRAMET (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)

VADFRAMET - Voice Activity Detector Frame Time

◆ PDM_VAD0_CTRL_2_VADFRENDIS [1/2]

#define PDM_VAD0_CTRL_2_VADFRENDIS (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)

VADFRENDIS - Voice Activity Detector Frame Energy Disable 0b1..Frame energy calculus disabled. 0b0..Frame energy calculus enabled.

◆ PDM_VAD0_CTRL_2_VADFRENDIS [2/2]

#define PDM_VAD0_CTRL_2_VADFRENDIS (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)

VADFRENDIS - Voice Activity Detector Frame Energy Disable 0b1..Frame energy calculus disabled. 0b0..Frame energy calculus enabled.

◆ PDM_VAD0_CTRL_2_VADHPF [1/2]

#define PDM_VAD0_CTRL_2_VADHPF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)

VADHPF - Voice Activity Detector High-Pass Filter 0b00..Filter bypassed. 0b01..Cut-off frequency at 1750Hz. 0b10..Cut-off frequency at 215Hz. 0b11..Cut-off frequency at 102Hz.

◆ PDM_VAD0_CTRL_2_VADHPF [2/2]

#define PDM_VAD0_CTRL_2_VADHPF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)

VADHPF - Voice Activity Detector High-Pass Filter 0b00..Filter bypassed. 0b01..Cut-off frequency at 1750Hz. 0b10..Cut-off frequency at 215Hz. 0b11..Cut-off frequency at 102Hz.

◆ PDM_VAD0_CTRL_2_VADINPGAIN [1/2]

#define PDM_VAD0_CTRL_2_VADINPGAIN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)

VADINPGAIN - Voice Activity Detector Input Gain

◆ PDM_VAD0_CTRL_2_VADINPGAIN [2/2]

#define PDM_VAD0_CTRL_2_VADINPGAIN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)

VADINPGAIN - Voice Activity Detector Input Gain

◆ PDM_VAD0_CTRL_2_VADPREFEN [1/2]

#define PDM_VAD0_CTRL_2_VADPREFEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)

VADPREFEN - Voice Activity Detector Pre Filter Enable 0b0..Pre-filter is bypassed. 0b1..Pre-filter is enabled.

◆ PDM_VAD0_CTRL_2_VADPREFEN [2/2]

#define PDM_VAD0_CTRL_2_VADPREFEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)

VADPREFEN - Voice Activity Detector Pre Filter Enable 0b0..Pre-filter is bypassed. 0b1..Pre-filter is enabled.

◆ PDM_VAD0_NCONFIG_VADNDECEN [1/2]

#define PDM_VAD0_NCONFIG_VADNDECEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)

VADNDECEN - Voice Activity Detector Noise Decimation Enable 0b0..Noise input is not decimated. 0b1..Noise input is decimated.

◆ PDM_VAD0_NCONFIG_VADNDECEN [2/2]

#define PDM_VAD0_NCONFIG_VADNDECEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)

VADNDECEN - Voice Activity Detector Noise Decimation Enable 0b0..Noise input is not decimated. 0b1..Noise input is decimated.

◆ PDM_VAD0_NCONFIG_VADNFILADJ [1/2]

#define PDM_VAD0_NCONFIG_VADNFILADJ (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)

VADNFILADJ - Voice Activity Detector Noise Filter Adjustment

◆ PDM_VAD0_NCONFIG_VADNFILADJ [2/2]

#define PDM_VAD0_NCONFIG_VADNFILADJ (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)

VADNFILADJ - Voice Activity Detector Noise Filter Adjustment

◆ PDM_VAD0_NCONFIG_VADNFILAUTO [1/2]

#define PDM_VAD0_NCONFIG_VADNFILAUTO (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)

VADNFILAUTO - Voice Activity Detector Noise Filter Auto 0b0..Noise filter is always enabled. 0b1..Noise filter is enabled/disabled based on voice activity information.

◆ PDM_VAD0_NCONFIG_VADNFILAUTO [2/2]

#define PDM_VAD0_NCONFIG_VADNFILAUTO (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)

VADNFILAUTO - Voice Activity Detector Noise Filter Auto 0b0..Noise filter is always enabled. 0b1..Noise filter is enabled/disabled based on voice activity information.

◆ PDM_VAD0_NCONFIG_VADNGAIN [1/2]

#define PDM_VAD0_NCONFIG_VADNGAIN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)

VADNGAIN - Voice Activity Detector Noise Gain

◆ PDM_VAD0_NCONFIG_VADNGAIN [2/2]

#define PDM_VAD0_NCONFIG_VADNGAIN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)

VADNGAIN - Voice Activity Detector Noise Gain

◆ PDM_VAD0_NCONFIG_VADNMINEN [1/2]

#define PDM_VAD0_NCONFIG_VADNMINEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)

VADNMINEN - Voice Activity Detector Noise Minimum Enable 0b0..Minimum block is bypassed. 0b1..Minimum block is enabled.

◆ PDM_VAD0_NCONFIG_VADNMINEN [2/2]

#define PDM_VAD0_NCONFIG_VADNMINEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)

VADNMINEN - Voice Activity Detector Noise Minimum Enable 0b0..Minimum block is bypassed. 0b1..Minimum block is enabled.

◆ PDM_VAD0_NCONFIG_VADNOREN [1/2]

#define PDM_VAD0_NCONFIG_VADNOREN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)

VADNOREN - Voice Activity Detector Noise OR Enable 0b0..Noise input is not decimated. 0b1..Noise input is decimated.

◆ PDM_VAD0_NCONFIG_VADNOREN [2/2]

#define PDM_VAD0_NCONFIG_VADNOREN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)

VADNOREN - Voice Activity Detector Noise OR Enable 0b0..Noise input is not decimated. 0b1..Noise input is decimated.

◆ PDM_VAD0_NDATA_VADNDATA [1/2]

#define PDM_VAD0_NDATA_VADNDATA (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)

VADNDATA - Voice Activity Detector Noise Data

◆ PDM_VAD0_NDATA_VADNDATA [2/2]

#define PDM_VAD0_NDATA_VADNDATA (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)

VADNDATA - Voice Activity Detector Noise Data

◆ PDM_VAD0_SCONFIG_VADSFILEN [1/2]

#define PDM_VAD0_SCONFIG_VADSFILEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)

VADSFILEN - Voice Activity Detector Signal Filter Enable 0b0..Signal filter is disabled. 0b1..Signal filter is enabled.

◆ PDM_VAD0_SCONFIG_VADSFILEN [2/2]

#define PDM_VAD0_SCONFIG_VADSFILEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)

VADSFILEN - Voice Activity Detector Signal Filter Enable 0b0..Signal filter is disabled. 0b1..Signal filter is enabled.

◆ PDM_VAD0_SCONFIG_VADSGAIN [1/2]

#define PDM_VAD0_SCONFIG_VADSGAIN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)

VADSGAIN - Voice Activity Detector Signal Gain

◆ PDM_VAD0_SCONFIG_VADSGAIN [2/2]

#define PDM_VAD0_SCONFIG_VADSGAIN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)

VADSGAIN - Voice Activity Detector Signal Gain

◆ PDM_VAD0_SCONFIG_VADSMAXEN [1/2]

#define PDM_VAD0_SCONFIG_VADSMAXEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)

VADSMAXEN - Voice Activity Detector Signal Maximum Enable 0b0..Maximum block is bypassed. 0b1..Maximum block is enabled.

◆ PDM_VAD0_SCONFIG_VADSMAXEN [2/2]

#define PDM_VAD0_SCONFIG_VADSMAXEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)

VADSMAXEN - Voice Activity Detector Signal Maximum Enable 0b0..Maximum block is bypassed. 0b1..Maximum block is enabled.

◆ PDM_VAD0_STAT_VADEF [1/2]

#define PDM_VAD0_STAT_VADEF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)

VADEF - Voice Activity Detector Event Flag 0b0..Voice activity not detected 0b1..Voice activity detected

◆ PDM_VAD0_STAT_VADEF [2/2]

#define PDM_VAD0_STAT_VADEF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)

VADEF - Voice Activity Detector Event Flag 0b0..Voice activity not detected 0b1..Voice activity detected

◆ PDM_VAD0_STAT_VADIF [1/2]

#define PDM_VAD0_STAT_VADIF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)

VADIF - Voice Activity Detector Interrupt Flag 0b0..Voice activity not detected 0b1..Voice activity detected

◆ PDM_VAD0_STAT_VADIF [2/2]

#define PDM_VAD0_STAT_VADIF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)

VADIF - Voice Activity Detector Interrupt Flag 0b0..Voice activity not detected 0b1..Voice activity detected

◆ PDM_VAD0_STAT_VADINITF [1/2]

#define PDM_VAD0_STAT_VADINITF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)

VADINITF - Voice Activity Detector Initialization Flag 0b0..HWVAD is not being initialized. 0b1..HWVAD is being initialized.

◆ PDM_VAD0_STAT_VADINITF [2/2]

#define PDM_VAD0_STAT_VADINITF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)

VADINITF - Voice Activity Detector Initialization Flag 0b0..HWVAD is not being initialized. 0b1..HWVAD is being initialized.

◆ PDM_VAD0_STAT_VADINSATF [1/2]

#define PDM_VAD0_STAT_VADINSATF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)

VADINSATF - Voice Activity Detector Input Saturation Flag 0b0..No exception 0b1..Exception

◆ PDM_VAD0_STAT_VADINSATF [2/2]

#define PDM_VAD0_STAT_VADINSATF (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)

VADINSATF - Voice Activity Detector Input Saturation Flag 0b0..No exception 0b1..Exception

◆ PDM_VAD0_ZCD_VADZCDADJ [1/2]

#define PDM_VAD0_ZCD_VADZCDADJ (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)

VADZCDADJ - Zero-Crossing Detector Adjustment

◆ PDM_VAD0_ZCD_VADZCDADJ [2/2]

#define PDM_VAD0_ZCD_VADZCDADJ (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)

VADZCDADJ - Zero-Crossing Detector Adjustment

◆ PDM_VAD0_ZCD_VADZCDAND [1/2]

#define PDM_VAD0_ZCD_VADZCDAND (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)

VADZCDAND - Zero-Crossing Detector AND Behavior 0b0..The ZCD result is OR'ed with the energy-based detection. 0b1..The ZCD result is AND'ed with the energy-based detection.

◆ PDM_VAD0_ZCD_VADZCDAND [2/2]

#define PDM_VAD0_ZCD_VADZCDAND (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)

VADZCDAND - Zero-Crossing Detector AND Behavior 0b0..The ZCD result is OR'ed with the energy-based detection. 0b1..The ZCD result is AND'ed with the energy-based detection.

◆ PDM_VAD0_ZCD_VADZCDAUTO [1/2]

#define PDM_VAD0_ZCD_VADZCDAUTO (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)

VADZCDAUTO - Zero-Crossing Detector Automatic Threshold 0b0..The ZCD threshold is not estimated automatically 0b1..The ZCD threshold is estimated automatically

◆ PDM_VAD0_ZCD_VADZCDAUTO [2/2]

#define PDM_VAD0_ZCD_VADZCDAUTO (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)

VADZCDAUTO - Zero-Crossing Detector Automatic Threshold 0b0..The ZCD threshold is not estimated automatically 0b1..The ZCD threshold is estimated automatically

◆ PDM_VAD0_ZCD_VADZCDEN [1/2]

#define PDM_VAD0_ZCD_VADZCDEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)

VADZCDEN - Zero-Crossing Detector Enable 0b0..The ZCD is disabled 0b1..The ZCD is enabled

◆ PDM_VAD0_ZCD_VADZCDEN [2/2]

#define PDM_VAD0_ZCD_VADZCDEN (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)

VADZCDEN - Zero-Crossing Detector Enable 0b0..The ZCD is disabled 0b1..The ZCD is enabled

◆ PDM_VAD0_ZCD_VADZCDTH [1/2]

#define PDM_VAD0_ZCD_VADZCDTH (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)

VADZCDTH - Zero-Crossing Detector Threshold

◆ PDM_VAD0_ZCD_VADZCDTH [2/2]

#define PDM_VAD0_ZCD_VADZCDTH (   x)    (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)

VADZCDTH - Zero-Crossing Detector Threshold

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