RTEMS 6.1-rc6
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Macros

Macros

#define MMCAU_CA_COUNT   (9U)
 

CASR - Status Register

#define MMCAU_CASR_IC_MASK   (0x1U)
 
#define MMCAU_CASR_IC_SHIFT   (0U)
 
#define MMCAU_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_IC_SHIFT)) & MMCAU_CASR_IC_MASK)
 
#define MMCAU_CASR_DPE_MASK   (0x2U)
 
#define MMCAU_CASR_DPE_SHIFT   (1U)
 
#define MMCAU_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_DPE_SHIFT)) & MMCAU_CASR_DPE_MASK)
 
#define MMCAU_CASR_VER_MASK   (0xF0000000U)
 
#define MMCAU_CASR_VER_SHIFT   (28U)
 
#define MMCAU_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_VER_SHIFT)) & MMCAU_CASR_VER_MASK)
 

CAA - Accumulator

#define MMCAU_CAA_ACC_MASK   (0xFFFFFFFFU)
 
#define MMCAU_CAA_ACC_SHIFT   (0U)
 
#define MMCAU_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << MMCAU_CAA_ACC_SHIFT)) & MMCAU_CAA_ACC_MASK)
 

CA - General Purpose Register

#define MMCAU_CA_CAn_MASK   (0xFFFFFFFFU)
 
#define MMCAU_CA_CAn_SHIFT   (0U)
 
#define MMCAU_CA_CAn(x)   (((uint32_t)(((uint32_t)(x)) << MMCAU_CA_CAn_SHIFT)) & MMCAU_CA_CAn_MASK)
 

Detailed Description

Macro Definition Documentation

◆ MMCAU_CA_CAn

#define MMCAU_CA_CAn (   x)    (((uint32_t)(((uint32_t)(x)) << MMCAU_CA_CAn_SHIFT)) & MMCAU_CA_CAn_MASK)

CAn - General Purpose Registers

◆ MMCAU_CAA_ACC

#define MMCAU_CAA_ACC (   x)    (((uint32_t)(((uint32_t)(x)) << MMCAU_CAA_ACC_SHIFT)) & MMCAU_CAA_ACC_MASK)

ACC - Accumulator

◆ MMCAU_CASR_DPE

#define MMCAU_CASR_DPE (   x)    (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_DPE_SHIFT)) & MMCAU_CASR_DPE_MASK)

DPE - DES Parity Error 0b0..No error detected. 0b1..DES key parity error detected.

◆ MMCAU_CASR_IC

#define MMCAU_CASR_IC (   x)    (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_IC_SHIFT)) & MMCAU_CASR_IC_MASK)

IC - Illegal Command 0b0..No illegal commands issued. 0b1..Illegal command issued.

◆ MMCAU_CASR_VER

#define MMCAU_CASR_VER (   x)    (((uint32_t)(((uint32_t)(x)) << MMCAU_CASR_VER_SHIFT)) & MMCAU_CASR_VER_MASK)

VER - CAU Version 0b0001..Initial CAU version. 0b0010..Second version, added support for SHA-256 algorithm (This is the value on this device).