Macros
#define	MCM_LMDR_COUNT (4U)

PLREV - SoC-defined platform revision
#define	MCM_PLREV_PLREV_MASK (0xFFFFU)

#define	MCM_PLREV_PLREV_SHIFT (0U)

#define	MCM_PLREV_PLREV(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLREV_PLREV_SHIFT)) & MCM_PLREV_PLREV_MASK)

PCT - Processor core type
#define	MCM_PCT_PCT_MASK (0xFFFFU)

#define	MCM_PCT_PCT_SHIFT (0U)

#define	MCM_PCT_PCT(x) (((uint16_t)(((uint16_t)(x)) << MCM_PCT_PCT_SHIFT)) & MCM_PCT_PCT_MASK)

MEMCFG - Memory configuration
#define	MCM_MEMCFG_TCRAMUSZ_MASK (0x3CU)

#define	MCM_MEMCFG_TCRAMUSZ_SHIFT (2U)

#define	MCM_MEMCFG_TCRAMUSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_MEMCFG_TCRAMUSZ_SHIFT)) & MCM_MEMCFG_TCRAMUSZ_MASK)

#define	MCM_MEMCFG_TCRAMLSZ_MASK (0xF00U)

#define	MCM_MEMCFG_TCRAMLSZ_SHIFT (8U)

#define	MCM_MEMCFG_TCRAMLSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_MEMCFG_TCRAMLSZ_SHIFT)) & MCM_MEMCFG_TCRAMLSZ_MASK)

PLASC - Crossbar Switch (AXBS) Slave Configuration
#define	MCM_PLASC_ASC_MASK (0xFFU)

#define	MCM_PLASC_ASC_SHIFT (0U)

#define	MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)

PLAMC - Crossbar Switch (AXBS) Master Configuration
#define	MCM_PLAMC_AMC_MASK (0xFFU)

#define	MCM_PLAMC_AMC_SHIFT (0U)

#define	MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)

CR - Control Register
#define	MCM_CR_STATUS_MASK (0x1FFU)

#define	MCM_CR_STATUS_SHIFT (0U)

#define	MCM_CR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_STATUS_SHIFT)) & MCM_CR_STATUS_MASK)

#define	MCM_CR_CBRR_MASK (0x200U)

#define	MCM_CR_CBRR_SHIFT (9U)

#define	MCM_CR_CBRR(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_CBRR_SHIFT)) & MCM_CR_CBRR_MASK)

#define	MCM_CR_STCMAP_MASK (0x3000000U)

#define	MCM_CR_STCMAP_SHIFT (24U)

#define	MCM_CR_STCMAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_STCMAP_SHIFT)) & MCM_CR_STCMAP_MASK)

#define	MCM_CR_STCMWP_MASK (0x4000000U)

#define	MCM_CR_STCMWP_SHIFT (26U)

#define	MCM_CR_STCMWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_STCMWP_SHIFT)) & MCM_CR_STCMWP_MASK)

#define	MCM_CR_CTCMAP_MASK (0x30000000U)

#define	MCM_CR_CTCMAP_SHIFT (28U)

#define	MCM_CR_CTCMAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_CTCMAP_SHIFT)) & MCM_CR_CTCMAP_MASK)

#define	MCM_CR_CTCMWP_MASK (0x40000000U)

#define	MCM_CR_CTCMWP_SHIFT (30U)

#define	MCM_CR_CTCMWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_CTCMWP_SHIFT)) & MCM_CR_CTCMWP_MASK)

#define	OTFAD_CR_FERR_MASK (0x2U)

#define	OTFAD_CR_FERR_SHIFT (1U)

#define	OTFAD_CR_FERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)

#define	OTFAD_CR_FLDM_MASK (0x8U)

#define	OTFAD_CR_FLDM_SHIFT (3U)

#define	OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)

#define	OTFAD_CR_KBSE_MASK (0x10U)

#define	OTFAD_CR_KBSE_SHIFT (4U)

#define	OTFAD_CR_KBSE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)

#define	OTFAD_CR_KBPE_MASK (0x20U)

#define	OTFAD_CR_KBPE_SHIFT (5U)

#define	OTFAD_CR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)

#define	OTFAD_CR_RRAE_MASK (0x80U)

#define	OTFAD_CR_RRAE_SHIFT (7U)

#define	OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)

#define	OTFAD_CR_SKBP_MASK (0x40000000U)

#define	OTFAD_CR_SKBP_SHIFT (30U)

#define	OTFAD_CR_SKBP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)

#define	OTFAD_CR_GE_MASK (0x80000000U)

#define	OTFAD_CR_GE_SHIFT (31U)

#define	OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)

ISCR - Interrupt Status and Control Register
#define	MCM_ISCR_CWBER_MASK (0x10U)

#define	MCM_ISCR_CWBER_SHIFT (4U)

#define	MCM_ISCR_CWBER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBER_SHIFT)) & MCM_ISCR_CWBER_MASK)

#define	MCM_ISCR_FIOC_MASK (0x100U)

#define	MCM_ISCR_FIOC_SHIFT (8U)

#define	MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)

#define	MCM_ISCR_FDZC_MASK (0x200U)

#define	MCM_ISCR_FDZC_SHIFT (9U)

#define	MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)

#define	MCM_ISCR_FOFC_MASK (0x400U)

#define	MCM_ISCR_FOFC_SHIFT (10U)

#define	MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)

#define	MCM_ISCR_FUFC_MASK (0x800U)

#define	MCM_ISCR_FUFC_SHIFT (11U)

#define	MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)

#define	MCM_ISCR_FIXC_MASK (0x1000U)

#define	MCM_ISCR_FIXC_SHIFT (12U)

#define	MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)

#define	MCM_ISCR_FIDC_MASK (0x8000U)

#define	MCM_ISCR_FIDC_SHIFT (15U)

#define	MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)

#define	MCM_ISCR_CWBEE_MASK (0x100000U)

#define	MCM_ISCR_CWBEE_SHIFT (20U)

#define	MCM_ISCR_CWBEE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBEE_SHIFT)) & MCM_ISCR_CWBEE_MASK)

#define	MCM_ISCR_FIOCE_MASK (0x1000000U)

#define	MCM_ISCR_FIOCE_SHIFT (24U)

#define	MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)

#define	MCM_ISCR_FDZCE_MASK (0x2000000U)

#define	MCM_ISCR_FDZCE_SHIFT (25U)

#define	MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)

#define	MCM_ISCR_FOFCE_MASK (0x4000000U)

#define	MCM_ISCR_FOFCE_SHIFT (26U)

#define	MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)

#define	MCM_ISCR_FUFCE_MASK (0x8000000U)

#define	MCM_ISCR_FUFCE_SHIFT (27U)

#define	MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)

#define	MCM_ISCR_FIXCE_MASK (0x10000000U)

#define	MCM_ISCR_FIXCE_SHIFT (28U)

#define	MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)

#define	MCM_ISCR_FIDCE_MASK (0x80000000U)

#define	MCM_ISCR_FIDCE_SHIFT (31U)

#define	MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)

FADR - Fault address register
#define	MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU)

#define	MCM_FADR_ADDRESS_SHIFT (0U)

#define	MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)

FATR - Fault attributes register
#define	MCM_FATR_BEDA_MASK (0x1U)

#define	MCM_FATR_BEDA_SHIFT (0U)

#define	MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)

#define	MCM_FATR_BEMD_MASK (0x2U)

#define	MCM_FATR_BEMD_SHIFT (1U)

#define	MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)

#define	MCM_FATR_BESZ_MASK (0x30U)

#define	MCM_FATR_BESZ_SHIFT (4U)

#define	MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)

#define	MCM_FATR_BEWT_MASK (0x80U)

#define	MCM_FATR_BEWT_SHIFT (7U)

#define	MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)

#define	MCM_FATR_BEMN_MASK (0xF00U)

#define	MCM_FATR_BEMN_SHIFT (8U)

#define	MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)

#define	MCM_FATR_BEOVR_MASK (0x80000000U)

#define	MCM_FATR_BEOVR_SHIFT (31U)

#define	MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)

FDR - Fault data register
#define	MCM_FDR_DATA_MASK (0xFFFFFFFFU)

#define	MCM_FDR_DATA_SHIFT (0U)

#define	MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)

LMDR - Local Memory Descriptor Register
#define	MCM_LMDR_CF0_MASK (0xFU)

#define	MCM_LMDR_CF0_SHIFT (0U)

#define	MCM_LMDR_CF0(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_CF0_SHIFT)) & MCM_LMDR_CF0_MASK)

#define	MCM_LMDR_CF1_MASK (0xF0U)

#define	MCM_LMDR_CF1_SHIFT (4U)

#define	MCM_LMDR_CF1(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_CF1_SHIFT)) & MCM_LMDR_CF1_MASK)

#define	MCM_LMDR_MT_MASK (0xE000U)

#define	MCM_LMDR_MT_SHIFT (13U)

#define	MCM_LMDR_MT(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_MT_SHIFT)) & MCM_LMDR_MT_MASK)

#define	MCM_LMDR_RO_MASK (0x10000U)

#define	MCM_LMDR_RO_SHIFT (16U)

#define	MCM_LMDR_RO(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_RO_SHIFT)) & MCM_LMDR_RO_MASK)

#define	MCM_LMDR_DPW_MASK (0xE0000U)

#define	MCM_LMDR_DPW_SHIFT (17U)

#define	MCM_LMDR_DPW(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_DPW_SHIFT)) & MCM_LMDR_DPW_MASK)

#define	MCM_LMDR_WY_MASK (0xF00000U)

#define	MCM_LMDR_WY_SHIFT (20U)

#define	MCM_LMDR_WY(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_WY_SHIFT)) & MCM_LMDR_WY_MASK)

#define	MCM_LMDR_LMSZ_MASK (0xF000000U)

#define	MCM_LMDR_LMSZ_SHIFT (24U)

#define	MCM_LMDR_LMSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZ_SHIFT)) & MCM_LMDR_LMSZ_MASK)

#define	MCM_LMDR_LMSZH_MASK (0x10000000U)

#define	MCM_LMDR_LMSZH_SHIFT (28U)

#define	MCM_LMDR_LMSZH(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZH_SHIFT)) & MCM_LMDR_LMSZH_MASK)

#define	MCM_LMDR_V_MASK (0x80000000U)

#define	MCM_LMDR_V_SHIFT (31U)

#define	MCM_LMDR_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_V_SHIFT)) & MCM_LMDR_V_MASK)

LMPECR - LMEM Parity & ECC Control Register
#define	MCM_LMPECR_ERNCR_MASK (0x1U)

#define	MCM_LMPECR_ERNCR_SHIFT (0U)

#define	MCM_LMPECR_ERNCR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ERNCR_SHIFT)) & MCM_LMPECR_ERNCR_MASK)

#define	MCM_LMPECR_ERNCI_MASK (0x2U)

#define	MCM_LMPECR_ERNCI_SHIFT (1U)

#define	MCM_LMPECR_ERNCI(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ERNCI_SHIFT)) & MCM_LMPECR_ERNCI_MASK)

#define	MCM_LMPECR_ER1BR_MASK (0x100U)

#define	MCM_LMPECR_ER1BR_SHIFT (8U)

#define	MCM_LMPECR_ER1BR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ER1BR_SHIFT)) & MCM_LMPECR_ER1BR_MASK)

#define	MCM_LMPECR_ER1BI_MASK (0x200U)

#define	MCM_LMPECR_ER1BI_SHIFT (9U)

#define	MCM_LMPECR_ER1BI(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ER1BI_SHIFT)) & MCM_LMPECR_ER1BI_MASK)

#define	MCM_LMPECR_ECPR_MASK (0x100000U)

#define	MCM_LMPECR_ECPR_SHIFT (20U)

#define	MCM_LMPECR_ECPR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ECPR_SHIFT)) & MCM_LMPECR_ECPR_MASK)

#define	MCM_LMPECR_ECPI_MASK (0x200000U)

#define	MCM_LMPECR_ECPI_SHIFT (21U)

#define	MCM_LMPECR_ECPI(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ECPI_SHIFT)) & MCM_LMPECR_ECPI_MASK)

LMPEIR - LMEM Parity & ECC Interrupt Register
#define	MCM_LMPEIR_ENC_MASK (0xFFU)

#define	MCM_LMPEIR_ENC_SHIFT (0U)

#define	MCM_LMPEIR_ENC(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_ENC_SHIFT)) & MCM_LMPEIR_ENC_MASK)

#define	MCM_LMPEIR_E1B_MASK (0xFF00U)

#define	MCM_LMPEIR_E1B_SHIFT (8U)

#define	MCM_LMPEIR_E1B(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_E1B_SHIFT)) & MCM_LMPEIR_E1B_MASK)

#define	MCM_LMPEIR_PE_MASK (0xFF0000U)

#define	MCM_LMPEIR_PE_SHIFT (16U)

#define	MCM_LMPEIR_PE(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PE_SHIFT)) & MCM_LMPEIR_PE_MASK)

#define	MCM_LMPEIR_PEELOC_MASK (0x1F000000U)

#define	MCM_LMPEIR_PEELOC_SHIFT (24U)

#define	MCM_LMPEIR_PEELOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PEELOC_SHIFT)) & MCM_LMPEIR_PEELOC_MASK)

#define	MCM_LMPEIR_V_MASK (0x80000000U)

#define	MCM_LMPEIR_V_SHIFT (31U)

#define	MCM_LMPEIR_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_V_SHIFT)) & MCM_LMPEIR_V_MASK)

LMFAR - LMEM Fault Address Register
#define	MCM_LMFAR_EFADD_MASK (0xFFFFFFFFU)

#define	MCM_LMFAR_EFADD_SHIFT (0U)

#define	MCM_LMFAR_EFADD(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFAR_EFADD_SHIFT)) & MCM_LMFAR_EFADD_MASK)

LMFATR - LMEM Fault Attribute Register
#define	MCM_LMFATR_PEFPRT_MASK (0xFU)

#define	MCM_LMFATR_PEFPRT_SHIFT (0U)

#define	MCM_LMFATR_PEFPRT(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFPRT_SHIFT)) & MCM_LMFATR_PEFPRT_MASK)

#define	MCM_LMFATR_PEFSIZE_MASK (0x70U)

#define	MCM_LMFATR_PEFSIZE_SHIFT (4U)

#define	MCM_LMFATR_PEFSIZE(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFSIZE_SHIFT)) & MCM_LMFATR_PEFSIZE_MASK)

#define	MCM_LMFATR_PEFW_MASK (0x80U)

#define	MCM_LMFATR_PEFW_SHIFT (7U)

#define	MCM_LMFATR_PEFW(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFW_SHIFT)) & MCM_LMFATR_PEFW_MASK)

#define	MCM_LMFATR_PEFMST_MASK (0xFF00U)

#define	MCM_LMFATR_PEFMST_SHIFT (8U)

#define	MCM_LMFATR_PEFMST(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFMST_SHIFT)) & MCM_LMFATR_PEFMST_MASK)

#define	MCM_LMFATR_WORDID_MASK (0x1000000U)

#define	MCM_LMFATR_WORDID_SHIFT (24U)

#define	MCM_LMFATR_WORDID(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_WORDID_SHIFT)) & MCM_LMFATR_WORDID_MASK)

#define	MCM_LMFATR_OVR_MASK (0x80000000U)

#define	MCM_LMFATR_OVR_SHIFT (31U)

#define	MCM_LMFATR_OVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_OVR_SHIFT)) & MCM_LMFATR_OVR_MASK)

LMFDHR - LMEM Fault Data High Register
#define	MCM_LMFDHR_PEFDH_MASK (0xFFFFFFFFU)

#define	MCM_LMFDHR_PEFDH_SHIFT (0U)

#define	MCM_LMFDHR_PEFDH(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFDHR_PEFDH_SHIFT)) & MCM_LMFDHR_PEFDH_MASK)

LMFDLR - LMEM Fault Data Low Register
#define	MCM_LMFDLR_PEFDL_MASK (0xFFFFFFFFU)

#define	MCM_LMFDLR_PEFDL_SHIFT (0U)

#define	MCM_LMFDLR_PEFDL(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFDLR_PEFDL_SHIFT)) & MCM_LMFDLR_PEFDL_MASK)

ISCR - Interrupt Status and Control Register
#define	MCM_ISCR_WABS_MASK (0x20U)

#define	MCM_ISCR_WABS_SHIFT (5U)

#define	MCM_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABS_SHIFT)) & MCM_ISCR_WABS_MASK)

#define	MCM_ISCR_WABSO_MASK (0x40U)

#define	MCM_ISCR_WABSO_SHIFT (6U)

#define	MCM_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABSO_SHIFT)) & MCM_ISCR_WABSO_MASK)

#define	MCM_ISCR_FIOC_MASK (0x100U)

#define	MCM_ISCR_FIOC_SHIFT (8U)

#define	MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)

#define	MCM_ISCR_FDZC_MASK (0x200U)

#define	MCM_ISCR_FDZC_SHIFT (9U)

#define	MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)

#define	MCM_ISCR_FOFC_MASK (0x400U)

#define	MCM_ISCR_FOFC_SHIFT (10U)

#define	MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)

#define	MCM_ISCR_FUFC_MASK (0x800U)

#define	MCM_ISCR_FUFC_SHIFT (11U)

#define	MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)

#define	MCM_ISCR_FIXC_MASK (0x1000U)

#define	MCM_ISCR_FIXC_SHIFT (12U)

#define	MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)

#define	MCM_ISCR_FIDC_MASK (0x8000U)

#define	MCM_ISCR_FIDC_SHIFT (15U)

#define	MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)

#define	MCM_ISCR_WABE_MASK (0x200000U)

#define	MCM_ISCR_WABE_SHIFT (21U)

#define	MCM_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABE_SHIFT)) & MCM_ISCR_WABE_MASK)

#define	MCM_ISCR_FIOCE_MASK (0x1000000U)

#define	MCM_ISCR_FIOCE_SHIFT (24U)

#define	MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)

#define	MCM_ISCR_FDZCE_MASK (0x2000000U)

#define	MCM_ISCR_FDZCE_SHIFT (25U)

#define	MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)

#define	MCM_ISCR_FOFCE_MASK (0x4000000U)

#define	MCM_ISCR_FOFCE_SHIFT (26U)

#define	MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)

#define	MCM_ISCR_FUFCE_MASK (0x8000000U)

#define	MCM_ISCR_FUFCE_SHIFT (27U)

#define	MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)

#define	MCM_ISCR_FIXCE_MASK (0x10000000U)

#define	MCM_ISCR_FIXCE_SHIFT (28U)

#define	MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)

#define	MCM_ISCR_FIDCE_MASK (0x80000000U)

#define	MCM_ISCR_FIDCE_SHIFT (31U)

#define	MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)

Detailed Description

Macro Definition Documentation

◆ MCM_CR_CBRR

#define MCM_CR_CBRR ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_CR_CBRR_SHIFT)) & MCM_CR_CBRR_MASK)

CBRR - Crossbar round-robin arbitration enable 0b0..Fixed-priority arbitration 0b1..Round-robin arbitration

◆ MCM_CR_CTCMAP

#define MCM_CR_CTCMAP ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_CR_CTCMAP_SHIFT)) & MCM_CR_CTCMAP_MASK)

CTCMAP - Code TCM arbitration priority 0b00..Round robin 0b01..Special round robin (favors TCM backoor accesses over the processor) 0b10..Fixed priority. Processor has highest, backdoor has lowest 0b11..Fixed priority. Backdoor has highest, processor has lowest

◆ MCM_CR_CTCMWP

#define MCM_CR_CTCMWP ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_CR_CTCMWP_SHIFT)) & MCM_CR_CTCMWP_MASK)

CTCMWP - Code TCM Write Protect

◆ MCM_CR_STATUS

#define MCM_CR_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_CR_STATUS_SHIFT)) & MCM_CR_STATUS_MASK)

STATUS - Status bits

◆ MCM_CR_STCMAP

#define MCM_CR_STCMAP ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_CR_STCMAP_SHIFT)) & MCM_CR_STCMAP_MASK)

STCMAP - System TCM arbitration priority 0b00..Round robin 0b01..Special round robin (favors TCM backoor accesses over the processor) 0b10..Fixed priority. Processor has highest, backdoor has lowest 0b11..Fixed priority. Backdoor has highest, processor has lowest

◆ MCM_CR_STCMWP

#define MCM_CR_STCMWP ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_CR_STCMWP_SHIFT)) & MCM_CR_STCMWP_MASK)

STCMWP - System TCM write protect

◆ MCM_FADR_ADDRESS

#define MCM_FADR_ADDRESS ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)

ADDRESS - Fault address

◆ MCM_FATR_BEDA

#define MCM_FATR_BEDA ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)

BEDA - Bus error access type 0b0..Instruction 0b1..Data

◆ MCM_FATR_BEMD

#define MCM_FATR_BEMD ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)

BEMD - Bus error privilege level 0b0..User mode 0b1..Supervisor/privileged mode

◆ MCM_FATR_BEMN

#define MCM_FATR_BEMN ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)

BEMN - Bus error master number

◆ MCM_FATR_BEOVR

#define MCM_FATR_BEOVR ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)

BEOVR - Bus error overrun 0b0..No bus error overrun 0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error.

◆ MCM_FATR_BESZ

#define MCM_FATR_BESZ ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)

BESZ - Bus error size 0b00..8-bit access 0b01..16-bit access 0b10..32-bit access 0b11..Reserved

◆ MCM_FATR_BEWT

#define MCM_FATR_BEWT ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)

BEWT - Bus error write 0b0..Read access 0b1..Write access

◆ MCM_FDR_DATA

#define MCM_FDR_DATA ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)

DATA - Fault data

◆ MCM_ISCR_CWBEE

#define MCM_ISCR_CWBEE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBEE_SHIFT)) & MCM_ISCR_CWBEE_MASK)

CWBEE - Cache write buffer error enable 0b0..Disable error interrupt 0b1..Enable error interrupt

◆ MCM_ISCR_CWBER

#define MCM_ISCR_CWBER ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBER_SHIFT)) & MCM_ISCR_CWBER_MASK)

CWBER - Cache write buffer error status 0b0..No error 0b1..Error occurred

◆ MCM_ISCR_FDZC [1/2]

#define MCM_ISCR_FDZC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)

FDZC - FPU divide-by-zero interrupt status 0b0..No interrupt 0b1..Interrupt occurred

◆ MCM_ISCR_FDZC [2/2]

#define MCM_ISCR_FDZC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)

FDZC - FPU Divide-by-Zero Interrupt Status 0b0..No interrupt 0b1..Interrupt occured

◆ MCM_ISCR_FDZCE [1/2]

#define MCM_ISCR_FDZCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)

FDZCE - FPU divide-by-zero interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_FDZCE [2/2]

#define MCM_ISCR_FDZCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)

FDZCE - FPU Divide-by-Zero Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_FIDC [1/2]

#define MCM_ISCR_FIDC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)

FIDC - FPU input denormal interrupt status 0b0..No interrupt 0b1..Interrupt occurred

◆ MCM_ISCR_FIDC [2/2]

#define MCM_ISCR_FIDC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)

FIDC - FPU Input Denormal Interrupt Status 0b0..No interrupt 0b1..Interrupt occured

◆ MCM_ISCR_FIDCE [1/2]

#define MCM_ISCR_FIDCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)

FIDCE - FPU input denormal interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_FIDCE [2/2]

#define MCM_ISCR_FIDCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)

FIDCE - FPU Input Denormal Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_FIOC [1/2]

#define MCM_ISCR_FIOC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)

FIOC - FPU invalid operation interrupt status 0b0..No interrupt 0b1..Interrupt occurred

◆ MCM_ISCR_FIOC [2/2]

#define MCM_ISCR_FIOC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)

FIOC - FPU Invalid Operation interrupt Status 0b0..No interrupt 0b1..Interrupt occured

◆ MCM_ISCR_FIOCE [1/2]

#define MCM_ISCR_FIOCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)

FIOCE - FPU invalid operation interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_FIOCE [2/2]

#define MCM_ISCR_FIOCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)

FIOCE - FPU Invalid Operation Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_FIXC [1/2]

#define MCM_ISCR_FIXC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)

FIXC - FPU inexact interrupt status 0b0..No interrupt 0b1..Interrupt occurred

◆ MCM_ISCR_FIXC [2/2]

#define MCM_ISCR_FIXC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)

FIXC - FPU Inexact Interrupt Status 0b0..No interrupt 0b1..Interrupt occured

◆ MCM_ISCR_FIXCE [1/2]

#define MCM_ISCR_FIXCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)

FIXCE - FPU inexact interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_FIXCE [2/2]

#define MCM_ISCR_FIXCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)

FIXCE - FPU Inexact Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_FOFC [1/2]

#define MCM_ISCR_FOFC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)

FOFC - FPU overflow interrupt status 0b0..No interrupt 0b1..Interrupt occurred

◆ MCM_ISCR_FOFC [2/2]

#define MCM_ISCR_FOFC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)

FOFC - FPU Overflow interrupt status 0b0..No interrupt 0b1..Interrupt occured

◆ MCM_ISCR_FOFCE [1/2]

#define MCM_ISCR_FOFCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)

FOFCE - FPU overflow interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_FOFCE [2/2]

#define MCM_ISCR_FOFCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)

FOFCE - FPU Overflow Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_FUFC [1/2]

#define MCM_ISCR_FUFC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)

FUFC - FPU underflow interrupt status 0b0..No interrupt 0b1..Interrupt occurred

◆ MCM_ISCR_FUFC [2/2]

#define MCM_ISCR_FUFC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)

FUFC - FPU Underflow Interrupt Status 0b0..No interrupt 0b1..Interrupt occured

◆ MCM_ISCR_FUFCE [1/2]

#define MCM_ISCR_FUFCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)

FUFCE - FPU underflow interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_FUFCE [2/2]

#define MCM_ISCR_FUFCE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)

FUFCE - FPU Underflow Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_WABE

#define MCM_ISCR_WABE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABE_SHIFT)) & MCM_ISCR_WABE_MASK)

WABE - TCM Write Abort Interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt

◆ MCM_ISCR_WABS

#define MCM_ISCR_WABS ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABS_SHIFT)) & MCM_ISCR_WABS_MASK)

WABS - Write Abort on Slave 0b0..No abort 0b1..Abort

◆ MCM_ISCR_WABSO

#define MCM_ISCR_WABSO ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABSO_SHIFT)) & MCM_ISCR_WABSO_MASK)

WABSO - Write Abort on Slave Overrun 0b0..No write abort overrun 0b1..Write abort overrun occurred

◆ MCM_LMDR_CF0

#define MCM_LMDR_CF0 ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_CF0_SHIFT)) & MCM_LMDR_CF0_MASK)

CF0 - Control Field 0

◆ MCM_LMDR_CF1

#define MCM_LMDR_CF1 ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_CF1_SHIFT)) & MCM_LMDR_CF1_MASK)

CF1 - Control Field 1 - for Cache Parity control functions

◆ MCM_LMDR_DPW

#define MCM_LMDR_DPW ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_DPW_SHIFT)) & MCM_LMDR_DPW_MASK)

DPW 0b000-0b001..Reserved 0b010..LMEMn 32-bits wide 0b011..LMEMn 64-bits wide 0b100-0b111..Reserved

◆ MCM_LMDR_LMSZ

#define MCM_LMDR_LMSZ ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZ_SHIFT)) & MCM_LMDR_LMSZ_MASK)

LMSZ 0b0000..no LMEMn (0 KB) 0b0001..1 KB LMEMn 0b0010..2 KB LMEMn 0b0011..4 KB LMEMn 0b0100..8 KB LMEMn 0b0101..16 KB LMEMn 0b0110..32 KB LMEMn 0b0111..64 KB LMEMn 0b1000..128 KB LMEMn 0b1001..256 KB LMEMn 0b1010..512 KB LMEMn 0b1011..1024 KB LMEMn 0b1100..2048 KB LMEMn 0b1101..4096 KB LMEMn 0b1110..8192 KB LMEMn 0b1111..16384 KB LMEMn

◆ MCM_LMDR_LMSZH

#define MCM_LMDR_LMSZH ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZH_SHIFT)) & MCM_LMDR_LMSZH_MASK)

LMSZH 0b0..LMEMn is a power-of-2 capacity. 0b1..LMEMn is not a power-of-2, with a capacity is 0.75 * LMSZ.

◆ MCM_LMDR_MT

#define MCM_LMDR_MT ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_MT_SHIFT)) & MCM_LMDR_MT_MASK)

MT - Memory Type 0b000..code TCM 0b001..system TCM 0b010..PC Cache 0b011..PS Cache

◆ MCM_LMDR_RO

#define MCM_LMDR_RO ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_RO_SHIFT)) & MCM_LMDR_RO_MASK)

RO 0b0..Writes to the LMDRn[7:0] are allowed. 0b1..Writes to the LMDRn[7:0] are ignored.

◆ MCM_LMDR_V

#define MCM_LMDR_V ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_V_SHIFT)) & MCM_LMDR_V_MASK)

V 0b0..LMEMn is not present. 0b1..LMEMn is present.

◆ MCM_LMDR_WY

#define MCM_LMDR_WY ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_WY_SHIFT)) & MCM_LMDR_WY_MASK)

WY - Level 1 Cache Ways 0b0000..No Cache 0b0010..2-Way Set Associative 0b0100..4-Way Set Associative

◆ MCM_LMFAR_EFADD

#define MCM_LMFAR_EFADD ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMFAR_EFADD_SHIFT)) & MCM_LMFAR_EFADD_MASK)

EFADD - ECC Fault Address

◆ MCM_LMFATR_OVR

#define MCM_LMFATR_OVR ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_OVR_SHIFT)) & MCM_LMFATR_OVR_MASK)

OVR - Overrun

◆ MCM_LMPECR_ECPI

#define MCM_LMPECR_ECPI ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ECPI_SHIFT)) & MCM_LMPECR_ECPI_MASK)

ECPI - Enable Cache Parity IRQ 0b0..enabled 0b1..disabled

◆ MCM_LMPECR_ECPR

#define MCM_LMPECR_ECPR ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ECPR_SHIFT)) & MCM_LMPECR_ECPR_MASK)

ECPR - Enable Cache Parity Reporting 0b0..reporting enabled 0b1..reporting disabled

◆ MCM_LMPECR_ER1BI

#define MCM_LMPECR_ER1BI ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ER1BI_SHIFT)) & MCM_LMPECR_ER1BI_MASK)

ER1BI - Enable RAM ECC 1-bit Interrupt 0b0..Interrupt is disabled 0b1..Interrupt is enabled

◆ MCM_LMPECR_ER1BR

#define MCM_LMPECR_ER1BR ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ER1BR_SHIFT)) & MCM_LMPECR_ER1BR_MASK)

ER1BR - Enable RAM ECC 1-bit Reporting 0b0..reporting enabled 0b1..reporting disabled

◆ MCM_LMPECR_ERNCI

#define MCM_LMPECR_ERNCI ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ERNCI_SHIFT)) & MCM_LMPECR_ERNCI_MASK)

ERNCI 0b0..Interrupt is disabled 0b1..Interrupt is enabled

◆ MCM_LMPECR_ERNCR

#define MCM_LMPECR_ERNCR ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ERNCR_SHIFT)) & MCM_LMPECR_ERNCR_MASK)

ERNCR - Enable RAM ECC Non-correctable Reporting 0b0..reporting enabled 0b1..reporting disabled

◆ MCM_LMPEIR_E1B

#define MCM_LMPEIR_E1B ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_E1B_SHIFT)) & MCM_LMPEIR_E1B_MASK)

E1B - E1Bn = ECC 1-bit Error n

◆ MCM_LMPEIR_ENC

#define MCM_LMPEIR_ENC ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_ENC_SHIFT)) & MCM_LMPEIR_ENC_MASK)

ENC - ENCn = ECC Non-correctable Error n

◆ MCM_LMPEIR_PE

#define MCM_LMPEIR_PE ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PE_SHIFT)) & MCM_LMPEIR_PE_MASK)

PE - Parity Error

◆ MCM_LMPEIR_V

#define MCM_LMPEIR_V ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_V_SHIFT)) & MCM_LMPEIR_V_MASK)

V - Valid bit

◆ MCM_MEMCFG_TCRAMLSZ

#define MCM_MEMCFG_TCRAMLSZ ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_MEMCFG_TCRAMLSZ_SHIFT)) & MCM_MEMCFG_TCRAMLSZ_MASK)

TCRAMLSZ - TCRAML size

◆ MCM_MEMCFG_TCRAMUSZ

#define MCM_MEMCFG_TCRAMUSZ ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_MEMCFG_TCRAMUSZ_SHIFT)) & MCM_MEMCFG_TCRAMUSZ_MASK)

TCRAMUSZ - TCRAMU size

◆ MCM_PCT_PCT

#define MCM_PCT_PCT ( x ) (((uint16_t)(((uint16_t)(x)) << MCM_PCT_PCT_SHIFT)) & MCM_PCT_PCT_MASK)

PCT - This MCM design supports the ARM Cortex M4 core. The following value identifies this core complex. 0b1010110001000000..ARM Cortex M4

◆ MCM_PLAMC_AMC

#define MCM_PLAMC_AMC ( x ) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)

AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0b00000000..A bus master connection to AXBS input port n is absent 0b00000001..A bus master connection to AXBS input port n is present

◆ MCM_PLASC_ASC

#define MCM_PLASC_ASC ( x ) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)

ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0b00000000..A bus slave connection to AXBS input port n is absent 0b00000001..A bus slave connection to AXBS input port n is present

◆ MCM_PLREV_PLREV

#define MCM_PLREV_PLREV ( x ) (((uint16_t)(((uint16_t)(x)) << MCM_PLREV_PLREV_SHIFT)) & MCM_PLREV_PLREV_MASK)

PLREV - The PLREV[15:0] field is specified by an platform input signal to define a software-visible revision number.

◆ OTFAD_CR_FERR

#define OTFAD_CR_FERR ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)

FERR - Force Error 0b0..No effect on the SR[KBERE] indicator. 0b1..SR[KBERR] is immediately set after a write with this data bit set.

◆ OTFAD_CR_FLDM

#define OTFAD_CR_FLDM ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)

FLDM - Force Logically Disabled Mode 0b0..No effect on the operating mode. 0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.

◆ OTFAD_CR_GE

#define OTFAD_CR_GE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)

GE - Global OTFAD Enable 0b0..OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing. 0b1..OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.

◆ OTFAD_CR_KBPE

#define OTFAD_CR_KBPE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)

KBPE - Key Blob Processing Enable 0b0..Key blob processing is disabled. 0b1..Key blob processing is enabled.

◆ OTFAD_CR_KBSE

#define OTFAD_CR_KBSE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)

KBSE - Key Blob Scramble Enable 0b0..Key blob KEK scrambling is disabled. 0b1..Key blob KEK scrambling is enabled.

◆ OTFAD_CR_RRAE

#define OTFAD_CR_RRAE ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)

RRAE - Restricted Register Access Enable 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.

◆ OTFAD_CR_SKBP

#define OTFAD_CR_SKBP ( x ) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)

SKBP - Start key blob processing 0b0..Key blob processing is not initiated. 0b1..Properly-enabled key blob processing is initiated.

Macros

PLREV - SoC-defined platform revision

PCT - Processor core type

MEMCFG - Memory configuration

PLASC - Crossbar Switch (AXBS) Slave Configuration

PLAMC - Crossbar Switch (AXBS) Master Configuration

CR - Control Register

ISCR - Interrupt Status and Control Register

FADR - Fault address register

FATR - Fault attributes register

FDR - Fault data register

LMDR - Local Memory Descriptor Register

LMPECR - LMEM Parity & ECC Control Register

LMPEIR - LMEM Parity & ECC Interrupt Register

LMFAR - LMEM Fault Address Register

LMFATR - LMEM Fault Attribute Register

LMFDHR - LMEM Fault Data High Register

LMFDLR - LMEM Fault Data Low Register