This group contains the L2C-310 cache support.
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file | cache-l2c-310.c |
| This source file contains the implementation of the ARM L2C-310 cache controller support.
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#define | CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT |
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#define | CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT |
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#define | CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
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#define | CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS |
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#define | L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 ) |
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#define | L2C_310_INSTRUCTION_LINE_MASK |
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#define | L2C_310_NUM_WAYS 8 |
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#define | L2C_310_WAY_MASK ( ( 1 << L2C_310_NUM_WAYS ) - 1 ) |
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#define | L2C_310_MIN(a, b) ((a < b) ? (a) : (b)) |
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#define | L2C_310_MAX_LOCKING_BYTES (4 * 1024) |
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#define | L2C_310_RTL_RELEASE_R0_P0 0x0 |
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#define | L2C_310_RTL_RELEASE_R1_P0 0x2 |
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#define | L2C_310_RTL_RELEASE_R2_P0 0x4 |
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#define | L2C_310_RTL_RELEASE_R3_P0 0x5 |
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#define | L2C_310_RTL_RELEASE_R3_P1 0x6 |
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#define | L2C_310_RTL_RELEASE_R3_P2 0x8 |
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#define | L2C_310_RTL_RELEASE_R3_P3 0x9 |
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#define | BSP_ARM_L2C_310_RTL_RELEASE (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) |
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#define | L2C_310_ERRATA_IS_APPLICABLE_588369 |
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#define | CACHE_ARM_ERRATA_775420_HANDLER() |
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This group contains the L2C-310 cache support.
◆ CACHE_ARM_ERRATA_775420_HANDLER
#define CACHE_ARM_ERRATA_775420_HANDLER |
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Value: if( arm_errata_is_applicable_processor_errata_775420 ) { \
} \
◆ L2C_310_INSTRUCTION_LINE_MASK
#define L2C_310_INSTRUCTION_LINE_MASK |
Value: ( CPU_INSTRUCTION_CACHE_ALIGNMENT \
- 1 )
◆ l2c_310_lock
Initial value:
"L2-310 cache controller"
)
#define RTEMS_INTERRUPT_LOCK_INITIALIZER(_name)
Statically initializes an ISR lock object.
Definition: intr.h:909