RTEMS 6.1-rc6
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Macros | |
#define | IPS_DOMAIN_SLOT_CTRL_COUNT (38U) |
#define | IPS_DOMAIN_SLOT_CTRL_COUNT (38U) |
SLOT_CTRL - Slot Control Register | |
#define | IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK (0x8000U) |
#define | IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT (15U) |
#define | IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK (0x10000U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT (16U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK (0x20000U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT (17U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_USER(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK (0x80000000U) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT (31U) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK) |
SLOT_CTRL - Slot Control Register | |
#define | IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK (0x8000U) |
#define | IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT (15U) |
#define | IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK (0x10000U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT (16U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK (0x20000U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT (17U) |
#define | IPS_DOMAIN_SLOT_CTRL_ALLOW_USER(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK (0x80000000U) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT (31U) |
#define | IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK) |
#define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK) |
ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register 0b0..Do not allow non-secure write access 0b1..Allow non-secure write access
#define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK) |
ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register 0b0..Do not allow non-secure write access 0b1..Allow non-secure write access
#define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK) |
ALLOW_USER - Allow user write access to this domain control register or domain register 0b0..Do not allow user write access 0b1..Allow user write access
#define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK) |
ALLOW_USER - Allow user write access to this domain control register or domain register 0b0..Do not allow user write access 0b1..Allow user write access
#define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK) |
DOMAIN_LOCK - Lock domain ID of this slot 0b0..Do not lock the domain ID 0b1..Lock the domain ID
#define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK) |
DOMAIN_LOCK - Lock domain ID of this slot 0b0..Do not lock the domain ID 0b1..Lock the domain ID
#define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK) |
LOCK_CONTROL - Lock control of this slot 0b0..Do not lock the control register of this slot 0b1..Lock the control register of this slot
#define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK) |
LOCK_CONTROL - Lock control of this slot 0b0..Do not lock the control register of this slot 0b1..Lock the control register of this slot
#define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK) |
LOCKED_DOMAIN_ID - Domain ID of the slot to be locked
#define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK) |
LOCKED_DOMAIN_ID - Domain ID of the slot to be locked