Macros
#define	GPT_OCR_COUNT (3U)

#define	GPT_ICR_COUNT (2U)

#define	GPT_OCR_COUNT (3U)

#define	GPT_ICR_COUNT (2U)

#define	GPT_OCR_COUNT (3U)

#define	GPT_ICR_COUNT (2U)

CR - GPT Control Register
#define	GPT_CR_EN_MASK (0x1U)

#define	GPT_CR_EN_SHIFT (0U)

#define	GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)

#define	GPT_CR_ENMOD_MASK (0x2U)

#define	GPT_CR_ENMOD_SHIFT (1U)

#define	GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)

#define	GPT_CR_DBGEN_MASK (0x4U)

#define	GPT_CR_DBGEN_SHIFT (2U)

#define	GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)

#define	GPT_CR_WAITEN_MASK (0x8U)

#define	GPT_CR_WAITEN_SHIFT (3U)

#define	GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)

#define	GPT_CR_DOZEEN_MASK (0x10U)

#define	GPT_CR_DOZEEN_SHIFT (4U)

#define	GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)

#define	GPT_CR_STOPEN_MASK (0x20U)

#define	GPT_CR_STOPEN_SHIFT (5U)

#define	GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)

#define	GPT_CR_CLKSRC_MASK (0x1C0U)

#define	GPT_CR_CLKSRC_SHIFT (6U)

#define	GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)

#define	GPT_CR_FRR_MASK (0x200U)

#define	GPT_CR_FRR_SHIFT (9U)

#define	GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)

#define	GPT_CR_EN_24M_MASK (0x400U)

#define	GPT_CR_EN_24M_SHIFT (10U)

#define	GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)

#define	GPT_CR_SWR_MASK (0x8000U)

#define	GPT_CR_SWR_SHIFT (15U)

#define	GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)

#define	GPT_CR_IM1_MASK (0x30000U)

#define	GPT_CR_IM1_SHIFT (16U)

#define	GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)

#define	GPT_CR_IM2_MASK (0xC0000U)

#define	GPT_CR_IM2_SHIFT (18U)

#define	GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)

#define	GPT_CR_OM1_MASK (0x700000U)

#define	GPT_CR_OM1_SHIFT (20U)

#define	GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)

#define	GPT_CR_OM2_MASK (0x3800000U)

#define	GPT_CR_OM2_SHIFT (23U)

#define	GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)

#define	GPT_CR_OM3_MASK (0x1C000000U)

#define	GPT_CR_OM3_SHIFT (26U)

#define	GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)

#define	GPT_CR_FO1_MASK (0x20000000U)

#define	GPT_CR_FO1_SHIFT (29U)

#define	GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)

#define	GPT_CR_FO2_MASK (0x40000000U)

#define	GPT_CR_FO2_SHIFT (30U)

#define	GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)

#define	GPT_CR_FO3_MASK (0x80000000U)

#define	GPT_CR_FO3_SHIFT (31U)

#define	GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)

PR - GPT Prescaler Register
#define	GPT_PR_PRESCALER_MASK (0xFFFU)

#define	GPT_PR_PRESCALER_SHIFT (0U)

#define	GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)

#define	GPT_PR_PRESCALER24M_MASK (0xF000U)

#define	GPT_PR_PRESCALER24M_SHIFT (12U)

#define	GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)

SR - GPT Status Register
#define	GPT_SR_OF1_MASK (0x1U)

#define	GPT_SR_OF1_SHIFT (0U)

#define	GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)

#define	GPT_SR_OF2_MASK (0x2U)

#define	GPT_SR_OF2_SHIFT (1U)

#define	GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)

#define	GPT_SR_OF3_MASK (0x4U)

#define	GPT_SR_OF3_SHIFT (2U)

#define	GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)

#define	GPT_SR_IF1_MASK (0x8U)

#define	GPT_SR_IF1_SHIFT (3U)

#define	GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)

#define	GPT_SR_IF2_MASK (0x10U)

#define	GPT_SR_IF2_SHIFT (4U)

#define	GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)

#define	GPT_SR_ROV_MASK (0x20U)

#define	GPT_SR_ROV_SHIFT (5U)

#define	GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)

IR - GPT Interrupt Register
#define	GPT_IR_OF1IE_MASK (0x1U)

#define	GPT_IR_OF1IE_SHIFT (0U)

#define	GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)

#define	GPT_IR_OF2IE_MASK (0x2U)

#define	GPT_IR_OF2IE_SHIFT (1U)

#define	GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)

#define	GPT_IR_OF3IE_MASK (0x4U)

#define	GPT_IR_OF3IE_SHIFT (2U)

#define	GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)

#define	GPT_IR_IF1IE_MASK (0x8U)

#define	GPT_IR_IF1IE_SHIFT (3U)

#define	GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)

#define	GPT_IR_IF2IE_MASK (0x10U)

#define	GPT_IR_IF2IE_SHIFT (4U)

#define	GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)

#define	GPT_IR_ROVIE_MASK (0x20U)

#define	GPT_IR_ROVIE_SHIFT (5U)

#define	GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)

OCR - GPT Output Compare Register 1..GPT Output Compare Register 3
#define	GPT_OCR_COMP_MASK (0xFFFFFFFFU)

#define	GPT_OCR_COMP_SHIFT (0U)

#define	GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)

ICR - GPT Input Capture Register 1..GPT Input Capture Register 2
#define	GPT_ICR_CAPT_MASK (0xFFFFFFFFU)

#define	GPT_ICR_CAPT_SHIFT (0U)

#define	GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)

CNT - GPT Counter Register
#define	GPT_CNT_COUNT_MASK (0xFFFFFFFFU)

#define	GPT_CNT_COUNT_SHIFT (0U)

#define	GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)

CR - GPT Control Register
#define	GPT_CR_EN_MASK (0x1U)

#define	GPT_CR_EN_SHIFT (0U)

#define	GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)

#define	GPT_CR_ENMOD_MASK (0x2U)

#define	GPT_CR_ENMOD_SHIFT (1U)

#define	GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)

#define	GPT_CR_DBGEN_MASK (0x4U)

#define	GPT_CR_DBGEN_SHIFT (2U)

#define	GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)

#define	GPT_CR_WAITEN_MASK (0x8U)

#define	GPT_CR_WAITEN_SHIFT (3U)

#define	GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)

#define	GPT_CR_DOZEEN_MASK (0x10U)

#define	GPT_CR_DOZEEN_SHIFT (4U)

#define	GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)

#define	GPT_CR_STOPEN_MASK (0x20U)

#define	GPT_CR_STOPEN_SHIFT (5U)

#define	GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)

#define	GPT_CR_CLKSRC_MASK (0x1C0U)

#define	GPT_CR_CLKSRC_SHIFT (6U)

#define	GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)

#define	GPT_CR_FRR_MASK (0x200U)

#define	GPT_CR_FRR_SHIFT (9U)

#define	GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)

#define	GPT_CR_EN_24M_MASK (0x400U)

#define	GPT_CR_EN_24M_SHIFT (10U)

#define	GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)

#define	GPT_CR_SWR_MASK (0x8000U)

#define	GPT_CR_SWR_SHIFT (15U)

#define	GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)

#define	GPT_CR_IM1_MASK (0x30000U)

#define	GPT_CR_IM1_SHIFT (16U)

#define	GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)

#define	GPT_CR_IM2_MASK (0xC0000U)

#define	GPT_CR_IM2_SHIFT (18U)

#define	GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)

#define	GPT_CR_OM1_MASK (0x700000U)

#define	GPT_CR_OM1_SHIFT (20U)

#define	GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)

#define	GPT_CR_OM2_MASK (0x3800000U)

#define	GPT_CR_OM2_SHIFT (23U)

#define	GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)

#define	GPT_CR_OM3_MASK (0x1C000000U)

#define	GPT_CR_OM3_SHIFT (26U)

#define	GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)

#define	GPT_CR_FO1_MASK (0x20000000U)

#define	GPT_CR_FO1_SHIFT (29U)

#define	GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)

#define	GPT_CR_FO2_MASK (0x40000000U)

#define	GPT_CR_FO2_SHIFT (30U)

#define	GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)

#define	GPT_CR_FO3_MASK (0x80000000U)

#define	GPT_CR_FO3_SHIFT (31U)

#define	GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)

PR - GPT Prescaler Register
#define	GPT_PR_PRESCALER_MASK (0xFFFU)

#define	GPT_PR_PRESCALER_SHIFT (0U)

#define	GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)

#define	GPT_PR_PRESCALER24M_MASK (0xF000U)

#define	GPT_PR_PRESCALER24M_SHIFT (12U)

#define	GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)

SR - GPT Status Register
#define	GPT_SR_OF1_MASK (0x1U)

#define	GPT_SR_OF1_SHIFT (0U)

#define	GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)

#define	GPT_SR_OF2_MASK (0x2U)

#define	GPT_SR_OF2_SHIFT (1U)

#define	GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)

#define	GPT_SR_OF3_MASK (0x4U)

#define	GPT_SR_OF3_SHIFT (2U)

#define	GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)

#define	GPT_SR_IF1_MASK (0x8U)

#define	GPT_SR_IF1_SHIFT (3U)

#define	GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)

#define	GPT_SR_IF2_MASK (0x10U)

#define	GPT_SR_IF2_SHIFT (4U)

#define	GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)

#define	GPT_SR_ROV_MASK (0x20U)

#define	GPT_SR_ROV_SHIFT (5U)

#define	GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)

IR - GPT Interrupt Register
#define	GPT_IR_OF1IE_MASK (0x1U)

#define	GPT_IR_OF1IE_SHIFT (0U)

#define	GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)

#define	GPT_IR_OF2IE_MASK (0x2U)

#define	GPT_IR_OF2IE_SHIFT (1U)

#define	GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)

#define	GPT_IR_OF3IE_MASK (0x4U)

#define	GPT_IR_OF3IE_SHIFT (2U)

#define	GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)

#define	GPT_IR_IF1IE_MASK (0x8U)

#define	GPT_IR_IF1IE_SHIFT (3U)

#define	GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)

#define	GPT_IR_IF2IE_MASK (0x10U)

#define	GPT_IR_IF2IE_SHIFT (4U)

#define	GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)

#define	GPT_IR_ROVIE_MASK (0x20U)

#define	GPT_IR_ROVIE_SHIFT (5U)

#define	GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)

OCR - GPT Output Compare Register
#define	GPT_OCR_COMP_MASK (0xFFFFFFFFU)

#define	GPT_OCR_COMP_SHIFT (0U)

#define	GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)

ICR - GPT Input Capture Register
#define	GPT_ICR_CAPT_MASK (0xFFFFFFFFU)

#define	GPT_ICR_CAPT_SHIFT (0U)

#define	GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)

CNT - GPT Counter Register
#define	GPT_CNT_COUNT_MASK (0xFFFFFFFFU)

#define	GPT_CNT_COUNT_SHIFT (0U)

#define	GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)

CR - GPT Control Register
#define	GPT_CR_EN_MASK (0x1U)

#define	GPT_CR_EN_SHIFT (0U)

#define	GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)

#define	GPT_CR_ENMOD_MASK (0x2U)

#define	GPT_CR_ENMOD_SHIFT (1U)

#define	GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)

#define	GPT_CR_DBGEN_MASK (0x4U)

#define	GPT_CR_DBGEN_SHIFT (2U)

#define	GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)

#define	GPT_CR_WAITEN_MASK (0x8U)

#define	GPT_CR_WAITEN_SHIFT (3U)

#define	GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)

#define	GPT_CR_DOZEEN_MASK (0x10U)

#define	GPT_CR_DOZEEN_SHIFT (4U)

#define	GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)

#define	GPT_CR_STOPEN_MASK (0x20U)

#define	GPT_CR_STOPEN_SHIFT (5U)

#define	GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)

#define	GPT_CR_CLKSRC_MASK (0x1C0U)

#define	GPT_CR_CLKSRC_SHIFT (6U)

#define	GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)

#define	GPT_CR_FRR_MASK (0x200U)

#define	GPT_CR_FRR_SHIFT (9U)

#define	GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)

#define	GPT_CR_EN_24M_MASK (0x400U)

#define	GPT_CR_EN_24M_SHIFT (10U)

#define	GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)

#define	GPT_CR_SWR_MASK (0x8000U)

#define	GPT_CR_SWR_SHIFT (15U)

#define	GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)

#define	GPT_CR_IM1_MASK (0x30000U)

#define	GPT_CR_IM1_SHIFT (16U)

#define	GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)

#define	GPT_CR_IM2_MASK (0xC0000U)

#define	GPT_CR_IM2_SHIFT (18U)

#define	GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)

#define	GPT_CR_OM1_MASK (0x700000U)

#define	GPT_CR_OM1_SHIFT (20U)

#define	GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)

#define	GPT_CR_OM2_MASK (0x3800000U)

#define	GPT_CR_OM2_SHIFT (23U)

#define	GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)

#define	GPT_CR_OM3_MASK (0x1C000000U)

#define	GPT_CR_OM3_SHIFT (26U)

#define	GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)

#define	GPT_CR_FO1_MASK (0x20000000U)

#define	GPT_CR_FO1_SHIFT (29U)

#define	GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)

#define	GPT_CR_FO2_MASK (0x40000000U)

#define	GPT_CR_FO2_SHIFT (30U)

#define	GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)

#define	GPT_CR_FO3_MASK (0x80000000U)

#define	GPT_CR_FO3_SHIFT (31U)

#define	GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)

PR - GPT Prescaler Register
#define	GPT_PR_PRESCALER_MASK (0xFFFU)

#define	GPT_PR_PRESCALER_SHIFT (0U)

#define	GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)

#define	GPT_PR_PRESCALER24M_MASK (0xF000U)

#define	GPT_PR_PRESCALER24M_SHIFT (12U)

#define	GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)

SR - GPT Status Register
#define	GPT_SR_OF1_MASK (0x1U)

#define	GPT_SR_OF1_SHIFT (0U)

#define	GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)

#define	GPT_SR_OF2_MASK (0x2U)

#define	GPT_SR_OF2_SHIFT (1U)

#define	GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)

#define	GPT_SR_OF3_MASK (0x4U)

#define	GPT_SR_OF3_SHIFT (2U)

#define	GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)

#define	GPT_SR_IF1_MASK (0x8U)

#define	GPT_SR_IF1_SHIFT (3U)

#define	GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)

#define	GPT_SR_IF2_MASK (0x10U)

#define	GPT_SR_IF2_SHIFT (4U)

#define	GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)

#define	GPT_SR_ROV_MASK (0x20U)

#define	GPT_SR_ROV_SHIFT (5U)

#define	GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)

IR - GPT Interrupt Register
#define	GPT_IR_OF1IE_MASK (0x1U)

#define	GPT_IR_OF1IE_SHIFT (0U)

#define	GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)

#define	GPT_IR_OF2IE_MASK (0x2U)

#define	GPT_IR_OF2IE_SHIFT (1U)

#define	GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)

#define	GPT_IR_OF3IE_MASK (0x4U)

#define	GPT_IR_OF3IE_SHIFT (2U)

#define	GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)

#define	GPT_IR_IF1IE_MASK (0x8U)

#define	GPT_IR_IF1IE_SHIFT (3U)

#define	GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)

#define	GPT_IR_IF2IE_MASK (0x10U)

#define	GPT_IR_IF2IE_SHIFT (4U)

#define	GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)

#define	GPT_IR_ROVIE_MASK (0x20U)

#define	GPT_IR_ROVIE_SHIFT (5U)

#define	GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)

OCR - GPT Output Compare Register
#define	GPT_OCR_COMP_MASK (0xFFFFFFFFU)

#define	GPT_OCR_COMP_SHIFT (0U)

#define	GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)

ICR - GPT Input Capture Register
#define	GPT_ICR_CAPT_MASK (0xFFFFFFFFU)

#define	GPT_ICR_CAPT_SHIFT (0U)

#define	GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)

CNT - GPT Counter Register
#define	GPT_CNT_COUNT_MASK (0xFFFFFFFFU)

#define	GPT_CNT_COUNT_SHIFT (0U)

#define	GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)

Detailed Description

Macro Definition Documentation

◆ GPT_CNT_COUNT [1/2]

#define GPT_CNT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)

COUNT - Counter Value

◆ GPT_CNT_COUNT [2/2]

#define GPT_CNT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)

COUNT - Counter Value

◆ GPT_CR_CLKSRC [1/3]

#define GPT_CR_CLKSRC ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)

CLKSRC 0b000..No clock 0b001..Peripheral Clock (ipg_clk) 0b010..High Frequency Reference Clock (ipg_clk_highfreq) 0b011..External Clock 0b100..Low Frequency Reference Clock (ipg_clk_32k) 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)

◆ GPT_CR_CLKSRC [2/3]

#define GPT_CR_CLKSRC ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)

CLKSRC - Clock Source Select 0b000..No clock 0b001..Peripheral Clock (ipg_clk) 0b010..High Frequency Reference Clock (ipg_clk_highfreq) 0b011..External Clock 0b100..Low Frequency Reference Clock (ipg_clk_32k) 0b101..Oscillator as Reference Clock (ipg_clk_16M)

◆ GPT_CR_CLKSRC [3/3]

#define GPT_CR_CLKSRC ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)

CLKSRC - Clock Source Select 0b000..No clock 0b001..Peripheral Clock (ipg_clk) 0b010..High Frequency Reference Clock (ipg_clk_highfreq) 0b011..External Clock 0b100..Low Frequency Reference Clock (ipg_clk_32k) 0b101..Oscillator as Reference Clock (ipg_clk_16M)

◆ GPT_CR_DBGEN [1/3]

#define GPT_CR_DBGEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)

DBGEN 0b0..GPT is disabled in debug mode. 0b1..GPT is enabled in debug mode.

◆ GPT_CR_DBGEN [2/3]

#define GPT_CR_DBGEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)

DBGEN - GPT Debug Mode Enable 0b0..Disable in Debug mode 0b1..Enable in Debug mode

◆ GPT_CR_DBGEN [3/3]

#define GPT_CR_DBGEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)

DBGEN - GPT Debug Mode Enable 0b0..Disable in Debug mode 0b1..Enable in Debug mode

◆ GPT_CR_DOZEEN [1/3]

#define GPT_CR_DOZEEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)

DOZEEN 0b0..GPT is disabled in doze mode. 0b1..GPT is enabled in doze mode.

◆ GPT_CR_DOZEEN [2/3]

#define GPT_CR_DOZEEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)

DOZEEN - GPT Doze Mode Enable 0b0..Disable in Doze mode 0b1..Enable in Doze mode

◆ GPT_CR_DOZEEN [3/3]

#define GPT_CR_DOZEEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)

DOZEEN - GPT Doze Mode Enable 0b0..Disable in Doze mode 0b1..Enable in Doze mode

◆ GPT_CR_EN [1/3]

#define GPT_CR_EN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)

EN 0b0..GPT is disabled. 0b1..GPT is enabled.

◆ GPT_CR_EN [2/3]

#define GPT_CR_EN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)

EN - GPT Enable 0b0..Disable 0b1..Enable

◆ GPT_CR_EN [3/3]

#define GPT_CR_EN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)

EN - GPT Enable 0b0..Disable 0b1..Enable

◆ GPT_CR_EN_24M [1/3]

#define GPT_CR_EN_24M ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)

EN_24M 0b0..24M clock disabled 0b1..24M clock enabled

◆ GPT_CR_EN_24M [2/3]

#define GPT_CR_EN_24M ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)

EN_24M - Enable Oscillator Clock Input 0b0..Disable 0b1..Enable

◆ GPT_CR_EN_24M [3/3]

#define GPT_CR_EN_24M ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)

EN_24M - Enable Oscillator Clock Input 0b0..Disable 0b1..Enable

◆ GPT_CR_ENMOD [1/3]

#define GPT_CR_ENMOD ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)

ENMOD 0b0..GPT counter will retain its value when it is disabled. 0b1..GPT counter value is reset to 0 when it is disabled.

◆ GPT_CR_ENMOD [2/3]

#define GPT_CR_ENMOD ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)

ENMOD - GPT Enable Mode 0b0..Restart counting from their frozen values after GPT is enabled (EN=1). 0b1..Reset counting from 0 after GPT is enabled (EN=1).

◆ GPT_CR_ENMOD [3/3]

#define GPT_CR_ENMOD ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)

ENMOD - GPT Enable Mode 0b0..Restart counting from their frozen values after GPT is enabled (EN=1). 0b1..Reset counting from 0 after GPT is enabled (EN=1).

◆ GPT_CR_FO1 [1/2]

#define GPT_CR_FO1 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)

FO1 - Force Output Compare for Channel 1 0b0..No effect 0b1..Trigger the programmed response on the pin

◆ GPT_CR_FO1 [2/2]

#define GPT_CR_FO1 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)

FO1 - Force Output Compare for Channel 1 0b0..No effect 0b1..Trigger the programmed response on the pin

◆ GPT_CR_FO2 [1/2]

#define GPT_CR_FO2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)

FO2 - Force Output Compare for Channel 2 0b0..No effect 0b1..Trigger the programmed response on the pin

◆ GPT_CR_FO2 [2/2]

#define GPT_CR_FO2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)

FO2 - Force Output Compare for Channel 2 0b0..No effect 0b1..Trigger the programmed response on the pin

◆ GPT_CR_FO3 [1/3]

#define GPT_CR_FO3 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)

FO3 0b0..Writing a 0 has no effect. 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.

◆ GPT_CR_FO3 [2/3]

#define GPT_CR_FO3 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)

FO3 - Force Output Compare for Channel 3 0b0..No effect 0b1..Trigger the programmed response on the pin

◆ GPT_CR_FO3 [3/3]

#define GPT_CR_FO3 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)

FO3 - Force Output Compare for Channel 3 0b0..No effect 0b1..Trigger the programmed response on the pin

◆ GPT_CR_FRR [1/3]

#define GPT_CR_FRR ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)

FRR 0b0..Restart mode 0b1..Free-Run mode

◆ GPT_CR_FRR [2/3]

#define GPT_CR_FRR ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)

FRR - Free-Run or Restart Mode 0b0..Restart mode. After a compare event, the counter resets to 0x0000_0000 and resumes counting. 0b1..Free-Run mode. After a compare event, the counter continues counting until 0xFFFF_FFFF and then rolls over to 0.

◆ GPT_CR_FRR [3/3]

#define GPT_CR_FRR ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)

FRR - Free-Run or Restart Mode 0b0..Restart mode. After a compare event, the counter resets to 0x0000_0000 and resumes counting. 0b1..Free-Run mode. After a compare event, the counter continues counting until 0xFFFF_FFFF and then rolls over to 0.

◆ GPT_CR_IM1 [1/2]

#define GPT_CR_IM1 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)

IM1 - Input Capture Operating Mode for Channel 1 0b00..Capture disabled 0b01..Capture on rising edge only 0b10..Capture on falling edge only 0b11..Capture on both edges

◆ GPT_CR_IM1 [2/2]

#define GPT_CR_IM1 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)

IM1 - Input Capture Operating Mode for Channel 1 0b00..Capture disabled 0b01..Capture on rising edge only 0b10..Capture on falling edge only 0b11..Capture on both edges

◆ GPT_CR_IM2 [1/3]

#define GPT_CR_IM2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)

IM2 0b00..capture disabled 0b01..capture on rising edge only 0b10..capture on falling edge only 0b11..capture on both edges

◆ GPT_CR_IM2 [2/3]

#define GPT_CR_IM2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)

IM2 - Input Capture Operating Mode for Channel 2 0b00..Capture disabled 0b01..Capture on rising edge only 0b10..Capture on falling edge only 0b11..Capture on both edges

◆ GPT_CR_IM2 [3/3]

#define GPT_CR_IM2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)

IM2 - Input Capture Operating Mode for Channel 2 0b00..Capture disabled 0b01..Capture on rising edge only 0b10..Capture on falling edge only 0b11..Capture on both edges

◆ GPT_CR_OM1 [1/2]

#define GPT_CR_OM1 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)

OM1 - Output Compare Operating Mode for Channel 1 0b000..Output disabled. No response on pin. 0b001..Toggle output pin 0b010..Clear output pin 0b011..Set output pin 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register.

◆ GPT_CR_OM1 [2/2]

#define GPT_CR_OM1 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)

OM1 - Output Compare Operating Mode for Channel 1 0b000..Output disabled. No response on pin. 0b001..Toggle output pin 0b010..Clear output pin 0b011..Set output pin 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register.

◆ GPT_CR_OM2 [1/2]

#define GPT_CR_OM2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)

OM2 - Output Compare Operating Mode for Channel 2 0b000..Output disabled. No response on pin. 0b001..Toggle output pin 0b010..Clear output pin 0b011..Set output pin 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register.

◆ GPT_CR_OM2 [2/2]

#define GPT_CR_OM2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)

OM2 - Output Compare Operating Mode for Channel 2 0b000..Output disabled. No response on pin. 0b001..Toggle output pin 0b010..Clear output pin 0b011..Set output pin 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register.

◆ GPT_CR_OM3 [1/3]

#define GPT_CR_OM3 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)

OM3 0b000..Output disconnected. No response on pin. 0b001..Toggle output pin 0b010..Clear output pin 0b011..Set output pin 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.

◆ GPT_CR_OM3 [2/3]

#define GPT_CR_OM3 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)

OM3 - Output Compare Operating Mode for Channel 3 0b000..Output disabled. No response on pin. 0b001..Toggle output pin 0b010..Clear output pin 0b011..Set output pin 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register.

◆ GPT_CR_OM3 [3/3]

#define GPT_CR_OM3 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)

OM3 - Output Compare Operating Mode for Channel 3 0b000..Output disabled. No response on pin. 0b001..Toggle output pin 0b010..Clear output pin 0b011..Set output pin 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already). "Input clock" here refers to the clock selected by the CLKSRC field of this register.

◆ GPT_CR_STOPEN [1/3]

#define GPT_CR_STOPEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)

STOPEN 0b0..GPT is disabled in Stop mode. 0b1..GPT is enabled in Stop mode.

◆ GPT_CR_STOPEN [2/3]

#define GPT_CR_STOPEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)

STOPEN - GPT Stop Mode Enable 0b0..Disable in Stop mode 0b1..Enable in Stop mode

◆ GPT_CR_STOPEN [3/3]

#define GPT_CR_STOPEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)

STOPEN - GPT Stop Mode Enable 0b0..Disable in Stop mode 0b1..Enable in Stop mode

◆ GPT_CR_SWR [1/3]

#define GPT_CR_SWR ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)

SWR 0b0..GPT is not in reset state 0b1..GPT is in reset state

◆ GPT_CR_SWR [2/3]

#define GPT_CR_SWR ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)

SWR - Software Reset 0b0..GPT is not in software reset state 0b1..GPT is in software reset state

◆ GPT_CR_SWR [3/3]

#define GPT_CR_SWR ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)

SWR - Software Reset 0b0..GPT is not in software reset state 0b1..GPT is in software reset state

◆ GPT_CR_WAITEN [1/3]

#define GPT_CR_WAITEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)

WAITEN 0b0..GPT is disabled in wait mode. 0b1..GPT is enabled in wait mode.

◆ GPT_CR_WAITEN [2/3]

#define GPT_CR_WAITEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)

WAITEN - GPT Wait Mode Enable 0b0..Disable in Wait mode 0b1..Enable in Wait mode

◆ GPT_CR_WAITEN [3/3]

#define GPT_CR_WAITEN ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)

WAITEN - GPT Wait Mode Enable 0b0..Disable in Wait mode 0b1..Enable in Wait mode

◆ GPT_ICR_CAPT [1/2]

#define GPT_ICR_CAPT ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)

CAPT - Capture Value

◆ GPT_ICR_CAPT [2/2]

#define GPT_ICR_CAPT ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)

CAPT - Capture Value

◆ GPT_IR_IF1IE [1/2]

#define GPT_IR_IF1IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)

IF1IE - Input Capture Flag for Channel 1 Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_IR_IF1IE [2/2]

#define GPT_IR_IF1IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)

IF1IE - Input Capture Flag for Channel 1 Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_IR_IF2IE [1/3]

#define GPT_IR_IF2IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)

IF2IE 0b0..IF2IE Input Capture n Interrupt Enable is disabled. 0b1..IF2IE Input Capture n Interrupt Enable is enabled.

◆ GPT_IR_IF2IE [2/3]

#define GPT_IR_IF2IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)

IF2IE - Input Capture Flag for Channel 2 Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_IR_IF2IE [3/3]

#define GPT_IR_IF2IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)

IF2IE - Input Capture Flag for Channel 2 Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_IR_OF1IE [1/2]

#define GPT_IR_OF1IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)

OF1IE - Output Compare Flag for Channel 1 Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_IR_OF1IE [2/2]

#define GPT_IR_OF1IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)

OF1IE - Output Compare Flag for Channel 1 Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_IR_OF2IE [1/2]

#define GPT_IR_OF2IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)

OF2IE - Output Compare Flag for Channel 2 Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_IR_OF2IE [2/2]

#define GPT_IR_OF2IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)

OF2IE - Output Compare Flag for Channel 2 Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_IR_OF3IE [1/3]

#define GPT_IR_OF3IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)

OF3IE 0b0..Output Compare Channel n interrupt is disabled. 0b1..Output Compare Channel n interrupt is enabled.

◆ GPT_IR_OF3IE [2/3]

#define GPT_IR_OF3IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)

OF3IE - Output Compare Flag for Channel 3 Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_IR_OF3IE [3/3]

#define GPT_IR_OF3IE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)

OF3IE - Output Compare Flag for Channel 3 Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_IR_ROVIE [1/3]

#define GPT_IR_ROVIE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)

ROVIE 0b0..Rollover interrupt is disabled. 0b1..Rollover interrupt enabled.

◆ GPT_IR_ROVIE [2/3]

#define GPT_IR_ROVIE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)

ROVIE - Rollover Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_IR_ROVIE [3/3]

#define GPT_IR_ROVIE ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)

ROVIE - Rollover Interrupt Enable 0b0..Disable 0b1..Enable

◆ GPT_OCR_COMP [1/2]

#define GPT_OCR_COMP ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)

COMP - Compare Value

◆ GPT_OCR_COMP [2/2]

#define GPT_OCR_COMP ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)

COMP - Compare Value

◆ GPT_PR_PRESCALER [1/3]

#define GPT_PR_PRESCALER ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)

PRESCALER 0b000000000000..Divide by 1 0b000000000001..Divide by 2 0b111111111111..Divide by 4096

◆ GPT_PR_PRESCALER [2/3]

#define GPT_PR_PRESCALER ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)

PRESCALER - Prescaler divide value 0b000000000000..Divide by 1 0b000000000001..Divide by 2 0b111111111111..Divide by 4096

◆ GPT_PR_PRESCALER [3/3]

#define GPT_PR_PRESCALER ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)

PRESCALER - Prescaler divide value 0b000000000000..Divide by 1 0b000000000001..Divide by 2 0b111111111111..Divide by 4096

◆ GPT_PR_PRESCALER24M [1/3]

#define GPT_PR_PRESCALER24M ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)

PRESCALER24M 0b0000..Divide by 1 0b0001..Divide by 2 0b1111..Divide by 16

◆ GPT_PR_PRESCALER24M [2/3]

#define GPT_PR_PRESCALER24M ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)

PRESCALER24M - Prescaler divide value for the oscillator clock 0b0000..Divide by 1 0b0001..Divide by 2 0b1111..Divide by 16

◆ GPT_PR_PRESCALER24M [3/3]

#define GPT_PR_PRESCALER24M ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)

PRESCALER24M - Prescaler divide value for the oscillator clock 0b0000..Divide by 1 0b0001..Divide by 2 0b1111..Divide by 16

◆ GPT_SR_IF1 [1/2]

#define GPT_SR_IF1 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)

IF1 - Input Capture Flag for Channel 1 0b0..Capture event has not occurred. 0b1..Capture event has occurred.

◆ GPT_SR_IF1 [2/2]

#define GPT_SR_IF1 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)

IF1 - Input Capture Flag for Channel 1 0b0..Capture event has not occurred. 0b1..Capture event has occurred.

◆ GPT_SR_IF2 [1/3]

#define GPT_SR_IF2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)

IF2 0b0..Capture event has not occurred. 0b1..Capture event has occurred.

◆ GPT_SR_IF2 [2/3]

#define GPT_SR_IF2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)

IF2 - Input Capture Flag for Channel 2 0b0..Capture event has not occurred. 0b1..Capture event has occurred.

◆ GPT_SR_IF2 [3/3]

#define GPT_SR_IF2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)

IF2 - Input Capture Flag for Channel 2 0b0..Capture event has not occurred. 0b1..Capture event has occurred.

◆ GPT_SR_OF1 [1/2]

#define GPT_SR_OF1 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)

OF1 - Output Compare Flag for Channel 1 0b0..Compare event has not occurred. 0b1..Compare event has occurred.

◆ GPT_SR_OF1 [2/2]

#define GPT_SR_OF1 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)

OF1 - Output Compare Flag for Channel 1 0b0..Compare event has not occurred. 0b1..Compare event has occurred.

◆ GPT_SR_OF2 [1/2]

#define GPT_SR_OF2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)

OF2 - Output Compare Flag for Channel 2 0b0..Compare event has not occurred. 0b1..Compare event has occurred.

◆ GPT_SR_OF2 [2/2]

#define GPT_SR_OF2 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)

OF2 - Output Compare Flag for Channel 2 0b0..Compare event has not occurred. 0b1..Compare event has occurred.

◆ GPT_SR_OF3 [1/3]

#define GPT_SR_OF3 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)

OF3 0b0..Compare event has not occurred. 0b1..Compare event has occurred.

◆ GPT_SR_OF3 [2/3]

#define GPT_SR_OF3 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)

OF3 - Output Compare Flag for Channel 3 0b0..Compare event has not occurred. 0b1..Compare event has occurred.

◆ GPT_SR_OF3 [3/3]

#define GPT_SR_OF3 ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)

OF3 - Output Compare Flag for Channel 3 0b0..Compare event has not occurred. 0b1..Compare event has occurred.

◆ GPT_SR_ROV [1/3]

#define GPT_SR_ROV ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)

ROV 0b0..Rollover has not occurred. 0b1..Rollover has occurred.

◆ GPT_SR_ROV [2/3]

#define GPT_SR_ROV ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)

ROV - Rollover Flag 0b0..Rollover has not occurred. 0b1..Rollover has occurred.

◆ GPT_SR_ROV [3/3]

#define GPT_SR_ROV ( x ) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)

ROV - Rollover Flag 0b0..Rollover has not occurred. 0b1..Rollover has occurred.

Macros

CR - GPT Control Register

PR - GPT Prescaler Register

SR - GPT Status Register

IR - GPT Interrupt Register

OCR - GPT Output Compare Register 1..GPT Output Compare Register 3

ICR - GPT Input Capture Register 1..GPT Input Capture Register 2

CNT - GPT Counter Register

CR - GPT Control Register

PR - GPT Prescaler Register

SR - GPT Status Register

IR - GPT Interrupt Register

OCR - GPT Output Compare Register

ICR - GPT Input Capture Register

CNT - GPT Counter Register

CR - GPT Control Register

PR - GPT Prescaler Register

SR - GPT Status Register

IR - GPT Interrupt Register

OCR - GPT Output Compare Register

ICR - GPT Input Capture Register

CNT - GPT Counter Register

Detailed Description

Macro Definition Documentation

◆ GPT_CNT_COUNT [1/2]

◆ GPT_CNT_COUNT [2/2]

◆ GPT_CR_CLKSRC [1/3]

◆ GPT_CR_CLKSRC [2/3]

◆ GPT_CR_CLKSRC [3/3]

◆ GPT_CR_DBGEN [1/3]

◆ GPT_CR_DBGEN [2/3]

◆ GPT_CR_DBGEN [3/3]

◆ GPT_CR_DOZEEN [1/3]

◆ GPT_CR_DOZEEN [2/3]

◆ GPT_CR_DOZEEN [3/3]

◆ GPT_CR_EN [1/3]

◆ GPT_CR_EN [2/3]

◆ GPT_CR_EN [3/3]

◆ GPT_CR_EN_24M [1/3]

◆ GPT_CR_EN_24M [2/3]

◆ GPT_CR_EN_24M [3/3]

◆ GPT_CR_ENMOD [1/3]

◆ GPT_CR_ENMOD [2/3]

◆ GPT_CR_ENMOD [3/3]

◆ GPT_CR_FO1 [1/2]

◆ GPT_CR_FO1 [2/2]

◆ GPT_CR_FO2 [1/2]

◆ GPT_CR_FO2 [2/2]

◆ GPT_CR_FO3 [1/3]

◆ GPT_CR_FO3 [2/3]

◆ GPT_CR_FO3 [3/3]

◆ GPT_CR_FRR [1/3]

◆ GPT_CR_FRR [2/3]

◆ GPT_CR_FRR [3/3]

◆ GPT_CR_IM1 [1/2]

◆ GPT_CR_IM1 [2/2]

◆ GPT_CR_IM2 [1/3]

◆ GPT_CR_IM2 [2/3]

◆ GPT_CR_IM2 [3/3]

◆ GPT_CR_OM1 [1/2]

◆ GPT_CR_OM1 [2/2]

◆ GPT_CR_OM2 [1/2]

◆ GPT_CR_OM2 [2/2]

◆ GPT_CR_OM3 [1/3]

◆ GPT_CR_OM3 [2/3]

◆ GPT_CR_OM3 [3/3]

◆ GPT_CR_STOPEN [1/3]

◆ GPT_CR_STOPEN [2/3]

◆ GPT_CR_STOPEN [3/3]

◆ GPT_CR_SWR [1/3]

◆ GPT_CR_SWR [2/3]

◆ GPT_CR_SWR [3/3]

◆ GPT_CR_WAITEN [1/3]

◆ GPT_CR_WAITEN [2/3]

◆ GPT_CR_WAITEN [3/3]

◆ GPT_ICR_CAPT [1/2]

◆ GPT_ICR_CAPT [2/2]

◆ GPT_IR_IF1IE [1/2]

◆ GPT_IR_IF1IE [2/2]

◆ GPT_IR_IF2IE [1/3]