ENC Peripheral Access Layer

Modules
	ENC Register Masks

Data Structures
struct	ENC_Type

Macros
#define	ENC1_BASE   (0x403C8000u)
#define	ENC1   ((ENC_Type *)ENC1_BASE)
#define	ENC2_BASE   (0x403CC000u)
#define	ENC2   ((ENC_Type *)ENC2_BASE)
#define	ENC3_BASE   (0x403D0000u)
#define	ENC3   ((ENC_Type *)ENC3_BASE)
#define	ENC4_BASE   (0x403D4000u)
#define	ENC4   ((ENC_Type *)ENC4_BASE)
#define	ENC_BASE_ADDRS   { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
#define	ENC_BASE_PTRS   { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
#define	ENC_COMPARE_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_HOME_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_WDOG_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_INDEX_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_INPUT_SWITCH_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC1_BASE   (0x40174000u)
#define	ENC1   ((ENC_Type *)ENC1_BASE)
#define	ENC2_BASE   (0x40178000u)
#define	ENC2   ((ENC_Type *)ENC2_BASE)
#define	ENC3_BASE   (0x4017C000u)
#define	ENC3   ((ENC_Type *)ENC3_BASE)
#define	ENC4_BASE   (0x40180000u)
#define	ENC4   ((ENC_Type *)ENC4_BASE)
#define	ENC_BASE_ADDRS   { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
#define	ENC_BASE_PTRS   { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
#define	ENC_COMPARE_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_HOME_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_WDOG_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_INDEX_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_INPUT_SWITCH_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC1_BASE   (0x40174000u)
#define	ENC1   ((ENC_Type *)ENC1_BASE)
#define	ENC2_BASE   (0x40178000u)
#define	ENC2   ((ENC_Type *)ENC2_BASE)
#define	ENC3_BASE   (0x4017C000u)
#define	ENC3   ((ENC_Type *)ENC3_BASE)
#define	ENC4_BASE   (0x40180000u)
#define	ENC4   ((ENC_Type *)ENC4_BASE)
#define	ENC_BASE_ADDRS   { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
#define	ENC_BASE_PTRS   { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
#define	ENC_COMPARE_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_HOME_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_WDOG_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_INDEX_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define	ENC_INPUT_SWITCH_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }

Detailed Description

Macro Definition Documentation

ENC1 [1/3]

#define ENC1   ((ENC_Type *)ENC1_BASE)

Peripheral ENC1 base pointer

ENC1 [2/3]

#define ENC1   ((ENC_Type *)ENC1_BASE)

Peripheral ENC1 base pointer

ENC1 [3/3]

#define ENC1   ((ENC_Type *)ENC1_BASE)

Peripheral ENC1 base pointer

ENC1_BASE [1/3]

#define ENC1_BASE   (0x403C8000u)

Peripheral ENC1 base address

ENC1_BASE [2/3]

#define ENC1_BASE   (0x40174000u)

Peripheral ENC1 base address

ENC1_BASE [3/3]

#define ENC1_BASE   (0x40174000u)

Peripheral ENC1 base address

ENC2 [1/3]

#define ENC2   ((ENC_Type *)ENC2_BASE)

Peripheral ENC2 base pointer

ENC2 [2/3]

#define ENC2   ((ENC_Type *)ENC2_BASE)

Peripheral ENC2 base pointer

ENC2 [3/3]

#define ENC2   ((ENC_Type *)ENC2_BASE)

Peripheral ENC2 base pointer

ENC2_BASE [1/3]

#define ENC2_BASE   (0x403CC000u)

Peripheral ENC2 base address

ENC2_BASE [2/3]

#define ENC2_BASE   (0x40178000u)

Peripheral ENC2 base address

ENC2_BASE [3/3]

#define ENC2_BASE   (0x40178000u)

Peripheral ENC2 base address

ENC3 [1/3]

#define ENC3   ((ENC_Type *)ENC3_BASE)

Peripheral ENC3 base pointer

ENC3 [2/3]

#define ENC3   ((ENC_Type *)ENC3_BASE)

Peripheral ENC3 base pointer

ENC3 [3/3]

#define ENC3   ((ENC_Type *)ENC3_BASE)

Peripheral ENC3 base pointer

ENC3_BASE [1/3]

#define ENC3_BASE   (0x403D0000u)

Peripheral ENC3 base address

ENC3_BASE [2/3]

#define ENC3_BASE   (0x4017C000u)

Peripheral ENC3 base address

ENC3_BASE [3/3]

#define ENC3_BASE   (0x4017C000u)

Peripheral ENC3 base address

ENC4 [1/3]

#define ENC4   ((ENC_Type *)ENC4_BASE)

Peripheral ENC4 base pointer

ENC4 [2/3]

#define ENC4   ((ENC_Type *)ENC4_BASE)

Peripheral ENC4 base pointer

ENC4 [3/3]

#define ENC4   ((ENC_Type *)ENC4_BASE)

Peripheral ENC4 base pointer

ENC4_BASE [1/3]

#define ENC4_BASE   (0x403D4000u)

Peripheral ENC4 base address

ENC4_BASE [2/3]

#define ENC4_BASE   (0x40180000u)

Peripheral ENC4 base address

ENC4_BASE [3/3]

#define ENC4_BASE   (0x40180000u)

Peripheral ENC4 base address

ENC_BASE_ADDRS [1/3]

#define ENC_BASE_ADDRS   { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }

Array initializer of ENC peripheral base addresses

ENC_BASE_ADDRS [2/3]

#define ENC_BASE_ADDRS   { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }

Array initializer of ENC peripheral base addresses

ENC_BASE_ADDRS [3/3]

#define ENC_BASE_ADDRS   { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }

Array initializer of ENC peripheral base addresses

ENC_BASE_PTRS [1/3]

#define ENC_BASE_PTRS   { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }

Array initializer of ENC peripheral base pointers

ENC_BASE_PTRS [2/3]

#define ENC_BASE_PTRS   { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }

Array initializer of ENC peripheral base pointers

ENC_BASE_PTRS [3/3]

#define ENC_BASE_PTRS   { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }

Array initializer of ENC peripheral base pointers

ENC_COMPARE_IRQS [1/3]

#define ENC_COMPARE_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }

Interrupt vectors for the ENC peripheral type

ENC_COMPARE_IRQS [2/3]

#define ENC_COMPARE_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }

Interrupt vectors for the ENC peripheral type

ENC_COMPARE_IRQS [3/3]

#define ENC_COMPARE_IRQS   { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }

Interrupt vectors for the ENC peripheral type