This group contains the Interrupt Manager implementation parts specific to the ARM Generic Interrupt Controller. More...

Files
file	arm-gic-arch.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support specific to the AArch64 architecture.

file	arm-gic-arch.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support specific to the Arm architecture.

file	arm-gic-irq.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support.

file	arm-gic-regs.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) memory-mapped registers.

file	arm-gic-tm27.h
	This header file provides the TM27 support for the ARM Generic Interrupt Controller (GIC).

file	arm-gic.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support.

file	arm-gicv3.h
	This header file provides interfaces of the ARM Generic Interrupt Controller (GIC) support specific to the GICv3.

file	arm-gicv2-get-attributes.c
	This source file contains the implementation of bsp_interrupt_get_attributes() for the GICv2.

file	arm-gicv2-zynqmp.c
	This source file contains the implementation of bsp_interrupt_get_attributes() for the GICv2 of Xilinx Zynq UltraScale+ MPSoC and RFSoC devices.

file	arm-gicv2.c
	This source file contains the implementation of the generic GICv2 support.

file	arm-gicv3.c
	This source file contains the implementation of the generic GICv3 support.

Data Structures
struct	gic_cpuif

struct	gic_dist

struct	gic_redist

struct	gic_sgi_ppi

Macros
#define	ARM_GIC_IRQ_SGI_0 0

#define	ARM_GIC_IRQ_SGI_1 1

#define	ARM_GIC_IRQ_SGI_2 2

#define	ARM_GIC_IRQ_SGI_3 3

#define	ARM_GIC_IRQ_SGI_5 5

#define	ARM_GIC_IRQ_SGI_6 6

#define	ARM_GIC_IRQ_SGI_7 7

#define	ARM_GIC_IRQ_SGI_8 8

#define	ARM_GIC_IRQ_SGI_9 9

#define	ARM_GIC_IRQ_SGI_10 10

#define	ARM_GIC_IRQ_SGI_11 11

#define	ARM_GIC_IRQ_SGI_12 12

#define	ARM_GIC_IRQ_SGI_13 13

#define	ARM_GIC_IRQ_SGI_14 14

#define	ARM_GIC_IRQ_SGI_15 15

#define	ARM_GIC_IRQ_SGI_LAST 15

#define	ARM_GIC_IRQ_PPI_LAST 31

#define	ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)

#define	GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5)

#define	GIC_ID_TO_ONE_BIT_REG_BIT(id) (1U << ((id) & 0x1fU))

#define	GIC_ID_TO_TWO_BITS_REG_INDEX(id) ((id) >> 4)

#define	GIC_ID_TO_TWO_BITS_REG_OFFSET(id) (((id) & 0xfU) << 1)

#define	PRIORITY_DEFAULT 127

#define	MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)

#define	MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23)

#define	MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)

#define	MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15)

#define	MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15)

#define	MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)

#define	MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7)

#define	MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7)

#define	MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)

#define	ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55)

#define	ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55)

#define	ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55)

#define	ICC_SGIR_IRM BSP_BIT32(40)

#define	ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39)

#define	ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39)

#define	ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)

#define	ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27)

#define	ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27)

#define	ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27)

#define	ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23)

#define	ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23)

#define	ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)

#define	ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15)

#define	ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15)

#define	ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15)

#define	ICC_IGRPEN0_EL1 "S3_0_C12_C12_6, %0"

#define	ICC_IGRPEN1_EL1 "S3_0_C12_C12_7, %0"

#define	ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"

#define	ICC_IGRPEN0 ICC_IGRPEN0_EL1

#define	ICC_IGRPEN1 ICC_IGRPEN1_EL1

#define	ICC_PMR "S3_0_C4_C6_0, %0"

#define	ICC_EOIR1 "S3_0_C12_C12_1, %0"

#define	ICC_SRE "S3_0_C12_C12_5, %0"

#define	ICC_BPR0 "S3_0_C12_C8_3, %0"

#define	ICC_BPR1 "S3_0_C12_C12_3, %0"

#define	ICC_CTLR "S3_0_C12_C12_4, %0"

#define	ICC_IAR1 "%0, S3_0_C12_C12_0"

#define	MPIDR "%0, mpidr_el1"

#define	MPIDR_AFFINITY3(val) BSP_FLD64(val, 32, 39)

#define	MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 32, 39)

#define	MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)

#define	ICC_SGI1 "S3_0_C12_C11_5, %0"

#define	WRITE64_SR(SR_NAME, VALUE) __asm__ volatile("msr " SR_NAME " \n" : : "r" (VALUE) );

#define	WRITE_SR(SR_NAME, VALUE) WRITE64_SR(SR_NAME, VALUE)

#define	READ_SR(SR_NAME)

Enumerations
enum	gic_group { GIC_GROUP_0 , GIC_GROUP_1 }

enum	gic_trigger_mode { GIC_LEVEL_SENSITIVE , GIC_EDGE_TRIGGERED }

enum	gic_handling_model { GIC_N_TO_N , GIC_1_TO_N }

Functions
rtems_status_code	arm_gic_irq_set_group (rtems_vector_number vector, gic_group group)

rtems_status_code	arm_gic_irq_get_group (rtems_vector_number vector, gic_group *group)

void	arm_gic_trigger_sgi (rtems_vector_number vector, uint32_t targets)

Detailed Description

This group contains the Interrupt Manager implementation parts specific to the ARM Generic Interrupt Controller.

Macro Definition Documentation

◆ READ_SR

#define READ_SR ( SR_NAME )

Value:

({ \
  uint64_t value; \
  __asm__ volatile("mrs    " SR_NAME : "=&r" (value) ); \
  value; \
})

Files

Data Structures

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ READ_SR