CFG_NUM_LANES - CFG_NUM_LANES
#define	DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK (0x3U)

#define	DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT (0U)

#define	DSI_HOST_CFG_NUM_LANES_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK)

CFG_NONCONTINUOUS_CLK - CFG_NONCONTINUOUS_CLK
#define	DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK (0x1U)

#define	DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT (0U)

#define	DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK)

CFG_T_PRE - CFG_T_PRE
#define	DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK (0xFFU)

#define	DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT (0U)

#define	DSI_HOST_CFG_T_PRE_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK)

CFG_T_POST - CFG_T_POST
#define	DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK (0xFFU)

#define	DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT (0U)

#define	DSI_HOST_CFG_T_POST_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK)

CFG_TX_GAP - CFG_TX_GAP
#define	DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK (0xFFU)

#define	DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT (0U)

#define	DSI_HOST_CFG_TX_GAP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK)

CFG_AUTOINSERT_EOTP - CFG_AUTOINSERT_ETOP
#define	DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK (0x1U)

#define	DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT (0U)

#define	DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK)

CFG_EXTRA_CMDS_AFTER_EOTP - CFG_EXTRA_CMDS_AFTER_ETOP
#define	DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK (0xFFU)

#define	DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT (0U)

#define	DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK)

CFG_HTX_TO_COUNT - CFG_HTX_TO_COUNT
#define	DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK (0xFFFFFFU)

#define	DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT (0U)

#define	DSI_HOST_CFG_HTX_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK)

CFG_LRX_H_TO_COUNT - CFG_LRX_H_TO_COUNT
#define	DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK (0xFFFFFFU)

#define	DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT (0U)

#define	DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK)

CFG_BTA_H_TO_COUNT - CFG_BTA_H_TO_COUNT
#define	DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK (0xFFFFFFU)

#define	DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT (0U)

#define	DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK)

CFG_TWAKEUP - CFG_TWAKEUP
#define	DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK (0x7FFFFU)

#define	DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT (0U)

#define	DSI_HOST_CFG_TWAKEUP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK)

CFG_STATUS_OUT - CFG_STATUS_OUT
#define	DSI_HOST_CFG_STATUS_OUT_STATUS_MASK (0xFFFFFFFFU)

#define	DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT (0U)

#define	DSI_HOST_CFG_STATUS_OUT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & DSI_HOST_CFG_STATUS_OUT_STATUS_MASK)

RX_ERROR_STATUS - RX_ERROR_STATUS
#define	DSI_HOST_RX_ERROR_STATUS_STATUS_MASK (0x7FFU)

#define	DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT (0U)

#define	DSI_HOST_RX_ERROR_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT)) & DSI_HOST_RX_ERROR_STATUS_STATUS_MASK)

CFG_NUM_LANES - CFG_NUM_LANES
#define	DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK (0x3U)

#define	DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT (0U)

#define	DSI_HOST_CFG_NUM_LANES_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK)

CFG_NONCONTINUOUS_CLK - CFG_NONCONTINUOUS_CLK
#define	DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK (0x1U)

#define	DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT (0U)

#define	DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK)

CFG_T_PRE - CFG_T_PRE
#define	DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK (0xFFU)

#define	DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT (0U)

#define	DSI_HOST_CFG_T_PRE_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK)

CFG_T_POST - CFG_T_POST
#define	DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK (0xFFU)

#define	DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT (0U)

#define	DSI_HOST_CFG_T_POST_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK)

CFG_TX_GAP - CFG_TX_GAP
#define	DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK (0xFFU)

#define	DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT (0U)

#define	DSI_HOST_CFG_TX_GAP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK)

CFG_AUTOINSERT_EOTP - CFG_AUTOINSERT_ETOP
#define	DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK (0x1U)

#define	DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT (0U)

#define	DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK)

CFG_EXTRA_CMDS_AFTER_EOTP - CFG_EXTRA_CMDS_AFTER_ETOP
#define	DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK (0xFFU)

#define	DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT (0U)

#define	DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK)

CFG_HTX_TO_COUNT - CFG_HTX_TO_COUNT
#define	DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK (0xFFFFFFU)

#define	DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT (0U)

#define	DSI_HOST_CFG_HTX_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK)

CFG_LRX_H_TO_COUNT - CFG_LRX_H_TO_COUNT
#define	DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK (0xFFFFFFU)

#define	DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT (0U)

#define	DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK)

CFG_BTA_H_TO_COUNT - CFG_BTA_H_TO_COUNT
#define	DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK (0xFFFFFFU)

#define	DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT (0U)

#define	DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK)

CFG_TWAKEUP - CFG_TWAKEUP
#define	DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK (0x7FFFFU)

#define	DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT (0U)

#define	DSI_HOST_CFG_TWAKEUP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK)

CFG_STATUS_OUT - CFG_STATUS_OUT
#define	DSI_HOST_CFG_STATUS_OUT_STATUS_MASK (0xFFFFFFFFU)

#define	DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT (0U)

#define	DSI_HOST_CFG_STATUS_OUT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & DSI_HOST_CFG_STATUS_OUT_STATUS_MASK)

RX_ERROR_STATUS - RX_ERROR_STATUS
#define	DSI_HOST_RX_ERROR_STATUS_STATUS_MASK (0x7FFU)

#define	DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT (0U)

#define	DSI_HOST_RX_ERROR_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT)) & DSI_HOST_RX_ERROR_STATUS_STATUS_MASK)

Detailed Description

Macro Definition Documentation

◆ DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT [1/2]

#define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK)

AUTOINSERT - Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode. 0b0..EoTp is not automatically inserted 0b1..EoTp is automatically inserted

◆ DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT [2/2]

#define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK)

AUTOINSERT - Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode. 0b0..EoTp is not automatically inserted 0b1..EoTp is automatically inserted

◆ DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT [1/2]

#define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK)

COUNT - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in clk_byte clock periods that once reached will initiate a timeout error.

◆ DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT [2/2]

#define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK)

COUNT - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in clk_byte clock periods that once reached will initiate a timeout error.

◆ DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP [1/2]

#define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK)

EXTRA_EOTP - Configures the DSI Host Controller to send extra End Of Transmission Packets after the end of a packet. The value is the number of extra EOTP packets sent.

◆ DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP [2/2]

#define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK)

EXTRA_EOTP - Configures the DSI Host Controller to send extra End Of Transmission Packets after the end of a packet. The value is the number of extra EOTP packets sent.

◆ DSI_HOST_CFG_HTX_TO_COUNT_COUNT [1/2]

#define DSI_HOST_CFG_HTX_TO_COUNT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK)

COUNT - Sets the value of the DSI Host High Speed TX timeout count in clk_byte clock periods that once reached will initiate a timeout error and follow the recovery procedure documented in the DSI specification.

◆ DSI_HOST_CFG_HTX_TO_COUNT_COUNT [2/2]

#define DSI_HOST_CFG_HTX_TO_COUNT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK)

COUNT - Sets the value of the DSI Host High Speed TX timeout count in clk_byte clock periods that once reached will initiate a timeout error and follow the recovery procedure documented in the DSI specification.

◆ DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT [1/2]

#define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK)

COUNT - Sets the value of the DSI Host low power RX timeout count in clk_byte clock periods that once reached will initiate a timeout error and follow the recovery procedure documented in the DSI specification.

◆ DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT [2/2]

#define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK)

COUNT - Sets the value of the DSI Host low power RX timeout count in clk_byte clock periods that once reached will initiate a timeout error and follow the recovery procedure documented in the DSI specification.

◆ DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE [1/2]

#define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK)

CLK_MODE - Sets the Host Controller into non-continuous MIPI clock mode. When in non-continuous clock mode, the high speed clock will transition into low power mode between transmissions. 0b0..Continuous high speed clock 0b1..Non-Continuous high speed clock

◆ DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE [2/2]

#define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK)

CLK_MODE - Sets the Host Controller into non-continuous MIPI clock mode. When in non-continuous clock mode, the high speed clock will transition into low power mode between transmissions. 0b0..Continuous high speed clock 0b1..Non-Continuous high speed clock

◆ DSI_HOST_CFG_NUM_LANES_NUM_LANES [1/2]

#define DSI_HOST_CFG_NUM_LANES_NUM_LANES ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK)

NUM_LANES - Sets the number of active lanes that are to be used for transmitting data. 0b00..1 lane 0b01..2 lanes

◆ DSI_HOST_CFG_NUM_LANES_NUM_LANES [2/2]

#define DSI_HOST_CFG_NUM_LANES_NUM_LANES ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK)

NUM_LANES - Sets the number of active lanes that are to be used for transmitting data. 0b00..1 lane 0b01..2 lanes

◆ DSI_HOST_CFG_STATUS_OUT_STATUS [1/2]

#define DSI_HOST_CFG_STATUS_OUT_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & DSI_HOST_CFG_STATUS_OUT_STATUS_MASK)

STATUS - Status Register

◆ DSI_HOST_CFG_STATUS_OUT_STATUS [2/2]

#define DSI_HOST_CFG_STATUS_OUT_STATUS ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & DSI_HOST_CFG_STATUS_OUT_STATUS_MASK)

STATUS - Status Register

◆ DSI_HOST_CFG_T_POST_NUM_PERIODS [1/2]

#define DSI_HOST_CFG_T_POST_NUM_PERIODS ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK)

NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) to wait before putting the clock lane into LP mode after the data lanes have been detected to be in Stop State. This setting represents the DPHY timing parameters TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE requirement for the clock lane before the data lane is allowed to change from LP11 to start a high speed transmission. The minimum value for this port is 1.

◆ DSI_HOST_CFG_T_POST_NUM_PERIODS [2/2]

#define DSI_HOST_CFG_T_POST_NUM_PERIODS ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK)

NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) to wait before putting the clock lane into LP mode after the data lanes have been detected to be in Stop State. This setting represents the DPHY timing parameters TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE requirement for the clock lane before the data lane is allowed to change from LP11 to start a high speed transmission. The minimum value for this port is 1.

◆ DSI_HOST_CFG_T_PRE_NUM_PERIODS [1/2]

#define DSI_HOST_CFG_T_PRE_NUM_PERIODS ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK)

NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will wait after enabling the clock lane for HS operation before enabling the data lanes for HS operation. This setting represents the TCLK-PRE DPHY timing parameter. The minimum value for this port is 1.

◆ DSI_HOST_CFG_T_PRE_NUM_PERIODS [2/2]

#define DSI_HOST_CFG_T_PRE_NUM_PERIODS ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK)

NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will wait after enabling the clock lane for HS operation before enabling the data lanes for HS operation. This setting represents the TCLK-PRE DPHY timing parameter. The minimum value for this port is 1.

◆ DSI_HOST_CFG_TWAKEUP_NUM_PERIODS [1/2]

#define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK)

NUM_PERIODS - DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods to keep a clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a minimum of 1ms in Mark-1 state after leaving ULPS.

◆ DSI_HOST_CFG_TWAKEUP_NUM_PERIODS [2/2]

#define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK)

NUM_PERIODS - DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods to keep a clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a minimum of 1ms in Mark-1 state after leaving ULPS.

◆ DSI_HOST_CFG_TX_GAP_NUM_PERIODS [1/2]

#define DSI_HOST_CFG_TX_GAP_NUM_PERIODS ( x ) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK)

NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode again. This setting represents the THS-EXIT DPHY timing parameter. The minimum value for this port is 1.

◆ DSI_HOST_CFG_TX_GAP_NUM_PERIODS [2/2]