DCDC Register Masks

REG0 - DCDC Register 0
#define	DCDC_REG0_PWD_ZCD_MASK   (0x1U)
#define	DCDC_REG0_PWD_ZCD_SHIFT   (0U)
#define	DCDC_REG0_PWD_ZCD(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK   (0x2U)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT   (1U)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
#define	DCDC_REG0_SEL_CLK_MASK   (0x4U)
#define	DCDC_REG0_SEL_CLK_SHIFT   (2U)
#define	DCDC_REG0_SEL_CLK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
#define	DCDC_REG0_PWD_OSC_INT_MASK   (0x8U)
#define	DCDC_REG0_PWD_OSC_INT_SHIFT   (3U)
#define	DCDC_REG0_PWD_OSC_INT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
#define	DCDC_REG0_PWD_CUR_SNS_CMP_MASK   (0x10U)
#define	DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT   (4U)
#define	DCDC_REG0_PWD_CUR_SNS_CMP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
#define	DCDC_REG0_CUR_SNS_THRSH_MASK   (0xE0U)
#define	DCDC_REG0_CUR_SNS_THRSH_SHIFT   (5U)
#define	DCDC_REG0_CUR_SNS_THRSH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
#define	DCDC_REG0_PWD_OVERCUR_DET_MASK   (0x100U)
#define	DCDC_REG0_PWD_OVERCUR_DET_SHIFT   (8U)
#define	DCDC_REG0_PWD_OVERCUR_DET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
#define	DCDC_REG0_OVERCUR_TRIG_ADJ_MASK   (0x600U)
#define	DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT   (9U)
#define	DCDC_REG0_OVERCUR_TRIG_ADJ(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
#define	DCDC_REG0_PWD_CMP_BATT_DET_MASK   (0x800U)
#define	DCDC_REG0_PWD_CMP_BATT_DET_SHIFT   (11U)
#define	DCDC_REG0_PWD_CMP_BATT_DET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
#define	DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK   (0x10000U)
#define	DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT   (16U)
#define	DCDC_REG0_EN_LP_OVERLOAD_SNS(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
#define	DCDC_REG0_PWD_HIGH_VOLT_DET_MASK   (0x20000U)
#define	DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT   (17U)
#define	DCDC_REG0_PWD_HIGH_VOLT_DET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
#define	DCDC_REG0_LP_OVERLOAD_THRSH_MASK   (0xC0000U)
#define	DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT   (18U)
#define	DCDC_REG0_LP_OVERLOAD_THRSH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
#define	DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK   (0x100000U)
#define	DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT   (20U)
#define	DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
#define	DCDC_REG0_LP_HIGH_HYS_MASK   (0x200000U)
#define	DCDC_REG0_LP_HIGH_HYS_SHIFT   (21U)
#define	DCDC_REG0_LP_HIGH_HYS(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
#define	DCDC_REG0_PWD_CMP_OFFSET_MASK   (0x4000000U)
#define	DCDC_REG0_PWD_CMP_OFFSET_SHIFT   (26U)
#define	DCDC_REG0_PWD_CMP_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
#define	DCDC_REG0_XTALOK_DISABLE_MASK   (0x8000000U)
#define	DCDC_REG0_XTALOK_DISABLE_SHIFT   (27U)
#define	DCDC_REG0_XTALOK_DISABLE(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
#define	DCDC_REG0_CURRENT_ALERT_RESET_MASK   (0x10000000U)
#define	DCDC_REG0_CURRENT_ALERT_RESET_SHIFT   (28U)
#define	DCDC_REG0_CURRENT_ALERT_RESET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
#define	DCDC_REG0_XTAL_24M_OK_MASK   (0x20000000U)
#define	DCDC_REG0_XTAL_24M_OK_SHIFT   (29U)
#define	DCDC_REG0_XTAL_24M_OK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
#define	DCDC_REG0_STS_DC_OK_MASK   (0x80000000U)
#define	DCDC_REG0_STS_DC_OK_SHIFT   (31U)
#define	DCDC_REG0_STS_DC_OK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)

REG1 - DCDC Register 1
#define	DCDC_REG1_REG_FBK_SEL_MASK   (0x180U)
#define	DCDC_REG1_REG_FBK_SEL_SHIFT   (7U)
#define	DCDC_REG1_REG_FBK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
#define	DCDC_REG1_REG_RLOAD_SW_MASK   (0x200U)
#define	DCDC_REG1_REG_RLOAD_SW_SHIFT   (9U)
#define	DCDC_REG1_REG_RLOAD_SW(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
#define	DCDC_REG1_LP_CMP_ISRC_SEL_MASK   (0x3000U)
#define	DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT   (12U)
#define	DCDC_REG1_LP_CMP_ISRC_SEL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
#define	DCDC_REG1_LOOPCTRL_HST_THRESH_MASK   (0x200000U)
#define	DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT   (21U)
#define	DCDC_REG1_LOOPCTRL_HST_THRESH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
#define	DCDC_REG1_LOOPCTRL_EN_HYST_MASK   (0x800000U)
#define	DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT   (23U)
#define	DCDC_REG1_LOOPCTRL_EN_HYST(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
#define	DCDC_REG1_VBG_TRIM_MASK   (0x1F000000U)
#define	DCDC_REG1_VBG_TRIM_SHIFT   (24U)
#define	DCDC_REG1_VBG_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)

REG2 - DCDC Register 2
#define	DCDC_REG2_LOOPCTRL_DC_FF_MASK   (0x1C0U)
#define	DCDC_REG2_LOOPCTRL_DC_FF_SHIFT   (6U)
#define	DCDC_REG2_LOOPCTRL_DC_FF(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK   (0xE00U)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT   (9U)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK   (0x1000U)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT   (12U)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK   (0x2000U)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT   (13U)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
#define	DCDC_REG2_DISABLE_PULSE_SKIP_MASK   (0x8000000U)
#define	DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT   (27U)
#define	DCDC_REG2_DISABLE_PULSE_SKIP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
#define	DCDC_REG2_DCM_SET_CTRL_MASK   (0x10000000U)
#define	DCDC_REG2_DCM_SET_CTRL_SHIFT   (28U)
#define	DCDC_REG2_DCM_SET_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)

REG3 - DCDC Register 3
#define	DCDC_REG3_TRG_MASK   (0x1FU)
#define	DCDC_REG3_TRG_SHIFT   (0U)
#define	DCDC_REG3_TRG(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
#define	DCDC_REG3_TARGET_LP_MASK   (0x700U)
#define	DCDC_REG3_TARGET_LP_SHIFT   (8U)
#define	DCDC_REG3_TARGET_LP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
#define	DCDC_REG3_MINPWR_DC_HALFCLK_MASK   (0x1000000U)
#define	DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT   (24U)
#define	DCDC_REG3_MINPWR_DC_HALFCLK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
#define	DCDC_REG3_DISABLE_STEP_MASK   (0x40000000U)
#define	DCDC_REG3_DISABLE_STEP_SHIFT   (30U)
#define	DCDC_REG3_DISABLE_STEP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)

CTRL0 - DCDC Control Register 0
#define	DCDC_CTRL0_ENABLE_MASK   (0x1U)
#define	DCDC_CTRL0_ENABLE_SHIFT   (0U)
#define	DCDC_CTRL0_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
#define	DCDC_CTRL0_DIG_EN_MASK   (0x2U)
#define	DCDC_CTRL0_DIG_EN_SHIFT   (1U)
#define	DCDC_CTRL0_DIG_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK)
#define	DCDC_CTRL0_STBY_EN_MASK   (0x4U)
#define	DCDC_CTRL0_STBY_EN_SHIFT   (2U)
#define	DCDC_CTRL0_STBY_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK)
#define	DCDC_CTRL0_LP_MODE_EN_MASK   (0x8U)
#define	DCDC_CTRL0_LP_MODE_EN_SHIFT   (3U)
#define	DCDC_CTRL0_LP_MODE_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK)
#define	DCDC_CTRL0_STBY_LP_MODE_EN_MASK   (0x10U)
#define	DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT   (4U)
#define	DCDC_CTRL0_STBY_LP_MODE_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK)
#define	DCDC_CTRL0_ENABLE_DCDC_CNT_MASK   (0x20U)
#define	DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT   (5U)
#define	DCDC_CTRL0_ENABLE_DCDC_CNT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK)
#define	DCDC_CTRL0_TRIM_HOLD_MASK   (0x40U)
#define	DCDC_CTRL0_TRIM_HOLD_SHIFT   (6U)
#define	DCDC_CTRL0_TRIM_HOLD(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK)
#define	DCDC_CTRL0_DEBUG_BITS_MASK   (0x7FF80000U)
#define	DCDC_CTRL0_DEBUG_BITS_SHIFT   (19U)
#define	DCDC_CTRL0_DEBUG_BITS(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK)
#define	DCDC_CTRL0_CONTROL_MODE_MASK   (0x80000000U)
#define	DCDC_CTRL0_CONTROL_MODE_SHIFT   (31U)
#define	DCDC_CTRL0_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)

CTRL1 - DCDC Control Register 1
#define	DCDC_CTRL1_VDD1P8CTRL_TRG_MASK   (0x1FU)
#define	DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT   (0U)
#define	DCDC_CTRL1_VDD1P8CTRL_TRG(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)
#define	DCDC_CTRL1_VDD1P0CTRL_TRG_MASK   (0x1F00U)
#define	DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT   (8U)
#define	DCDC_CTRL1_VDD1P0CTRL_TRG(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)
#define	DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK   (0x1F0000U)
#define	DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT   (16U)
#define	DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK)
#define	DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK   (0x1F000000U)
#define	DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT   (24U)
#define	DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)

REG0 - DCDC Register 0
#define	DCDC_REG0_PWD_ZCD_MASK   (0x1U)
#define	DCDC_REG0_PWD_ZCD_SHIFT   (0U)
#define	DCDC_REG0_PWD_ZCD(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK   (0x2U)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT   (1U)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
#define	DCDC_REG0_SEL_CLK_MASK   (0x4U)
#define	DCDC_REG0_SEL_CLK_SHIFT   (2U)
#define	DCDC_REG0_SEL_CLK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
#define	DCDC_REG0_PWD_OSC_INT_MASK   (0x8U)
#define	DCDC_REG0_PWD_OSC_INT_SHIFT   (3U)
#define	DCDC_REG0_PWD_OSC_INT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
#define	DCDC_REG0_PWD_CUR_SNS_CMP_MASK   (0x10U)
#define	DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT   (4U)
#define	DCDC_REG0_PWD_CUR_SNS_CMP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
#define	DCDC_REG0_CUR_SNS_THRSH_MASK   (0xE0U)
#define	DCDC_REG0_CUR_SNS_THRSH_SHIFT   (5U)
#define	DCDC_REG0_CUR_SNS_THRSH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
#define	DCDC_REG0_PWD_OVERCUR_DET_MASK   (0x100U)
#define	DCDC_REG0_PWD_OVERCUR_DET_SHIFT   (8U)
#define	DCDC_REG0_PWD_OVERCUR_DET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
#define	DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK   (0x800U)
#define	DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT   (11U)
#define	DCDC_REG0_PWD_CMP_DCDC_IN_DET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK)
#define	DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK   (0x10000U)
#define	DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT   (16U)
#define	DCDC_REG0_PWD_HIGH_VDD1P8_DET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK)
#define	DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK   (0x20000U)
#define	DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT   (17U)
#define	DCDC_REG0_PWD_HIGH_VDD1P0_DET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK)
#define	DCDC_REG0_LP_HIGH_HYS_MASK   (0x200000U)
#define	DCDC_REG0_LP_HIGH_HYS_SHIFT   (21U)
#define	DCDC_REG0_LP_HIGH_HYS(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
#define	DCDC_REG0_PWD_CMP_OFFSET_MASK   (0x4000000U)
#define	DCDC_REG0_PWD_CMP_OFFSET_SHIFT   (26U)
#define	DCDC_REG0_PWD_CMP_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
#define	DCDC_REG0_XTALOK_DISABLE_MASK   (0x8000000U)
#define	DCDC_REG0_XTALOK_DISABLE_SHIFT   (27U)
#define	DCDC_REG0_XTALOK_DISABLE(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
#define	DCDC_REG0_XTAL_24M_OK_MASK   (0x20000000U)
#define	DCDC_REG0_XTAL_24M_OK_SHIFT   (29U)
#define	DCDC_REG0_XTAL_24M_OK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
#define	DCDC_REG0_STS_DC_OK_MASK   (0x80000000U)
#define	DCDC_REG0_STS_DC_OK_SHIFT   (31U)
#define	DCDC_REG0_STS_DC_OK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)

REG1 - DCDC Register 1
#define	DCDC_REG1_DM_CTRL_MASK   (0x8U)
#define	DCDC_REG1_DM_CTRL_SHIFT   (3U)
#define	DCDC_REG1_DM_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DM_CTRL_SHIFT)) & DCDC_REG1_DM_CTRL_MASK)
#define	DCDC_REG1_RLOAD_REG_EN_LPSR_MASK   (0x10U)
#define	DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT   (4U)
#define	DCDC_REG1_RLOAD_REG_EN_LPSR(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
#define	DCDC_REG1_VBG_TRIM_MASK   (0x7C0U)
#define	DCDC_REG1_VBG_TRIM_SHIFT   (6U)
#define	DCDC_REG1_VBG_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
#define	DCDC_REG1_LP_CMP_ISRC_SEL_MASK   (0x1800U)
#define	DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT   (11U)
#define	DCDC_REG1_LP_CMP_ISRC_SEL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
#define	DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK   (0x8000000U)
#define	DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT   (27U)
#define	DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK)
#define	DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK   (0x10000000U)
#define	DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT   (28U)
#define	DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
#define	DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK   (0x20000000U)
#define	DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT   (29U)
#define	DCDC_REG1_LOOPCTRL_EN_CM_HYST(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK)
#define	DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK   (0x40000000U)
#define	DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT   (30U)
#define	DCDC_REG1_LOOPCTRL_EN_DF_HYST(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK)

REG2 - DCDC Register 2
#define	DCDC_REG2_LOOPCTRL_DC_C_MASK   (0x3U)
#define	DCDC_REG2_LOOPCTRL_DC_C_SHIFT   (0U)
#define	DCDC_REG2_LOOPCTRL_DC_C(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
#define	DCDC_REG2_LOOPCTRL_DC_R_MASK   (0x3CU)
#define	DCDC_REG2_LOOPCTRL_DC_R_SHIFT   (2U)
#define	DCDC_REG2_LOOPCTRL_DC_R(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
#define	DCDC_REG2_LOOPCTRL_DC_FF_MASK   (0x1C0U)
#define	DCDC_REG2_LOOPCTRL_DC_FF_SHIFT   (6U)
#define	DCDC_REG2_LOOPCTRL_DC_FF(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK   (0xE00U)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT   (9U)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK   (0x1000U)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT   (12U)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK   (0x2000U)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT   (13U)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
#define	DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK   (0x8000U)
#define	DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT   (15U)
#define	DCDC_REG2_BATTMONITOR_EN_BATADJ(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK)
#define	DCDC_REG2_BATTMONITOR_BATT_VAL_MASK   (0x3FF0000U)
#define	DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT   (16U)
#define	DCDC_REG2_BATTMONITOR_BATT_VAL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_BATTMONITOR_BATT_VAL_MASK)
#define	DCDC_REG2_DCM_SET_CTRL_MASK   (0x10000000U)
#define	DCDC_REG2_DCM_SET_CTRL_SHIFT   (28U)
#define	DCDC_REG2_DCM_SET_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
#define	DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK   (0x40000000U)
#define	DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT   (30U)
#define	DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT)) & DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK)

REG3 - DCDC Register 3
#define	DCDC_REG3_IN_BROWNOUT_MASK   (0x4000U)
#define	DCDC_REG3_IN_BROWNOUT_SHIFT   (14U)
#define	DCDC_REG3_IN_BROWNOUT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK)
#define	DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK   (0x8000U)
#define	DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT   (15U)
#define	DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK)
#define	DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK   (0x10000U)
#define	DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT   (16U)
#define	DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK)
#define	DCDC_REG3_OVERCUR_DETECT_OUT_MASK   (0x20000U)
#define	DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT   (17U)
#define	DCDC_REG3_OVERCUR_DETECT_OUT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK)
#define	DCDC_REG3_ENABLE_FF_MASK   (0x40000U)
#define	DCDC_REG3_ENABLE_FF_SHIFT   (18U)
#define	DCDC_REG3_ENABLE_FF(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK)
#define	DCDC_REG3_DISABLE_PULSE_SKIP_MASK   (0x80000U)
#define	DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT   (19U)
#define	DCDC_REG3_DISABLE_PULSE_SKIP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK)
#define	DCDC_REG3_DISABLE_IDLE_SKIP_MASK   (0x100000U)
#define	DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT   (20U)
#define	DCDC_REG3_DISABLE_IDLE_SKIP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK)
#define	DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK   (0x200000U)
#define	DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT   (21U)
#define	DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK)
#define	DCDC_REG3_REG_FBK_SEL_MASK   (0xC00000U)
#define	DCDC_REG3_REG_FBK_SEL_SHIFT   (22U)
#define	DCDC_REG3_REG_FBK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_REG_FBK_SEL_SHIFT)) & DCDC_REG3_REG_FBK_SEL_MASK)
#define	DCDC_REG3_MINPWR_DC_HALFCLK_MASK   (0x1000000U)
#define	DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT   (24U)
#define	DCDC_REG3_MINPWR_DC_HALFCLK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
#define	DCDC_REG3_MINPWR_HALF_FETS_MASK   (0x4000000U)
#define	DCDC_REG3_MINPWR_HALF_FETS_SHIFT   (26U)
#define	DCDC_REG3_MINPWR_HALF_FETS(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_MINPWR_HALF_FETS_MASK)
#define	DCDC_REG3_MISC_DELAY_TIMING_MASK   (0x8000000U)
#define	DCDC_REG3_MISC_DELAY_TIMING_SHIFT   (27U)
#define	DCDC_REG3_MISC_DELAY_TIMING(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
#define	DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK   (0x20000000U)
#define	DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT   (29U)
#define	DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
#define	DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK   (0x40000000U)
#define	DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT   (30U)
#define	DCDC_REG3_VDD1P8CTRL_DISABLE_STEP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK)

REG4 - DCDC Register 4
#define	DCDC_REG4_ENABLE_SP_MASK   (0xFFFFU)
#define	DCDC_REG4_ENABLE_SP_SHIFT   (0U)
#define	DCDC_REG4_ENABLE_SP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_ENABLE_SP_SHIFT)) & DCDC_REG4_ENABLE_SP_MASK)

REG5 - DCDC Register 5
#define	DCDC_REG5_DIG_EN_SP_MASK   (0xFFFFU)
#define	DCDC_REG5_DIG_EN_SP_SHIFT   (0U)
#define	DCDC_REG5_DIG_EN_SP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG5_DIG_EN_SP_SHIFT)) & DCDC_REG5_DIG_EN_SP_MASK)

REG6 - DCDC Register 6
#define	DCDC_REG6_LP_MODE_SP_MASK   (0xFFFFU)
#define	DCDC_REG6_LP_MODE_SP_SHIFT   (0U)
#define	DCDC_REG6_LP_MODE_SP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_LP_MODE_SP_SHIFT)) & DCDC_REG6_LP_MODE_SP_MASK)

REG7 - DCDC Register 7
#define	DCDC_REG7_STBY_EN_SP_MASK   (0xFFFFU)
#define	DCDC_REG7_STBY_EN_SP_SHIFT   (0U)
#define	DCDC_REG7_STBY_EN_SP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_STBY_EN_SP_SHIFT)) & DCDC_REG7_STBY_EN_SP_MASK)

REG7P - DCDC Register 7 plus
#define	DCDC_REG7P_STBY_LP_MODE_SP_MASK   (0xFFFFU)
#define	DCDC_REG7P_STBY_LP_MODE_SP_SHIFT   (0U)
#define	DCDC_REG7P_STBY_LP_MODE_SP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG7P_STBY_LP_MODE_SP_SHIFT)) & DCDC_REG7P_STBY_LP_MODE_SP_MASK)

REG8 - DCDC Register 8
#define	DCDC_REG8_ANA_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG8_ANA_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG8_ANA_TRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG8_ANA_TRG_SP0_SHIFT)) & DCDC_REG8_ANA_TRG_SP0_MASK)

REG9 - DCDC Register 9
#define	DCDC_REG9_ANA_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG9_ANA_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG9_ANA_TRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG9_ANA_TRG_SP1_SHIFT)) & DCDC_REG9_ANA_TRG_SP1_MASK)

REG10 - DCDC Register 10
#define	DCDC_REG10_ANA_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG10_ANA_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG10_ANA_TRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG10_ANA_TRG_SP2_SHIFT)) & DCDC_REG10_ANA_TRG_SP2_MASK)

REG11 - DCDC Register 11
#define	DCDC_REG11_ANA_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG11_ANA_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG11_ANA_TRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG11_ANA_TRG_SP3_SHIFT)) & DCDC_REG11_ANA_TRG_SP3_MASK)

REG12 - DCDC Register 12
#define	DCDC_REG12_DIG_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG12_DIG_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG12_DIG_TRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG12_DIG_TRG_SP0_SHIFT)) & DCDC_REG12_DIG_TRG_SP0_MASK)

REG13 - DCDC Register 13
#define	DCDC_REG13_DIG_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG13_DIG_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG13_DIG_TRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG13_DIG_TRG_SP1_SHIFT)) & DCDC_REG13_DIG_TRG_SP1_MASK)

REG14 - DCDC Register 14
#define	DCDC_REG14_DIG_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG14_DIG_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG14_DIG_TRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG14_DIG_TRG_SP2_SHIFT)) & DCDC_REG14_DIG_TRG_SP2_MASK)

REG15 - DCDC Register 15
#define	DCDC_REG15_DIG_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG15_DIG_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG15_DIG_TRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG15_DIG_TRG_SP3_SHIFT)) & DCDC_REG15_DIG_TRG_SP3_MASK)

REG16 - DCDC Register 16
#define	DCDC_REG16_ANA_STBY_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG16_ANA_STBY_TRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT)) & DCDC_REG16_ANA_STBY_TRG_SP0_MASK)

REG17 - DCDC Register 17
#define	DCDC_REG17_ANA_STBY_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG17_ANA_STBY_TRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)

REG18 - DCDC Register 18
#define	DCDC_REG18_ANA_STBY_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG18_ANA_STBY_TRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)

REG19 - DCDC Register 19
#define	DCDC_REG19_ANA_STBY_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG19_ANA_STBY_TRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)

REG20 - DCDC Register 20
#define	DCDC_REG20_DIG_STBY_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG20_DIG_STBY_TRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT)) & DCDC_REG20_DIG_STBY_TRG_SP0_MASK)

REG21 - DCDC Register 21
#define	DCDC_REG21_DIG_STBY_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG21_DIG_STBY_TRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT)) & DCDC_REG21_DIG_STBY_TRG_SP1_MASK)

REG22 - DCDC Register 22
#define	DCDC_REG22_DIG_STBY_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG22_DIG_STBY_TRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT)) & DCDC_REG22_DIG_STBY_TRG_SP2_MASK)

REG23 - DCDC Register 23
#define	DCDC_REG23_DIG_STBY_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG23_DIG_STBY_TRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT)) & DCDC_REG23_DIG_STBY_TRG_SP3_MASK)

REG24 - DCDC Register 24
#define	DCDC_REG24_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	DCDC_REG24_OK_COUNT_SHIFT   (0U)
#define	DCDC_REG24_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)

CTRL0 - DCDC Control Register 0
#define	DCDC_CTRL0_ENABLE_MASK   (0x1U)
#define	DCDC_CTRL0_ENABLE_SHIFT   (0U)
#define	DCDC_CTRL0_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
#define	DCDC_CTRL0_DIG_EN_MASK   (0x2U)
#define	DCDC_CTRL0_DIG_EN_SHIFT   (1U)
#define	DCDC_CTRL0_DIG_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK)
#define	DCDC_CTRL0_STBY_EN_MASK   (0x4U)
#define	DCDC_CTRL0_STBY_EN_SHIFT   (2U)
#define	DCDC_CTRL0_STBY_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK)
#define	DCDC_CTRL0_LP_MODE_EN_MASK   (0x8U)
#define	DCDC_CTRL0_LP_MODE_EN_SHIFT   (3U)
#define	DCDC_CTRL0_LP_MODE_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK)
#define	DCDC_CTRL0_STBY_LP_MODE_EN_MASK   (0x10U)
#define	DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT   (4U)
#define	DCDC_CTRL0_STBY_LP_MODE_EN(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK)
#define	DCDC_CTRL0_ENABLE_DCDC_CNT_MASK   (0x20U)
#define	DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT   (5U)
#define	DCDC_CTRL0_ENABLE_DCDC_CNT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK)
#define	DCDC_CTRL0_TRIM_HOLD_MASK   (0x40U)
#define	DCDC_CTRL0_TRIM_HOLD_SHIFT   (6U)
#define	DCDC_CTRL0_TRIM_HOLD(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK)
#define	DCDC_CTRL0_DEBUG_BITS_MASK   (0x7FF80000U)
#define	DCDC_CTRL0_DEBUG_BITS_SHIFT   (19U)
#define	DCDC_CTRL0_DEBUG_BITS(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK)
#define	DCDC_CTRL0_CONTROL_MODE_MASK   (0x80000000U)
#define	DCDC_CTRL0_CONTROL_MODE_SHIFT   (31U)
#define	DCDC_CTRL0_CONTROL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)

CTRL1 - DCDC Control Register 1
#define	DCDC_CTRL1_VDD1P8CTRL_TRG_MASK   (0x1FU)
#define	DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT   (0U)
#define	DCDC_CTRL1_VDD1P8CTRL_TRG(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)
#define	DCDC_CTRL1_VDD1P0CTRL_TRG_MASK   (0x1F00U)
#define	DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT   (8U)
#define	DCDC_CTRL1_VDD1P0CTRL_TRG(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)
#define	DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK   (0x1F0000U)
#define	DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT   (16U)
#define	DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK)
#define	DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK   (0x1F000000U)
#define	DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT   (24U)
#define	DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)

REG0 - DCDC Register 0
#define	DCDC_REG0_PWD_ZCD_MASK   (0x1U)
#define	DCDC_REG0_PWD_ZCD_SHIFT   (0U)
#define	DCDC_REG0_PWD_ZCD(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK   (0x2U)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT   (1U)
#define	DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
#define	DCDC_REG0_SEL_CLK_MASK   (0x4U)
#define	DCDC_REG0_SEL_CLK_SHIFT   (2U)
#define	DCDC_REG0_SEL_CLK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
#define	DCDC_REG0_PWD_OSC_INT_MASK   (0x8U)
#define	DCDC_REG0_PWD_OSC_INT_SHIFT   (3U)
#define	DCDC_REG0_PWD_OSC_INT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
#define	DCDC_REG0_PWD_CUR_SNS_CMP_MASK   (0x10U)
#define	DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT   (4U)
#define	DCDC_REG0_PWD_CUR_SNS_CMP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
#define	DCDC_REG0_CUR_SNS_THRSH_MASK   (0xE0U)
#define	DCDC_REG0_CUR_SNS_THRSH_SHIFT   (5U)
#define	DCDC_REG0_CUR_SNS_THRSH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
#define	DCDC_REG0_PWD_OVERCUR_DET_MASK   (0x100U)
#define	DCDC_REG0_PWD_OVERCUR_DET_SHIFT   (8U)
#define	DCDC_REG0_PWD_OVERCUR_DET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
#define	DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK   (0x800U)
#define	DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT   (11U)
#define	DCDC_REG0_PWD_CMP_DCDC_IN_DET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK)
#define	DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK   (0x10000U)
#define	DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT   (16U)
#define	DCDC_REG0_PWD_HIGH_VDD1P8_DET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK)
#define	DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK   (0x20000U)
#define	DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT   (17U)
#define	DCDC_REG0_PWD_HIGH_VDD1P0_DET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK)
#define	DCDC_REG0_LP_HIGH_HYS_MASK   (0x200000U)
#define	DCDC_REG0_LP_HIGH_HYS_SHIFT   (21U)
#define	DCDC_REG0_LP_HIGH_HYS(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
#define	DCDC_REG0_PWD_CMP_OFFSET_MASK   (0x4000000U)
#define	DCDC_REG0_PWD_CMP_OFFSET_SHIFT   (26U)
#define	DCDC_REG0_PWD_CMP_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
#define	DCDC_REG0_XTALOK_DISABLE_MASK   (0x8000000U)
#define	DCDC_REG0_XTALOK_DISABLE_SHIFT   (27U)
#define	DCDC_REG0_XTALOK_DISABLE(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
#define	DCDC_REG0_XTAL_24M_OK_MASK   (0x20000000U)
#define	DCDC_REG0_XTAL_24M_OK_SHIFT   (29U)
#define	DCDC_REG0_XTAL_24M_OK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
#define	DCDC_REG0_STS_DC_OK_MASK   (0x80000000U)
#define	DCDC_REG0_STS_DC_OK_SHIFT   (31U)
#define	DCDC_REG0_STS_DC_OK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)

REG1 - DCDC Register 1
#define	DCDC_REG1_DM_CTRL_MASK   (0x8U)
#define	DCDC_REG1_DM_CTRL_SHIFT   (3U)
#define	DCDC_REG1_DM_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DM_CTRL_SHIFT)) & DCDC_REG1_DM_CTRL_MASK)
#define	DCDC_REG1_RLOAD_REG_EN_LPSR_MASK   (0x10U)
#define	DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT   (4U)
#define	DCDC_REG1_RLOAD_REG_EN_LPSR(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
#define	DCDC_REG1_VBG_TRIM_MASK   (0x7C0U)
#define	DCDC_REG1_VBG_TRIM_SHIFT   (6U)
#define	DCDC_REG1_VBG_TRIM(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
#define	DCDC_REG1_LP_CMP_ISRC_SEL_MASK   (0x1800U)
#define	DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT   (11U)
#define	DCDC_REG1_LP_CMP_ISRC_SEL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
#define	DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK   (0x8000000U)
#define	DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT   (27U)
#define	DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK)
#define	DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK   (0x10000000U)
#define	DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT   (28U)
#define	DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
#define	DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK   (0x20000000U)
#define	DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT   (29U)
#define	DCDC_REG1_LOOPCTRL_EN_CM_HYST(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK)
#define	DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK   (0x40000000U)
#define	DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT   (30U)
#define	DCDC_REG1_LOOPCTRL_EN_DF_HYST(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK)

REG2 - DCDC Register 2
#define	DCDC_REG2_LOOPCTRL_DC_C_MASK   (0x3U)
#define	DCDC_REG2_LOOPCTRL_DC_C_SHIFT   (0U)
#define	DCDC_REG2_LOOPCTRL_DC_C(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
#define	DCDC_REG2_LOOPCTRL_DC_R_MASK   (0x3CU)
#define	DCDC_REG2_LOOPCTRL_DC_R_SHIFT   (2U)
#define	DCDC_REG2_LOOPCTRL_DC_R(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
#define	DCDC_REG2_LOOPCTRL_DC_FF_MASK   (0x1C0U)
#define	DCDC_REG2_LOOPCTRL_DC_FF_SHIFT   (6U)
#define	DCDC_REG2_LOOPCTRL_DC_FF(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK   (0xE00U)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT   (9U)
#define	DCDC_REG2_LOOPCTRL_EN_RCSCALE(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK   (0x1000U)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT   (12U)
#define	DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK   (0x2000U)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT   (13U)
#define	DCDC_REG2_LOOPCTRL_HYST_SIGN(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
#define	DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK   (0x8000U)
#define	DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT   (15U)
#define	DCDC_REG2_BATTMONITOR_EN_BATADJ(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK)
#define	DCDC_REG2_BATTMONITOR_BATT_VAL_MASK   (0x3FF0000U)
#define	DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT   (16U)
#define	DCDC_REG2_BATTMONITOR_BATT_VAL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_BATTMONITOR_BATT_VAL_MASK)
#define	DCDC_REG2_DCM_SET_CTRL_MASK   (0x10000000U)
#define	DCDC_REG2_DCM_SET_CTRL_SHIFT   (28U)
#define	DCDC_REG2_DCM_SET_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
#define	DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK   (0x40000000U)
#define	DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT   (30U)
#define	DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT)) & DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK)

REG3 - DCDC Register 3
#define	DCDC_REG3_IN_BROWNOUT_MASK   (0x4000U)
#define	DCDC_REG3_IN_BROWNOUT_SHIFT   (14U)
#define	DCDC_REG3_IN_BROWNOUT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK)
#define	DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK   (0x8000U)
#define	DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT   (15U)
#define	DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK)
#define	DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK   (0x10000U)
#define	DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT   (16U)
#define	DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK)
#define	DCDC_REG3_OVERCUR_DETECT_OUT_MASK   (0x20000U)
#define	DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT   (17U)
#define	DCDC_REG3_OVERCUR_DETECT_OUT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK)
#define	DCDC_REG3_ENABLE_FF_MASK   (0x40000U)
#define	DCDC_REG3_ENABLE_FF_SHIFT   (18U)
#define	DCDC_REG3_ENABLE_FF(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK)
#define	DCDC_REG3_DISABLE_PULSE_SKIP_MASK   (0x80000U)
#define	DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT   (19U)
#define	DCDC_REG3_DISABLE_PULSE_SKIP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK)
#define	DCDC_REG3_DISABLE_IDLE_SKIP_MASK   (0x100000U)
#define	DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT   (20U)
#define	DCDC_REG3_DISABLE_IDLE_SKIP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK)
#define	DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK   (0x200000U)
#define	DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT   (21U)
#define	DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK)
#define	DCDC_REG3_REG_FBK_SEL_MASK   (0xC00000U)
#define	DCDC_REG3_REG_FBK_SEL_SHIFT   (22U)
#define	DCDC_REG3_REG_FBK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_REG_FBK_SEL_SHIFT)) & DCDC_REG3_REG_FBK_SEL_MASK)
#define	DCDC_REG3_MINPWR_DC_HALFCLK_MASK   (0x1000000U)
#define	DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT   (24U)
#define	DCDC_REG3_MINPWR_DC_HALFCLK(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
#define	DCDC_REG3_MINPWR_HALF_FETS_MASK   (0x4000000U)
#define	DCDC_REG3_MINPWR_HALF_FETS_SHIFT   (26U)
#define	DCDC_REG3_MINPWR_HALF_FETS(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_MINPWR_HALF_FETS_MASK)
#define	DCDC_REG3_MISC_DELAY_TIMING_MASK   (0x8000000U)
#define	DCDC_REG3_MISC_DELAY_TIMING_SHIFT   (27U)
#define	DCDC_REG3_MISC_DELAY_TIMING(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
#define	DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK   (0x20000000U)
#define	DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT   (29U)
#define	DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
#define	DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK   (0x40000000U)
#define	DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT   (30U)
#define	DCDC_REG3_VDD1P8CTRL_DISABLE_STEP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK)

REG4 - DCDC Register 4
#define	DCDC_REG4_ENABLE_SP_MASK   (0xFFFFU)
#define	DCDC_REG4_ENABLE_SP_SHIFT   (0U)
#define	DCDC_REG4_ENABLE_SP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_ENABLE_SP_SHIFT)) & DCDC_REG4_ENABLE_SP_MASK)

REG5 - DCDC Register 5
#define	DCDC_REG5_DIG_EN_SP_MASK   (0xFFFFU)
#define	DCDC_REG5_DIG_EN_SP_SHIFT   (0U)
#define	DCDC_REG5_DIG_EN_SP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG5_DIG_EN_SP_SHIFT)) & DCDC_REG5_DIG_EN_SP_MASK)

REG6 - DCDC Register 6
#define	DCDC_REG6_LP_MODE_SP_MASK   (0xFFFFU)
#define	DCDC_REG6_LP_MODE_SP_SHIFT   (0U)
#define	DCDC_REG6_LP_MODE_SP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_LP_MODE_SP_SHIFT)) & DCDC_REG6_LP_MODE_SP_MASK)

REG7 - DCDC Register 7
#define	DCDC_REG7_STBY_EN_SP_MASK   (0xFFFFU)
#define	DCDC_REG7_STBY_EN_SP_SHIFT   (0U)
#define	DCDC_REG7_STBY_EN_SP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_STBY_EN_SP_SHIFT)) & DCDC_REG7_STBY_EN_SP_MASK)

REG7P - DCDC Register 7 plus
#define	DCDC_REG7P_STBY_LP_MODE_SP_MASK   (0xFFFFU)
#define	DCDC_REG7P_STBY_LP_MODE_SP_SHIFT   (0U)
#define	DCDC_REG7P_STBY_LP_MODE_SP(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG7P_STBY_LP_MODE_SP_SHIFT)) & DCDC_REG7P_STBY_LP_MODE_SP_MASK)

REG8 - DCDC Register 8
#define	DCDC_REG8_ANA_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG8_ANA_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG8_ANA_TRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG8_ANA_TRG_SP0_SHIFT)) & DCDC_REG8_ANA_TRG_SP0_MASK)

REG9 - DCDC Register 9
#define	DCDC_REG9_ANA_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG9_ANA_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG9_ANA_TRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG9_ANA_TRG_SP1_SHIFT)) & DCDC_REG9_ANA_TRG_SP1_MASK)

REG10 - DCDC Register 10
#define	DCDC_REG10_ANA_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG10_ANA_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG10_ANA_TRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG10_ANA_TRG_SP2_SHIFT)) & DCDC_REG10_ANA_TRG_SP2_MASK)

REG11 - DCDC Register 11
#define	DCDC_REG11_ANA_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG11_ANA_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG11_ANA_TRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG11_ANA_TRG_SP3_SHIFT)) & DCDC_REG11_ANA_TRG_SP3_MASK)

REG12 - DCDC Register 12
#define	DCDC_REG12_DIG_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG12_DIG_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG12_DIG_TRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG12_DIG_TRG_SP0_SHIFT)) & DCDC_REG12_DIG_TRG_SP0_MASK)

REG13 - DCDC Register 13
#define	DCDC_REG13_DIG_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG13_DIG_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG13_DIG_TRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG13_DIG_TRG_SP1_SHIFT)) & DCDC_REG13_DIG_TRG_SP1_MASK)

REG14 - DCDC Register 14
#define	DCDC_REG14_DIG_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG14_DIG_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG14_DIG_TRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG14_DIG_TRG_SP2_SHIFT)) & DCDC_REG14_DIG_TRG_SP2_MASK)

REG15 - DCDC Register 15
#define	DCDC_REG15_DIG_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG15_DIG_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG15_DIG_TRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG15_DIG_TRG_SP3_SHIFT)) & DCDC_REG15_DIG_TRG_SP3_MASK)

REG16 - DCDC Register 16
#define	DCDC_REG16_ANA_STBY_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG16_ANA_STBY_TRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT)) & DCDC_REG16_ANA_STBY_TRG_SP0_MASK)

REG17 - DCDC Register 17
#define	DCDC_REG17_ANA_STBY_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG17_ANA_STBY_TRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)

REG18 - DCDC Register 18
#define	DCDC_REG18_ANA_STBY_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG18_ANA_STBY_TRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)

REG19 - DCDC Register 19
#define	DCDC_REG19_ANA_STBY_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG19_ANA_STBY_TRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)

REG20 - DCDC Register 20
#define	DCDC_REG20_DIG_STBY_TRG_SP0_MASK   (0xFFFFFFFFU)
#define	DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT   (0U)
#define	DCDC_REG20_DIG_STBY_TRG_SP0(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT)) & DCDC_REG20_DIG_STBY_TRG_SP0_MASK)

REG21 - DCDC Register 21
#define	DCDC_REG21_DIG_STBY_TRG_SP1_MASK   (0xFFFFFFFFU)
#define	DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT   (0U)
#define	DCDC_REG21_DIG_STBY_TRG_SP1(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT)) & DCDC_REG21_DIG_STBY_TRG_SP1_MASK)

REG22 - DCDC Register 22
#define	DCDC_REG22_DIG_STBY_TRG_SP2_MASK   (0xFFFFFFFFU)
#define	DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT   (0U)
#define	DCDC_REG22_DIG_STBY_TRG_SP2(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT)) & DCDC_REG22_DIG_STBY_TRG_SP2_MASK)

REG23 - DCDC Register 23
#define	DCDC_REG23_DIG_STBY_TRG_SP3_MASK   (0xFFFFFFFFU)
#define	DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT   (0U)
#define	DCDC_REG23_DIG_STBY_TRG_SP3(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT)) & DCDC_REG23_DIG_STBY_TRG_SP3_MASK)

REG24 - DCDC Register 24
#define	DCDC_REG24_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	DCDC_REG24_OK_COUNT_SHIFT   (0U)
#define	DCDC_REG24_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)

Detailed Description

Macro Definition Documentation

DCDC_CTRL0_CONTROL_MODE [1/2]

#define DCDC_CTRL0_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)

CONTROL_MODE - Control mode 0b0..Software control mode 0b1..Hardware control mode (controlled by GPC Setpoints)

DCDC_CTRL0_CONTROL_MODE [2/2]

#define DCDC_CTRL0_CONTROL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)

CONTROL_MODE - Control mode 0b0..Software control mode 0b1..Hardware control mode (controlled by GPC Setpoints)

DCDC_CTRL0_DEBUG_BITS [1/2]

#define DCDC_CTRL0_DEBUG_BITS

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK)

DEBUG_BITS - DEBUG_BITS[11:0]

DCDC_CTRL0_DEBUG_BITS [2/2]

#define DCDC_CTRL0_DEBUG_BITS

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK)

DEBUG_BITS - DEBUG_BITS[11:0]

DCDC_CTRL0_DIG_EN [1/2]

#define DCDC_CTRL0_DIG_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK)

DIG_EN 0b0..Reserved 0b1..Enable

DCDC_CTRL0_DIG_EN [2/2]

#define DCDC_CTRL0_DIG_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK)

DIG_EN 0b0..Reserved 0b1..Enable

DCDC_CTRL0_ENABLE [1/2]

#define DCDC_CTRL0_ENABLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)

ENABLE 0b0..Disable (Bypass) 0b1..Enable

DCDC_CTRL0_ENABLE [2/2]

#define DCDC_CTRL0_ENABLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)

ENABLE 0b0..Disable (Bypass) 0b1..Enable

DCDC_CTRL0_ENABLE_DCDC_CNT [1/2]

#define DCDC_CTRL0_ENABLE_DCDC_CNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK)

ENABLE_DCDC_CNT - Enable internal count for DCDC_OK timeout 0b0..Wait DCDC_OK for ACK 0b1..Enable internal count for DCDC_OK timeout

DCDC_CTRL0_ENABLE_DCDC_CNT [2/2]

#define DCDC_CTRL0_ENABLE_DCDC_CNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK)

ENABLE_DCDC_CNT - Enable internal count for DCDC_OK timeout 0b0..Wait DCDC_OK for ACK 0b1..Enable internal count for DCDC_OK timeout

DCDC_CTRL0_LP_MODE_EN [1/2]

#define DCDC_CTRL0_LP_MODE_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK)

LP_MODE_EN 0b1..Enter into low-power mode

DCDC_CTRL0_LP_MODE_EN [2/2]

#define DCDC_CTRL0_LP_MODE_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK)

LP_MODE_EN 0b1..Enter into low-power mode

DCDC_CTRL0_STBY_EN [1/2]

#define DCDC_CTRL0_STBY_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK)

STBY_EN 0b1..Enter into standby mode

DCDC_CTRL0_STBY_EN [2/2]

#define DCDC_CTRL0_STBY_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK)

STBY_EN 0b1..Enter into standby mode

DCDC_CTRL0_STBY_LP_MODE_EN [1/2]

#define DCDC_CTRL0_STBY_LP_MODE_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK)

STBY_LP_MODE_EN 0b0..Disable DCDC entry into low-power mode from a GPC standby request 0b1..Enable DCDC to enter into low-power mode from a GPC standby request

DCDC_CTRL0_STBY_LP_MODE_EN [2/2]

#define DCDC_CTRL0_STBY_LP_MODE_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK)

STBY_LP_MODE_EN 0b0..Disable DCDC entry into low-power mode from a GPC standby request 0b1..Enable DCDC to enter into low-power mode from a GPC standby request

DCDC_CTRL0_TRIM_HOLD [1/2]

#define DCDC_CTRL0_TRIM_HOLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK)

TRIM_HOLD - Hold trim input 0b0..Sample trim input 0b1..Hold trim input

DCDC_CTRL0_TRIM_HOLD [2/2]

#define DCDC_CTRL0_TRIM_HOLD

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK)

TRIM_HOLD - Hold trim input 0b0..Sample trim input 0b1..Hold trim input

DCDC_CTRL1_VDD1P0CTRL_STBY_TRG [1/2]

#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)

VDD1P0CTRL_STBY_TRG 0b11111..1.4V 0b01111..1.0V 0b00000..0.625V

DCDC_CTRL1_VDD1P0CTRL_STBY_TRG [2/2]

#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)

VDD1P0CTRL_STBY_TRG 0b11111..1.4V 0b01111..1.0V 0b00000..0.625V

DCDC_CTRL1_VDD1P0CTRL_TRG [1/2]

#define DCDC_CTRL1_VDD1P0CTRL_TRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)

VDD1P0CTRL_TRG 0b11111..1.375V 0b10000..1.0V 0b00000..0.6V

DCDC_CTRL1_VDD1P0CTRL_TRG [2/2]

#define DCDC_CTRL1_VDD1P0CTRL_TRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)

VDD1P0CTRL_TRG 0b11111..1.375V 0b10000..1.0V 0b00000..0.6V

DCDC_CTRL1_VDD1P8CTRL_STBY_TRG [1/2]

#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK)

VDD1P8CTRL_STBY_TRG 0b11111..2.3V 0b01011..1.8V 0b00000..1.525V

DCDC_CTRL1_VDD1P8CTRL_STBY_TRG [2/2]

#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK)

VDD1P8CTRL_STBY_TRG 0b11111..2.3V 0b01011..1.8V 0b00000..1.525V

DCDC_CTRL1_VDD1P8CTRL_TRG [1/2]

#define DCDC_CTRL1_VDD1P8CTRL_TRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)

VDD1P8CTRL_TRG 0b11111..2.275V 0b01100..1.8V 0b00000..1.5V

DCDC_CTRL1_VDD1P8CTRL_TRG [2/2]

#define DCDC_CTRL1_VDD1P8CTRL_TRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)

VDD1P8CTRL_TRG 0b11111..2.275V 0b01100..1.8V 0b00000..1.5V

DCDC_REG0_CUR_SNS_THRSH [1/3]

#define DCDC_REG0_CUR_SNS_THRSH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)

CUR_SNS_THRSH - Current Sense (detector) Threshold 0b000..150 mA 0b001..250 mA 0b010..350 mA 0b011..450 mA 0b100..550 mA 0b101..650 mA

DCDC_REG0_CUR_SNS_THRSH [2/3]

#define DCDC_REG0_CUR_SNS_THRSH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)

CUR_SNS_THRSH - Current Sense (detector) Threshold

DCDC_REG0_CUR_SNS_THRSH [3/3]

#define DCDC_REG0_CUR_SNS_THRSH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)

CUR_SNS_THRSH - Current Sense (detector) Threshold

DCDC_REG0_CURRENT_ALERT_RESET

#define DCDC_REG0_CURRENT_ALERT_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)

CURRENT_ALERT_RESET - Reset Current Alert Signal 0b0..Current Alert Signal not reset 0b1..Current Alert Signal reset

DCDC_REG0_DISABLE_AUTO_CLK_SWITCH [1/3]

#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)

DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch 0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal ring OSC to 24M xtal automatically 0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses

DCDC_REG0_DISABLE_AUTO_CLK_SWITCH [2/3]

#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)

DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch 0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal ring oscillator to 24M xtal automatically 0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses

DCDC_REG0_DISABLE_AUTO_CLK_SWITCH [3/3]

#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)

DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch 0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal ring oscillator to 24M xtal automatically 0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses

DCDC_REG0_EN_LP_OVERLOAD_SNS

#define DCDC_REG0_EN_LP_OVERLOAD_SNS

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)

EN_LP_OVERLOAD_SNS - Low Power Overload Sense Enable 0b0..Overload Detection in power save mode disabled 0b1..Overload Detection in power save mode enabled

DCDC_REG0_LP_HIGH_HYS [1/3]

#define DCDC_REG0_LP_HIGH_HYS

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)

LP_HIGH_HYS - Low Power High Hysteric Value 0b0..Adjust hysteretic value in low power to 12.5mV 0b1..Adjust hysteretic value in low power to 25mV

DCDC_REG0_LP_HIGH_HYS [2/3]

#define DCDC_REG0_LP_HIGH_HYS

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)

LP_HIGH_HYS - Low Power High Hysteric Value 0b0..Adjust hysteretic value in low power to 12.5mV 0b1..Adjust hysteretic value in low power to 25mV

DCDC_REG0_LP_HIGH_HYS [3/3]

#define DCDC_REG0_LP_HIGH_HYS

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)

LP_HIGH_HYS - Low Power High Hysteric Value 0b0..Adjust hysteretic value in low power to 12.5mV 0b1..Adjust hysteretic value in low power to 25mV

DCDC_REG0_LP_OVERLOAD_FREQ_SEL

#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)

LP_OVERLOAD_FREQ_SEL - Low Power Overload Frequency Select 0b0..eight 32k cycle 0b1..sixteen 32k cycle

DCDC_REG0_LP_OVERLOAD_THRSH

#define DCDC_REG0_LP_OVERLOAD_THRSH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)

LP_OVERLOAD_THRSH - Low Power Overload Threshold 0b00..32 0b01..64 0b10..16 0b11..8

DCDC_REG0_OVERCUR_TRIG_ADJ

#define DCDC_REG0_OVERCUR_TRIG_ADJ

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)

OVERCUR_TRIG_ADJ - Overcurrent Trigger Adjust 0b00..In Run Mode, 1 A. In Power Save Mode, 0.25 A 0b01..In Run Mode, 2 A. In Power Save Mode, 0.25 A 0b10..In Run Mode, 1 A. In Power Save Mode, 0.2 A 0b11..In Run Mode, 2 A. In Power Save Mode, 0.2 A

DCDC_REG0_PWD_CMP_BATT_DET

#define DCDC_REG0_PWD_CMP_BATT_DET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)

PWD_CMP_BATT_DET - Power Down Battery Detection Comparator 0b0..Low voltage detection comparator is enabled 0b1..Low voltage detection comparator is disabled

DCDC_REG0_PWD_CMP_DCDC_IN_DET [1/2]

#define DCDC_REG0_PWD_CMP_DCDC_IN_DET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK)

PWD_CMP_DCDC_IN_DET 0b0..Low voltage detection comparator is enabled 0b1..Low voltage detection comparator is disabled

DCDC_REG0_PWD_CMP_DCDC_IN_DET [2/2]

#define DCDC_REG0_PWD_CMP_DCDC_IN_DET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK)

PWD_CMP_DCDC_IN_DET 0b0..Low voltage detection comparator is enabled 0b1..Low voltage detection comparator is disabled

DCDC_REG0_PWD_CMP_OFFSET [1/3]

#define DCDC_REG0_PWD_CMP_OFFSET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)

PWD_CMP_OFFSET - Power down output range comparator 0b0..Output range comparator powered up 0b1..Output range comparator powered down

DCDC_REG0_PWD_CMP_OFFSET [2/3]

#define DCDC_REG0_PWD_CMP_OFFSET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)

PWD_CMP_OFFSET - power down the out-of-range detection comparator 0b0..Out-of-range comparator powered up 0b1..Out-of-range comparator powered down

DCDC_REG0_PWD_CMP_OFFSET [3/3]

#define DCDC_REG0_PWD_CMP_OFFSET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)

PWD_CMP_OFFSET - power down the out-of-range detection comparator 0b0..Out-of-range comparator powered up 0b1..Out-of-range comparator powered down

DCDC_REG0_PWD_CUR_SNS_CMP [1/3]

#define DCDC_REG0_PWD_CUR_SNS_CMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)

PWD_CUR_SNS_CMP - Power down signal of the current detector. 0b0..Current Detector powered up 0b1..Current Detector powered down

DCDC_REG0_PWD_CUR_SNS_CMP [2/3]

#define DCDC_REG0_PWD_CUR_SNS_CMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)

PWD_CUR_SNS_CMP - Power down signal of the current detector 0b0..Current Detector powered up 0b1..Current Detector powered down

DCDC_REG0_PWD_CUR_SNS_CMP [3/3]

#define DCDC_REG0_PWD_CUR_SNS_CMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)

PWD_CUR_SNS_CMP - Power down signal of the current detector 0b0..Current Detector powered up 0b1..Current Detector powered down

DCDC_REG0_PWD_HIGH_VDD1P0_DET [1/2]

#define DCDC_REG0_PWD_HIGH_VDD1P0_DET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK)

PWD_HIGH_VDD1P0_DET - Power Down High Voltage Detection for VDD1P0 0b0..Overvoltage detection comparator for the VDD1P0 output is enabled 0b1..Overvoltage detection comparator for the VDD1P0 output is disabled

DCDC_REG0_PWD_HIGH_VDD1P0_DET [2/2]

#define DCDC_REG0_PWD_HIGH_VDD1P0_DET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK)

PWD_HIGH_VDD1P0_DET - Power Down High Voltage Detection for VDD1P0 0b0..Overvoltage detection comparator for the VDD1P0 output is enabled 0b1..Overvoltage detection comparator for the VDD1P0 output is disabled

DCDC_REG0_PWD_HIGH_VDD1P8_DET [1/2]

#define DCDC_REG0_PWD_HIGH_VDD1P8_DET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK)

PWD_HIGH_VDD1P8_DET - Power Down High Voltage Detection for VDD1P8 0b0..Overvoltage detection comparator for the VDD1P8 output is enabled 0b1..Overvoltage detection comparator for the VDD1P8 output is disabled

DCDC_REG0_PWD_HIGH_VDD1P8_DET [2/2]

#define DCDC_REG0_PWD_HIGH_VDD1P8_DET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK)

PWD_HIGH_VDD1P8_DET - Power Down High Voltage Detection for VDD1P8 0b0..Overvoltage detection comparator for the VDD1P8 output is enabled 0b1..Overvoltage detection comparator for the VDD1P8 output is disabled

DCDC_REG0_PWD_HIGH_VOLT_DET

#define DCDC_REG0_PWD_HIGH_VOLT_DET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)

PWD_HIGH_VOLT_DET - Power Down High Voltage Detection 0b0..Overvoltage detection comparator is enabled 0b1..Overvoltage detection comparator is disabled

DCDC_REG0_PWD_OSC_INT [1/3]

#define DCDC_REG0_PWD_OSC_INT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)

PWD_OSC_INT - Power down internal osc 0b0..Internal oscillator powered up 0b1..Internal oscillator powered down

DCDC_REG0_PWD_OSC_INT [2/3]

#define DCDC_REG0_PWD_OSC_INT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)

PWD_OSC_INT - Power down internal ring oscillator 0b0..Internal ring oscillator powered up 0b1..Internal ring oscillator powered down

DCDC_REG0_PWD_OSC_INT [3/3]

#define DCDC_REG0_PWD_OSC_INT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)

PWD_OSC_INT - Power down internal ring oscillator 0b0..Internal ring oscillator powered up 0b1..Internal ring oscillator powered down

DCDC_REG0_PWD_OVERCUR_DET [1/3]

#define DCDC_REG0_PWD_OVERCUR_DET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)

PWD_OVERCUR_DET - Power down overcurrent detection comparator 0b0..Overcurrent detection comparator is enabled 0b1..Overcurrent detection comparator is disabled

DCDC_REG0_PWD_OVERCUR_DET [2/3]

#define DCDC_REG0_PWD_OVERCUR_DET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)

PWD_OVERCUR_DET - Power down overcurrent detection comparator 0b0..Overcurrent detection comparator is enabled 0b1..Overcurrent detection comparator is disabled

DCDC_REG0_PWD_OVERCUR_DET [3/3]

#define DCDC_REG0_PWD_OVERCUR_DET

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)

PWD_OVERCUR_DET - Power down overcurrent detection comparator 0b0..Overcurrent detection comparator is enabled 0b1..Overcurrent detection comparator is disabled

DCDC_REG0_PWD_ZCD [1/3]

#define DCDC_REG0_PWD_ZCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)

PWD_ZCD - Power Down Zero Cross Detection 0b0..Zero cross detetion function powered up 0b1..Zero cross detetion function powered down

DCDC_REG0_PWD_ZCD [2/3]

#define DCDC_REG0_PWD_ZCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)

PWD_ZCD - Power Down Zero Cross Detection 0b0..Zero cross detetion function powered up 0b1..Zero cross detetion function powered down

DCDC_REG0_PWD_ZCD [3/3]

#define DCDC_REG0_PWD_ZCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)

PWD_ZCD - Power Down Zero Cross Detection 0b0..Zero cross detetion function powered up 0b1..Zero cross detetion function powered down

DCDC_REG0_SEL_CLK [1/3]

#define DCDC_REG0_SEL_CLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)

SEL_CLK - Select Clock 0b0..DCDC uses internal ring oscillator 0b1..DCDC uses 24M xtal

DCDC_REG0_SEL_CLK [2/3]

#define DCDC_REG0_SEL_CLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)

SEL_CLK - Select Clock 0b0..DCDC uses internal ring oscillator 0b1..DCDC uses 24M xtal

DCDC_REG0_SEL_CLK [3/3]

#define DCDC_REG0_SEL_CLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)

SEL_CLK - Select Clock 0b0..DCDC uses internal ring oscillator 0b1..DCDC uses 24M xtal

DCDC_REG0_STS_DC_OK [1/3]

#define DCDC_REG0_STS_DC_OK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)

STS_DC_OK - DCDC Output OK 0b0..DCDC is settling 0b1..DCDC already settled

DCDC_REG0_STS_DC_OK [2/3]

#define DCDC_REG0_STS_DC_OK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)

STS_DC_OK - DCDC Output OK 0b0..DCDC is settling 0b1..DCDC already settled

DCDC_REG0_STS_DC_OK [3/3]

#define DCDC_REG0_STS_DC_OK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)

STS_DC_OK - DCDC Output OK 0b0..DCDC is settling 0b1..DCDC already settled

DCDC_REG0_XTAL_24M_OK [1/3]

#define DCDC_REG0_XTAL_24M_OK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)

XTAL_24M_OK - 24M XTAL OK 0b0..DCDC uses internal ring OSC 0b1..DCDC uses xtal 24M

DCDC_REG0_XTAL_24M_OK [2/3]

#define DCDC_REG0_XTAL_24M_OK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)

XTAL_24M_OK - 24M XTAL OK 0b0..DCDC uses internal ring oscillator 0b1..DCDC uses xtal 24M

DCDC_REG0_XTAL_24M_OK [3/3]

#define DCDC_REG0_XTAL_24M_OK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)

XTAL_24M_OK - 24M XTAL OK 0b0..DCDC uses internal ring oscillator 0b1..DCDC uses xtal 24M

DCDC_REG0_XTALOK_DISABLE [1/3]

#define DCDC_REG0_XTALOK_DISABLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)

XTALOK_DISABLE - Disable xtalok detection circuit 0b0..Enable xtalok detection circuit 0b1..Disable xtalok detection circuit and always outputs OK signal "1"

DCDC_REG0_XTALOK_DISABLE [2/3]

#define DCDC_REG0_XTALOK_DISABLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)

XTALOK_DISABLE - Disable xtalok detection circuit 0b0..Enable xtalok detection circuit 0b1..Disable xtalok detection circuit and always outputs OK signal "1"

DCDC_REG0_XTALOK_DISABLE [3/3]

#define DCDC_REG0_XTALOK_DISABLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)

XTALOK_DISABLE - Disable xtalok detection circuit 0b0..Enable xtalok detection circuit 0b1..Disable xtalok detection circuit and always outputs OK signal "1"

DCDC_REG1_DM_CTRL [1/2]

#define DCDC_REG1_DM_CTRL

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DM_CTRL_SHIFT)) & DCDC_REG1_DM_CTRL_MASK)

DM_CTRL - DM Control 0b0..No change to ripple when the discontinuous current is present in DCM. 0b1..Improves ripple when the inductor current goes to zero in DCM.

DCDC_REG1_DM_CTRL [2/2]

#define DCDC_REG1_DM_CTRL

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DM_CTRL_SHIFT)) & DCDC_REG1_DM_CTRL_MASK)

DM_CTRL - DM Control 0b0..No change to ripple when the discontinuous current is present in DCM. 0b1..Improves ripple when the inductor current goes to zero in DCM.

DCDC_REG1_LOOPCTRL_CM_HST_THRESH [1/2]

#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK)

LOOPCTRL_CM_HST_THRESH - Increase Threshold Detection

DCDC_REG1_LOOPCTRL_CM_HST_THRESH [2/2]

#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK)

LOOPCTRL_CM_HST_THRESH - Increase Threshold Detection

DCDC_REG1_LOOPCTRL_DF_HST_THRESH [1/2]

#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)

LOOPCTRL_DF_HST_THRESH - Increase Threshold Detection

DCDC_REG1_LOOPCTRL_DF_HST_THRESH [2/2]

#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)

LOOPCTRL_DF_HST_THRESH - Increase Threshold Detection

DCDC_REG1_LOOPCTRL_EN_CM_HYST [1/2]

#define DCDC_REG1_LOOPCTRL_EN_CM_HYST

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK)

LOOPCTRL_EN_CM_HYST 0b0..Disable hysteresis in switching converter common mode analog comparators 0b1..Enable hysteresis in switching converter common mode analog comparators

DCDC_REG1_LOOPCTRL_EN_CM_HYST [2/2]

#define DCDC_REG1_LOOPCTRL_EN_CM_HYST

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK)

LOOPCTRL_EN_CM_HYST 0b0..Disable hysteresis in switching converter common mode analog comparators 0b1..Enable hysteresis in switching converter common mode analog comparators

DCDC_REG1_LOOPCTRL_EN_DF_HYST [1/2]

#define DCDC_REG1_LOOPCTRL_EN_DF_HYST

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK)

LOOPCTRL_EN_DF_HYST 0b0..Disable hysteresis in switching converter differential mode analog comparators 0b1..Enable hysteresis in switching converter differential mode analog comparators

DCDC_REG1_LOOPCTRL_EN_DF_HYST [2/2]

#define DCDC_REG1_LOOPCTRL_EN_DF_HYST

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK)

LOOPCTRL_EN_DF_HYST 0b0..Disable hysteresis in switching converter differential mode analog comparators 0b1..Enable hysteresis in switching converter differential mode analog comparators

DCDC_REG1_LOOPCTRL_EN_HYST

#define DCDC_REG1_LOOPCTRL_EN_HYST

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)

LOOPCTRL_EN_HYST - Enable Hysteresis 0b0..Disable hysteresis in switching converter common mode analog comparators 0b1..Enable hysteresis in switching converter common mode analog comparators

DCDC_REG1_LOOPCTRL_HST_THRESH

#define DCDC_REG1_LOOPCTRL_HST_THRESH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)

LOOPCTRL_HST_THRESH - Increase Threshold Detection 0b0..Lower hysteresis threshold (about 2.5mV in typical, but this value can vary with PVT corners 0b1..Higher hysteresis threshold (about 5mV in typical)

DCDC_REG1_LP_CMP_ISRC_SEL [1/3]

#define DCDC_REG1_LP_CMP_ISRC_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)

LP_CMP_ISRC_SEL - Low Power Comparator Current Bias 0b00..50 nA 0b01..100 nA 0b10..200 nA 0b11..400 nA

DCDC_REG1_LP_CMP_ISRC_SEL [2/3]

#define DCDC_REG1_LP_CMP_ISRC_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)

LP_CMP_ISRC_SEL - Low Power Comparator Current Bias 0b00..50nA 0b01..100nA 0b10..200nA 0b11..400nA

DCDC_REG1_LP_CMP_ISRC_SEL [3/3]

#define DCDC_REG1_LP_CMP_ISRC_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)

LP_CMP_ISRC_SEL - Low Power Comparator Current Bias 0b00..50nA 0b01..100nA 0b10..200nA 0b11..400nA

DCDC_REG1_REG_FBK_SEL

#define DCDC_REG1_REG_FBK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)

REG_FBK_SEL 0b00..The regulator outputs 1.0V with 1.2V reference voltage 0b01..The regulator outputs 1.1V with 1.2V reference voltage 0b10..The regulator outputs 1.0V with 1.3V reference voltage 0b11..The regulator outputs 1.1V with 1.3V reference voltage

DCDC_REG1_REG_RLOAD_SW

#define DCDC_REG1_REG_RLOAD_SW

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)

REG_RLOAD_SW 0b0..Load resistor disconnected 0b1..Load resistor connected

DCDC_REG1_RLOAD_REG_EN_LPSR [1/2]

#define DCDC_REG1_RLOAD_REG_EN_LPSR

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)

RLOAD_REG_EN_LPSR - Load Resistor Enable 0b0..Disconnect load resistor 0b1..Connect load resistor

DCDC_REG1_RLOAD_REG_EN_LPSR [2/2]

#define DCDC_REG1_RLOAD_REG_EN_LPSR

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)

RLOAD_REG_EN_LPSR - Load Resistor Enable 0b0..Disconnect load resistor 0b1..Connect load resistor

DCDC_REG1_VBG_TRIM [1/3]

#define DCDC_REG1_VBG_TRIM

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)

VBG_TRIM - Trim Bandgap Voltage

DCDC_REG1_VBG_TRIM [2/3]

#define DCDC_REG1_VBG_TRIM

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)

VBG_TRIM - Trim Bandgap Voltage 0b00000..0.452V 0b10000..0.5V 0b11111..0.545V

DCDC_REG1_VBG_TRIM [3/3]

#define DCDC_REG1_VBG_TRIM

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)

VBG_TRIM - Trim Bandgap Voltage 0b00000..0.452V 0b10000..0.5V 0b11111..0.545V

DCDC_REG2_DCM_SET_CTRL [1/3]

#define DCDC_REG2_DCM_SET_CTRL

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)

DCM_SET_CTRL - DCM Set Control

DCDC_REG2_DCM_SET_CTRL [2/3]

#define DCDC_REG2_DCM_SET_CTRL

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)

DCM_SET_CTRL - DCM Set Control

DCDC_REG2_DCM_SET_CTRL [3/3]

#define DCDC_REG2_DCM_SET_CTRL

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)

DCM_SET_CTRL - DCM Set Control

DCDC_REG2_DISABLE_PULSE_SKIP

#define DCDC_REG2_DISABLE_PULSE_SKIP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)

DISABLE_PULSE_SKIP - Disable Pulse Skip 0b0..DCDC will be idle to save current dissipation when the duty cycle get to the low limit which is set by NEGLIMIT_IN. 0b1..DCDC will keep working with the low limited duty cycle NEGLIMIT_IN.

DCDC_REG2_LOOPCTRL_EN_RCSCALE [1/3]

#define DCDC_REG2_LOOPCTRL_EN_RCSCALE

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)

LOOPCTRL_EN_RCSCALE - Enable RC Scale

DCDC_REG2_LOOPCTRL_EN_RCSCALE [2/3]

#define DCDC_REG2_LOOPCTRL_EN_RCSCALE

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)

LOOPCTRL_EN_RCSCALE - Enable RC Scale

DCDC_REG2_LOOPCTRL_EN_RCSCALE [3/3]

#define DCDC_REG2_LOOPCTRL_EN_RCSCALE

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)

LOOPCTRL_EN_RCSCALE - Enable RC Scale

DCDC_REG2_LOOPCTRL_HYST_SIGN

#define DCDC_REG2_LOOPCTRL_HYST_SIGN

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)

LOOPCTRL_HYST_SIGN 0b0..Do not invert sign of the hysteresis 0b1..Invert sign of the hysteresis

DCDC_REG2_LOOPCTRL_RCSCALE_THRSH

#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)

LOOPCTRL_RCSCALE_THRSH 0b0..Do not increase the threshold detection for RC scale circuit. 0b1..Increase the threshold detection for RC scale circuit.

DCDC_REG3_DISABLE_IDLE_SKIP [1/2]

#define DCDC_REG3_DISABLE_IDLE_SKIP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK)

DISABLE_IDLE_SKIP 0b0..Enable the idle skip function. The DCDC will be idle when out-of-range comparator detects the output voltage is higher than the target by 25mV. This function requires the out-of-range comparator to be enabled (PWD_CMP_OFFSET=0).

DCDC_REG3_DISABLE_IDLE_SKIP [2/2]

#define DCDC_REG3_DISABLE_IDLE_SKIP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK)

DISABLE_IDLE_SKIP 0b0..Enable the idle skip function. The DCDC will be idle when out-of-range comparator detects the output voltage is higher than the target by 25mV. This function requires the out-of-range comparator to be enabled (PWD_CMP_OFFSET=0).

DCDC_REG3_DISABLE_PULSE_SKIP [1/2]

#define DCDC_REG3_DISABLE_PULSE_SKIP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK)

DISABLE_PULSE_SKIP - Disable Pulse Skip 0b0..Stop charging if the duty cycle is lower than what is set by NEGLIMIT_IN

DCDC_REG3_DISABLE_PULSE_SKIP [2/2]

#define DCDC_REG3_DISABLE_PULSE_SKIP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK)

DISABLE_PULSE_SKIP - Disable Pulse Skip 0b0..Stop charging if the duty cycle is lower than what is set by NEGLIMIT_IN

DCDC_REG3_DISABLE_STEP

#define DCDC_REG3_DISABLE_STEP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)

DISABLE_STEP - Disable Step 0b0..Enable stepping for the output of VDD_SOC of DCDC 0b1..Disable stepping for the output of VDD_SOC of DCDC

DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR [1/2]

#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK)

DOUBLE_IBIAS_CMP_LP_LPSR 0b1..Double the bias current of the comparator for low-voltage detector in LP (low-power) mode

DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR [2/2]

#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK)

DOUBLE_IBIAS_CMP_LP_LPSR 0b1..Double the bias current of the comparator for low-voltage detector in LP (low-power) mode

DCDC_REG3_ENABLE_FF [1/2]

#define DCDC_REG3_ENABLE_FF

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK)

ENABLE_FF 0b1..Enable feed-forward (FF) function that can speed up transient settling.

DCDC_REG3_ENABLE_FF [2/2]

#define DCDC_REG3_ENABLE_FF

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK)

ENABLE_FF 0b1..Enable feed-forward (FF) function that can speed up transient settling.

DCDC_REG3_IN_BROWNOUT [1/2]

#define DCDC_REG3_IN_BROWNOUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK)

IN_BROWNOUT 0b1..DCDC_IN is lower than 2.6V

DCDC_REG3_IN_BROWNOUT [2/2]

#define DCDC_REG3_IN_BROWNOUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK)

IN_BROWNOUT 0b1..DCDC_IN is lower than 2.6V

DCDC_REG3_MINPWR_DC_HALFCLK [1/3]

#define DCDC_REG3_MINPWR_DC_HALFCLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)

MINPWR_DC_HALFCLK 0b0..DCDC clock remains at full frequency for continuous mode 0b1..DCDC clock set to half frequency for continuous mode

DCDC_REG3_MINPWR_DC_HALFCLK [2/3]

#define DCDC_REG3_MINPWR_DC_HALFCLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)

MINPWR_DC_HALFCLK 0b0..DCDC clock remains at full frequency for continuous mode 0b1..DCDC clock set to half frequency for continuous mode

DCDC_REG3_MINPWR_DC_HALFCLK [3/3]

#define DCDC_REG3_MINPWR_DC_HALFCLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)

MINPWR_DC_HALFCLK 0b0..DCDC clock remains at full frequency for continuous mode 0b1..DCDC clock set to half frequency for continuous mode

DCDC_REG3_MISC_DELAY_TIMING [1/2]

#define DCDC_REG3_MISC_DELAY_TIMING

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)

MISC_DELAY_TIMING - Miscellaneous Delay Timing

DCDC_REG3_MISC_DELAY_TIMING [2/2]

#define DCDC_REG3_MISC_DELAY_TIMING

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)

MISC_DELAY_TIMING - Miscellaneous Delay Timing

DCDC_REG3_OVERCUR_DETECT_OUT [1/2]

#define DCDC_REG3_OVERCUR_DETECT_OUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK)

OVERCUR_DETECT_OUT 0b1..Overcurrent

DCDC_REG3_OVERCUR_DETECT_OUT [2/2]

#define DCDC_REG3_OVERCUR_DETECT_OUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK)

OVERCUR_DETECT_OUT 0b1..Overcurrent

DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT [1/2]

#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK)

OVERVOLT_VDD1P0_DET_OUT 0b1..VDD1P0 Overvoltage

DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT [2/2]

#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK)

OVERVOLT_VDD1P0_DET_OUT 0b1..VDD1P0 Overvoltage

DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT [1/2]

#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK)

OVERVOLT_VDD1P8_DET_OUT 0b1..VDD1P8 Overvoltage

DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT [2/2]

#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK)

OVERVOLT_VDD1P8_DET_OUT 0b1..VDD1P8 Overvoltage

DCDC_REG3_TARGET_LP

#define DCDC_REG3_TARGET_LP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)

TARGET_LP - Low Power Target Value 0b000..0.9 V 0b001..0.925 V 0b010..0.95 V 0b011..0.975 V 0b100..1.0 V

DCDC_REG3_TRG

#define DCDC_REG3_TRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)

TRG - Target value of VDD_SOC

DCDC_REG3_VDD1P0CTRL_DISABLE_STEP [1/2]

#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)

VDD1P0CTRL_DISABLE_STEP - Disable Step for VDD1P0 0b0..Enable stepping for VDD1P0 0b1..Disable stepping for VDD1P0

DCDC_REG3_VDD1P0CTRL_DISABLE_STEP [2/2]

#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)

VDD1P0CTRL_DISABLE_STEP - Disable Step for VDD1P0 0b0..Enable stepping for VDD1P0 0b1..Disable stepping for VDD1P0

DCDC_REG3_VDD1P8CTRL_DISABLE_STEP [1/2]

#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK)

VDD1P8CTRL_DISABLE_STEP - Disable Step for VDD1P8 0b0..Enable stepping for VDD1P8 0b1..Disable stepping for VDD1P8

DCDC_REG3_VDD1P8CTRL_DISABLE_STEP [2/2]

#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP

(

x

)

(((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK)

VDD1P8CTRL_DISABLE_STEP - Disable Step for VDD1P8 0b0..Enable stepping for VDD1P8 0b1..Disable stepping for VDD1P8