RTEMS 6.1-rc6
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ISCR - Interrupt Status and Control Register | |
#define | CM7_MCM_ISCR_WABS_MASK (0x20U) |
#define | CM7_MCM_ISCR_WABS_SHIFT (5U) |
#define | CM7_MCM_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABS_SHIFT)) & CM7_MCM_ISCR_WABS_MASK) |
#define | CM7_MCM_ISCR_WABSO_MASK (0x40U) |
#define | CM7_MCM_ISCR_WABSO_SHIFT (6U) |
#define | CM7_MCM_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABSO_SHIFT)) & CM7_MCM_ISCR_WABSO_MASK) |
#define | CM7_MCM_ISCR_FIOC_MASK (0x100U) |
#define | CM7_MCM_ISCR_FIOC_SHIFT (8U) |
#define | CM7_MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOC_SHIFT)) & CM7_MCM_ISCR_FIOC_MASK) |
#define | CM7_MCM_ISCR_FDZC_MASK (0x200U) |
#define | CM7_MCM_ISCR_FDZC_SHIFT (9U) |
#define | CM7_MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZC_SHIFT)) & CM7_MCM_ISCR_FDZC_MASK) |
#define | CM7_MCM_ISCR_FOFC_MASK (0x400U) |
#define | CM7_MCM_ISCR_FOFC_SHIFT (10U) |
#define | CM7_MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFC_SHIFT)) & CM7_MCM_ISCR_FOFC_MASK) |
#define | CM7_MCM_ISCR_FUFC_MASK (0x800U) |
#define | CM7_MCM_ISCR_FUFC_SHIFT (11U) |
#define | CM7_MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFC_SHIFT)) & CM7_MCM_ISCR_FUFC_MASK) |
#define | CM7_MCM_ISCR_FIXC_MASK (0x1000U) |
#define | CM7_MCM_ISCR_FIXC_SHIFT (12U) |
#define | CM7_MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXC_SHIFT)) & CM7_MCM_ISCR_FIXC_MASK) |
#define | CM7_MCM_ISCR_FIDC_MASK (0x8000U) |
#define | CM7_MCM_ISCR_FIDC_SHIFT (15U) |
#define | CM7_MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDC_SHIFT)) & CM7_MCM_ISCR_FIDC_MASK) |
#define | CM7_MCM_ISCR_WABE_MASK (0x200000U) |
#define | CM7_MCM_ISCR_WABE_SHIFT (21U) |
#define | CM7_MCM_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABE_SHIFT)) & CM7_MCM_ISCR_WABE_MASK) |
#define | CM7_MCM_ISCR_FIOCE_MASK (0x1000000U) |
#define | CM7_MCM_ISCR_FIOCE_SHIFT (24U) |
#define | CM7_MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOCE_SHIFT)) & CM7_MCM_ISCR_FIOCE_MASK) |
#define | CM7_MCM_ISCR_FDZCE_MASK (0x2000000U) |
#define | CM7_MCM_ISCR_FDZCE_SHIFT (25U) |
#define | CM7_MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZCE_SHIFT)) & CM7_MCM_ISCR_FDZCE_MASK) |
#define | CM7_MCM_ISCR_FOFCE_MASK (0x4000000U) |
#define | CM7_MCM_ISCR_FOFCE_SHIFT (26U) |
#define | CM7_MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFCE_SHIFT)) & CM7_MCM_ISCR_FOFCE_MASK) |
#define | CM7_MCM_ISCR_FUFCE_MASK (0x8000000U) |
#define | CM7_MCM_ISCR_FUFCE_SHIFT (27U) |
#define | CM7_MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFCE_SHIFT)) & CM7_MCM_ISCR_FUFCE_MASK) |
#define | CM7_MCM_ISCR_FIXCE_MASK (0x10000000U) |
#define | CM7_MCM_ISCR_FIXCE_SHIFT (28U) |
#define | CM7_MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXCE_SHIFT)) & CM7_MCM_ISCR_FIXCE_MASK) |
#define | CM7_MCM_ISCR_FIDCE_MASK (0x80000000U) |
#define | CM7_MCM_ISCR_FIDCE_SHIFT (31U) |
#define | CM7_MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDCE_SHIFT)) & CM7_MCM_ISCR_FIDCE_MASK) |
#define CM7_MCM_ISCR_FDZC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZC_SHIFT)) & CM7_MCM_ISCR_FDZC_MASK) |
FDZC - FPU Divide-by-Zero Interrupt Status 0b0..No interrupt 0b1..Interrupt occured
#define CM7_MCM_ISCR_FDZCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZCE_SHIFT)) & CM7_MCM_ISCR_FDZCE_MASK) |
FDZCE - FPU Divide-by-Zero Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt
#define CM7_MCM_ISCR_FIDC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDC_SHIFT)) & CM7_MCM_ISCR_FIDC_MASK) |
FIDC - FPU Input Denormal Interrupt Status 0b0..No interrupt 0b1..Interrupt occured
#define CM7_MCM_ISCR_FIDCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDCE_SHIFT)) & CM7_MCM_ISCR_FIDCE_MASK) |
FIDCE - FPU Input Denormal Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt
#define CM7_MCM_ISCR_FIOC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOC_SHIFT)) & CM7_MCM_ISCR_FIOC_MASK) |
FIOC - FPU Invalid Operation interrupt Status 0b0..No interrupt 0b1..Interrupt occured
#define CM7_MCM_ISCR_FIOCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOCE_SHIFT)) & CM7_MCM_ISCR_FIOCE_MASK) |
FIOCE - FPU Invalid Operation Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt
#define CM7_MCM_ISCR_FIXC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXC_SHIFT)) & CM7_MCM_ISCR_FIXC_MASK) |
FIXC - FPU Inexact Interrupt Status 0b0..No interrupt 0b1..Interrupt occured
#define CM7_MCM_ISCR_FIXCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXCE_SHIFT)) & CM7_MCM_ISCR_FIXCE_MASK) |
FIXCE - FPU Inexact Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt
#define CM7_MCM_ISCR_FOFC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFC_SHIFT)) & CM7_MCM_ISCR_FOFC_MASK) |
FOFC - FPU Overflow interrupt status 0b0..No interrupt 0b1..Interrupt occured
#define CM7_MCM_ISCR_FOFCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFCE_SHIFT)) & CM7_MCM_ISCR_FOFCE_MASK) |
FOFCE - FPU Overflow Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt
#define CM7_MCM_ISCR_FUFC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFC_SHIFT)) & CM7_MCM_ISCR_FUFC_MASK) |
FUFC - FPU Underflow Interrupt Status 0b0..No interrupt 0b1..Interrupt occured
#define CM7_MCM_ISCR_FUFCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFCE_SHIFT)) & CM7_MCM_ISCR_FUFCE_MASK) |
FUFCE - FPU Underflow Interrupt Enable 0b0..Disable interrupt 0b1..Enable interrupt
#define CM7_MCM_ISCR_WABE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABE_SHIFT)) & CM7_MCM_ISCR_WABE_MASK) |
WABE - TCM Write Abort Interrupt enable 0b0..Disable interrupt 0b1..Enable interrupt
#define CM7_MCM_ISCR_WABS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABS_SHIFT)) & CM7_MCM_ISCR_WABS_MASK) |
WABS - Write Abort on Slave 0b0..No abort 0b1..Abort
#define CM7_MCM_ISCR_WABSO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABSO_SHIFT)) & CM7_MCM_ISCR_WABSO_MASK) |
WABSO - Write Abort on Slave Overrun 0b0..No write abort overrun 0b1..Write abort overrun occurred