RTEMS 6.1-rc6
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Macros

Macros

#define IS_ADC_CONVERSIONDATAMGT(DATA)
 Verify the ADC data conversion setting.
 
#define ADC_GET_RESOLUTION(__HANDLE__)    (LL_ADC_GetResolution((__HANDLE__)->Instance))
 Return resolution bits in CFGR register RES[1:0] field.
 
#define ADC_CLEAR_ERRORCODE(__HANDLE__)   ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
 Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
 
#define ADC_IS_ENABLE(__HANDLE__)
 Verification of ADC state: enabled or disabled.
 
#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)    (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
 Check if conversion is on going on regular group.
 
#define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__)   ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)
 Check if ADC clock mode is synchronous.
 
#define ADC_STATE_CLR_SET   MODIFY_REG
 Simultaneously clear and set specific bits of the handle State.
 
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__)    ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
 Verify that a given value is aligned with the ADC resolution range.
 
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__)   (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
 Verify the length of the scheduled regular conversions group.
 
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER)   (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
 Verify the number of scheduled regular conversions in discontinuous mode.
 
#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__)
 Verify the ADC clock setting.
 
#define IS_ADC_RESOLUTION(__RESOLUTION__)
 Verify the ADC resolution setting.
 
#define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__)   (((__RESOLUTION__) == ADC_RESOLUTION_8B))
 Verify the ADC resolution setting when limited to 8 bits.
 
#define IS_ADC_SCAN_MODE(__SCAN_MODE__)
 Verify the ADC scan mode.
 
#define IS_ADC_EXTTRIG_EDGE(__EDGE__)
 Verify the ADC edge trigger setting for regular group.
 
#define IS_ADC_EXTTRIG(__REGTRIG__)
 Verify the ADC regular conversions external trigger.
 
#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__)
 Verify the ADC regular conversions check for converted data availability.
 
#define IS_ADC_OVERRUN(__OVR__)
 Verify the ADC regular conversions overrun handling.
 
#define IS_ADC_SAMPLE_TIME(__TIME__)
 Verify the ADC conversions sampling time.
 
#define IS_ADC_REGULAR_RANK(__CHANNEL__)
 Verify the ADC regular channel setting.
 

Detailed Description

Macro Definition Documentation

◆ ADC_CLEAR_ERRORCODE

#define ADC_CLEAR_ERRORCODE (   __HANDLE__)    ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").

Parameters
__HANDLE__ADC handle
Return values
None

◆ ADC_GET_RESOLUTION

#define ADC_GET_RESOLUTION (   __HANDLE__)     (LL_ADC_GetResolution((__HANDLE__)->Instance))

Return resolution bits in CFGR register RES[1:0] field.

Parameters
__HANDLE__ADC handle
Return values
Valueof bitfield RES in CFGR register.

◆ ADC_IS_CONVERSION_ONGOING_REGULAR

#define ADC_IS_CONVERSION_ONGOING_REGULAR (   __HANDLE__)     (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))

Check if conversion is on going on regular group.

Parameters
__HANDLE__ADC handle
Return values
Value"0" (no conversion is on going) or value "1" (conversion is on going)

◆ ADC_IS_ENABLE

#define ADC_IS_ENABLE (   __HANDLE__)
Value:
(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
) ? SET : RESET)
#define ADC_FLAG_RDY
Definition: stm32h7xx_hal_adc.h:932
#define ADC_CR_ADEN
Definition: stm32h723xx.h:2802
#define ADC_CR_ADDIS
Definition: stm32h723xx.h:2805

Verification of ADC state: enabled or disabled.

Parameters
__HANDLE__ADC handle
Return values
SET(ADC enabled) or RESET (ADC disabled)

◆ ADC_IS_SYNCHRONOUS_CLOCK_MODE

#define ADC_IS_SYNCHRONOUS_CLOCK_MODE (   __HANDLE__)    ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)

Check if ADC clock mode is synchronous.

Parameters
__HANDLE__ADC handle
Return values
SET(clock mode is synchronous) or RESET (clock mode is asynchronous)

◆ ADC_STATE_CLR_SET

#define ADC_STATE_CLR_SET   MODIFY_REG

Simultaneously clear and set specific bits of the handle State.

Note
ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.
Return values
None

◆ IS_ADC_CLOCKPRESCALER

#define IS_ADC_CLOCKPRESCALER (   __ADC_CLOCK__)
Value:
(((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
#define ADC_CLOCK_ASYNC_DIV10
Definition: stm32h7xx_hal_adc.h:503
#define ADC_CLOCK_ASYNC_DIV1
Definition: stm32h7xx_hal_adc.h:498
#define ADC_CLOCK_SYNC_PCLK_DIV4
Definition: stm32h7xx_hal_adc.h:496
#define ADC_CLOCK_ASYNC_DIV12
Definition: stm32h7xx_hal_adc.h:504
#define ADC_CLOCK_ASYNC_DIV256
Definition: stm32h7xx_hal_adc.h:509
#define ADC_CLOCK_ASYNC_DIV6
Definition: stm32h7xx_hal_adc.h:501
#define ADC_CLOCK_ASYNC_DIV4
Definition: stm32h7xx_hal_adc.h:500
#define ADC_CLOCK_SYNC_PCLK_DIV2
Definition: stm32h7xx_hal_adc.h:495
#define ADC_CLOCK_ASYNC_DIV8
Definition: stm32h7xx_hal_adc.h:502
#define ADC_CLOCK_SYNC_PCLK_DIV1
Definition: stm32h7xx_hal_adc.h:494
#define ADC_CLOCK_ASYNC_DIV128
Definition: stm32h7xx_hal_adc.h:508
#define ADC_CLOCK_ASYNC_DIV16
Definition: stm32h7xx_hal_adc.h:505
#define ADC_CLOCK_ASYNC_DIV2
Definition: stm32h7xx_hal_adc.h:499
#define ADC_CLOCK_ASYNC_DIV64
Definition: stm32h7xx_hal_adc.h:507
#define ADC_CLOCK_ASYNC_DIV32
Definition: stm32h7xx_hal_adc.h:506

Verify the ADC clock setting.

Parameters
__ADC_CLOCK__programmed ADC clock.
Return values
SET(ADC_CLOCK is a valid value) or RESET (ADC_CLOCK is invalid)

◆ IS_ADC_CONVERSIONDATAMGT

#define IS_ADC_CONVERSIONDATAMGT (   DATA)
Value:
((((DATA) == ADC_CONVERSIONDATA_DR)) || \
(((DATA) == ADC_CONVERSIONDATA_DFSDM)) || \
(((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
#define ADC_CONVERSIONDATA_DMA_CIRCULAR
Definition: stm32h7xx_hal_adc.h:759
#define ADC_CONVERSIONDATA_DFSDM
Definition: stm32h7xx_hal_adc.h:757
#define ADC_CONVERSIONDATA_DMA_ONESHOT
Definition: stm32h7xx_hal_adc.h:758
#define ADC_CONVERSIONDATA_DR
Definition: stm32h7xx_hal_adc.h:756

Verify the ADC data conversion setting.

Parameters
DATA: programmed DATA conversion mode.
Return values
SET(DATA is a valid value) or RESET (DATA is invalid)

◆ IS_ADC_EOC_SELECTION

#define IS_ADC_EOC_SELECTION (   __EOC_SELECTION__)
Value:
(((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )
#define ADC_EOC_SINGLE_CONV
Definition: stm32h7xx_hal_adc.h:629
#define ADC_EOC_SEQ_CONV
Definition: stm32h7xx_hal_adc.h:630

Verify the ADC regular conversions check for converted data availability.

Parameters
__EOC_SELECTION__converted data availability check.
Return values
SET(EOC_SELECTION is a valid value) or RESET (EOC_SELECTION is invalid)

◆ IS_ADC_EXTTRIG

#define IS_ADC_EXTTRIG (   __REGTRIG__)
Value:
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
#define ADC_EXTERNALTRIG_T1_CC3
Definition: stm32h7xx_hal_adc.h:566
#define ADC_EXTERNALTRIG_T8_TRGO
Definition: stm32h7xx_hal_adc.h:571
#define ADC_EXTERNALTRIG_T8_TRGO2
Definition: stm32h7xx_hal_adc.h:572
#define ADC_EXTERNALTRIG_T15_TRGO
Definition: stm32h7xx_hal_adc.h:578
#define ADC_EXTERNALTRIG_HR1_ADCTRG3
Definition: stm32h7xx_hal_adc.h:581
#define ADC_SOFTWARE_START
Definition: stm32h7xx_hal_adc.h:563
#define ADC_EXTERNALTRIG_LPTIM1_OUT
Definition: stm32h7xx_hal_adc.h:582
#define ADC_EXTERNALTRIG_T1_TRGO
Definition: stm32h7xx_hal_adc.h:573
#define ADC_EXTERNALTRIG_T1_CC2
Definition: stm32h7xx_hal_adc.h:565
#define ADC_EXTERNALTRIG_T1_CC1
Definition: stm32h7xx_hal_adc.h:564
#define ADC_EXTERNALTRIG_T3_TRGO
Definition: stm32h7xx_hal_adc.h:568
#define ADC_EXTERNALTRIG_EXT_IT11
Definition: stm32h7xx_hal_adc.h:570
#define ADC_EXTERNALTRIG_T6_TRGO
Definition: stm32h7xx_hal_adc.h:577
#define ADC_EXTERNALTRIG_T1_TRGO2
Definition: stm32h7xx_hal_adc.h:574
#define ADC_EXTERNALTRIG_LPTIM3_OUT
Definition: stm32h7xx_hal_adc.h:584
#define ADC_EXTERNALTRIG_T4_CC4
Definition: stm32h7xx_hal_adc.h:569
#define ADC_EXTERNALTRIG_T2_TRGO
Definition: stm32h7xx_hal_adc.h:575
#define ADC_EXTERNALTRIG_T3_CC4
Definition: stm32h7xx_hal_adc.h:579
#define ADC_EXTERNALTRIG_T2_CC2
Definition: stm32h7xx_hal_adc.h:567
#define ADC_EXTERNALTRIG_T4_TRGO
Definition: stm32h7xx_hal_adc.h:576
#define ADC_EXTERNALTRIG_HR1_ADCTRG1
Definition: stm32h7xx_hal_adc.h:580
#define ADC_EXTERNALTRIG_LPTIM2_OUT
Definition: stm32h7xx_hal_adc.h:583

Verify the ADC regular conversions external trigger.

Parameters
__REGTRIG__programmed ADC regular conversions external trigger.
Return values
SET(REGTRIG is a valid value) or RESET (REGTRIG is invalid)

◆ IS_ADC_EXTTRIG_EDGE

#define IS_ADC_EXTTRIG_EDGE (   __EDGE__)
Value:
(((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
#define ADC_EXTERNALTRIGCONVEDGE_RISING
Definition: stm32h7xx_hal_adc.h:600
#define ADC_EXTERNALTRIGCONVEDGE_FALLING
Definition: stm32h7xx_hal_adc.h:601
#define ADC_EXTERNALTRIGCONVEDGE_NONE
Definition: stm32h7xx_hal_adc.h:599
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
Definition: stm32h7xx_hal_adc.h:602

Verify the ADC edge trigger setting for regular group.

Parameters
__EDGE__programmed ADC edge trigger setting.
Return values
SET(EDGE is a valid value) or RESET (EDGE is invalid)

◆ IS_ADC_OVERRUN

#define IS_ADC_OVERRUN (   __OVR__)
Value:
(((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
#define ADC_OVR_DATA_PRESERVED
Definition: stm32h7xx_hal_adc.h:639
#define ADC_OVR_DATA_OVERWRITTEN
Definition: stm32h7xx_hal_adc.h:640

Verify the ADC regular conversions overrun handling.

Parameters
__OVR__ADC regular conversions overrun handling.
Return values
SET(OVR is a valid value) or RESET (OVR is invalid)

◆ IS_ADC_RANGE

#define IS_ADC_RANGE (   __RESOLUTION__,
  __ADC_VALUE__ 
)     ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))

Verify that a given value is aligned with the ADC resolution range.

Parameters
__RESOLUTION__ADC resolution (16, 14, 12, 10 or 8 bits).
__ADC_VALUE__value checked against the resolution.
Return values
SET(ADC_VALUE in line with RESOLUTION) or RESET (ADC_VALUE not in line with RESOLUTION)

◆ IS_ADC_REGULAR_DISCONT_NUMBER

#define IS_ADC_REGULAR_DISCONT_NUMBER (   NUMBER)    (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))

Verify the number of scheduled regular conversions in discontinuous mode.

Parameters
NUMBERnumber of scheduled regular conversions in discontinuous mode.
Return values
SET(NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)

◆ IS_ADC_REGULAR_NB_CONV

#define IS_ADC_REGULAR_NB_CONV (   __LENGTH__)    (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))

Verify the length of the scheduled regular conversions group.

Parameters
__LENGTH__number of programmed conversions.
Return values
SET(LENGTH is within the maximum number of possible programmable regular conversions) or RESET (LENGTH is null or too large)

◆ IS_ADC_REGULAR_RANK

#define IS_ADC_REGULAR_RANK (   __CHANNEL__)
Value:
(((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
((__CHANNEL__) == ADC_REGULAR_RANK_16) )
#define ADC_REGULAR_RANK_12
Definition: stm32h7xx_hal_adc.h:660
#define ADC_REGULAR_RANK_2
Definition: stm32h7xx_hal_adc.h:650
#define ADC_REGULAR_RANK_5
Definition: stm32h7xx_hal_adc.h:653
#define ADC_REGULAR_RANK_9
Definition: stm32h7xx_hal_adc.h:657
#define ADC_REGULAR_RANK_15
Definition: stm32h7xx_hal_adc.h:663
#define ADC_REGULAR_RANK_7
Definition: stm32h7xx_hal_adc.h:655
#define ADC_REGULAR_RANK_6
Definition: stm32h7xx_hal_adc.h:654
#define ADC_REGULAR_RANK_16
Definition: stm32h7xx_hal_adc.h:664
#define ADC_REGULAR_RANK_14
Definition: stm32h7xx_hal_adc.h:662
#define ADC_REGULAR_RANK_8
Definition: stm32h7xx_hal_adc.h:656
#define ADC_REGULAR_RANK_10
Definition: stm32h7xx_hal_adc.h:658
#define ADC_REGULAR_RANK_11
Definition: stm32h7xx_hal_adc.h:659
#define ADC_REGULAR_RANK_3
Definition: stm32h7xx_hal_adc.h:651
#define ADC_REGULAR_RANK_1
Definition: stm32h7xx_hal_adc.h:649
#define ADC_REGULAR_RANK_4
Definition: stm32h7xx_hal_adc.h:652
#define ADC_REGULAR_RANK_13
Definition: stm32h7xx_hal_adc.h:661

Verify the ADC regular channel setting.

Parameters
__CHANNEL__programmed ADC regular channel.
Return values
SET(CHANNEL is valid) or RESET (CHANNEL is invalid)

◆ IS_ADC_RESOLUTION

#define IS_ADC_RESOLUTION (   __RESOLUTION__)
Value:
(((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
((__RESOLUTION__) == ADC_RESOLUTION_8B) )
#define ADC_RESOLUTION_14B
Definition: stm32h7xx_hal_adc.h:519
#define ADC_RESOLUTION_8B
Definition: stm32h7xx_hal_adc.h:522
#define ADC_RESOLUTION_12B
Definition: stm32h7xx_hal_adc.h:520
#define ADC_RESOLUTION_16B
Definition: stm32h7xx_hal_adc.h:518
#define ADC_RESOLUTION_10B
Definition: stm32h7xx_hal_adc.h:521

Verify the ADC resolution setting.

Parameters
__RESOLUTION__programmed ADC resolution.
Return values
SET(RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)

◆ IS_ADC_RESOLUTION_8_BITS

#define IS_ADC_RESOLUTION_8_BITS (   __RESOLUTION__)    (((__RESOLUTION__) == ADC_RESOLUTION_8B))

Verify the ADC resolution setting when limited to 8 bits.

Parameters
__RESOLUTION__programmed ADC resolution when limited to 8 bits.
Return values
SET(RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)

◆ IS_ADC_SAMPLE_TIME

#define IS_ADC_SAMPLE_TIME (   __TIME__)
Value:
(((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \
((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_8CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_16CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_32CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_64CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_810CYCLES_5) )
#define ADC_SAMPLETIME_1CYCLE_5
Definition: stm32h7xx_hal_adc.h:673
#define ADC_SAMPLETIME_64CYCLES_5
Definition: stm32h7xx_hal_adc.h:678
#define ADC_SAMPLETIME_8CYCLES_5
Definition: stm32h7xx_hal_adc.h:675
#define ADC_SAMPLETIME_810CYCLES_5
Definition: stm32h7xx_hal_adc.h:680
#define ADC_SAMPLETIME_16CYCLES_5
Definition: stm32h7xx_hal_adc.h:676
#define ADC_SAMPLETIME_32CYCLES_5
Definition: stm32h7xx_hal_adc.h:677
#define ADC_SAMPLETIME_2CYCLES_5
Definition: stm32h7xx_hal_adc.h:674
#define ADC_SAMPLETIME_387CYCLES_5
Definition: stm32h7xx_hal_adc.h:679

Verify the ADC conversions sampling time.

Parameters
__TIME__ADC conversions sampling time.
Return values
SET(TIME is a valid value) or RESET (TIME is invalid)

◆ IS_ADC_SCAN_MODE

#define IS_ADC_SCAN_MODE (   __SCAN_MODE__)
Value:
(((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
((__SCAN_MODE__) == ADC_SCAN_ENABLE) )
#define ADC_SCAN_ENABLE
Definition: stm32h7xx_hal_adc.h:553
#define ADC_SCAN_DISABLE
Definition: stm32h7xx_hal_adc.h:552

Verify the ADC scan mode.

Parameters
__SCAN_MODE__programmed ADC scan mode.
Return values
SET(SCAN_MODE is valid) or RESET (SCAN_MODE is invalid)