fsl_pdm.h

/*
 * Copyright (c) 2018, Freescale Semiconductor, Inc.
 * Copyright 2019-2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _FSL_PDM_H_
#define _FSL_PDM_H_
 
#include "fsl_common.h"
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_PDM_DRIVER_VERSION (MAKE_VERSION(2, 8, 0)) 
 
#define PDM_XFER_QUEUE_SIZE (4U)
 
enum
{
    kStatus_PDM_Busy = MAKE_STATUS(kStatusGroup_PDM, 0), 
#if (defined(FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ) && (FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ == 1U))
    kStatus_PDM_CLK_LOW = MAKE_STATUS(kStatusGroup_PDM, 1), 
#endif
    kStatus_PDM_FIFO_ERROR           = MAKE_STATUS(kStatusGroup_PDM, 2), 
    kStatus_PDM_QueueFull            = MAKE_STATUS(kStatusGroup_PDM, 3), 
    kStatus_PDM_Idle                 = MAKE_STATUS(kStatusGroup_PDM, 4), 
    kStatus_PDM_Output_ERROR         = MAKE_STATUS(kStatusGroup_PDM, 5), 
    kStatus_PDM_ChannelConfig_Failed = MAKE_STATUS(kStatusGroup_PDM, 6), 
#if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD)
    kStatus_PDM_HWVAD_VoiceDetected = MAKE_STATUS(kStatusGroup_PDM, 7), 
    kStatus_PDM_HWVAD_Error         = MAKE_STATUS(kStatusGroup_PDM, 8), 
#endif
};
 
enum _pdm_interrupt_enable
{
    kPDM_ErrorInterruptEnable = PDM_CTRL_1_ERREN_MASK, 
    kPDM_FIFOInterruptEnable  = PDM_CTRL_1_DISEL(2U),  
};
 
enum _pdm_internal_status
{
    kPDM_StatusDfBusyFlag = (int)PDM_STAT_BSY_FIL_MASK, 
#if !(defined(FSL_FEATURE_PDM_HAS_NO_FIR_RDY) && FSL_FEATURE_PDM_HAS_NO_FIR_RDY)
    kPDM_StatusFIRFilterReady = PDM_STAT_FIR_RDY_MASK, 
#endif
#if (defined(FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ) && (FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ == 1U))
    kPDM_StatusFrequencyLow = PDM_STAT_LOWFREQF_MASK, 
#endif
    kPDM_StatusCh0FifoDataAvaliable = PDM_STAT_CH0F_MASK, 
    kPDM_StatusCh1FifoDataAvaliable = PDM_STAT_CH1F_MASK, 
    kPDM_StatusCh2FifoDataAvaliable = PDM_STAT_CH2F_MASK, 
    kPDM_StatusCh3FifoDataAvaliable = PDM_STAT_CH3F_MASK, 
#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U)
    kPDM_StatusCh4FifoDataAvaliable = PDM_STAT_CH4F_MASK, 
    kPDM_StatusCh5FifoDataAvaliable = PDM_STAT_CH5F_MASK, 
    kPDM_StatusCh6FifoDataAvaliable = PDM_STAT_CH6F_MASK, 
    kPDM_StatusCh7FifoDataAvaliable = PDM_STAT_CH7F_MASK, 
#endif
};
 
enum _pdm_channel_enable_mask
{
    kPDM_EnableChannel0 = PDM_STAT_CH0F_MASK, 
    kPDM_EnableChannel1 = PDM_STAT_CH1F_MASK, 
    kPDM_EnableChannel2 = PDM_STAT_CH2F_MASK, 
    kPDM_EnableChannel3 = PDM_STAT_CH3F_MASK, 
#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U)
    kPDM_EnableChannel4 = PDM_STAT_CH4F_MASK, 
    kPDM_EnableChannel5 = PDM_STAT_CH5F_MASK, 
    kPDM_EnableChannel6 = PDM_STAT_CH6F_MASK, 
    kPDM_EnableChannel7 = PDM_STAT_CH7F_MASK, 
    kPDM_EnableChannelAll = kPDM_EnableChannel0 | kPDM_EnableChannel1 | kPDM_EnableChannel2 | kPDM_EnableChannel3 |
                            kPDM_EnableChannel4 | kPDM_EnableChannel5 | kPDM_EnableChannel6 | kPDM_EnableChannel7,
#else
    kPDM_EnableChannelAll = kPDM_EnableChannel0 | kPDM_EnableChannel1 | kPDM_EnableChannel2 | kPDM_EnableChannel3,
#endif
};
 
enum _pdm_fifo_status
{
    kPDM_FifoStatusUnderflowCh0 = PDM_FIFO_STAT_FIFOUND0_MASK, 
    kPDM_FifoStatusUnderflowCh1 = PDM_FIFO_STAT_FIFOUND1_MASK, 
    kPDM_FifoStatusUnderflowCh2 = PDM_FIFO_STAT_FIFOUND2_MASK, 
    kPDM_FifoStatusUnderflowCh3 = PDM_FIFO_STAT_FIFOUND3_MASK, 
#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U)
    kPDM_FifoStatusUnderflowCh4 = PDM_FIFO_STAT_FIFOUND4_MASK, 
    kPDM_FifoStatusUnderflowCh5 = PDM_FIFO_STAT_FIFOUND5_MASK, 
    kPDM_FifoStatusUnderflowCh6 = PDM_FIFO_STAT_FIFOUND6_MASK, 
    kPDM_FifoStatusUnderflowCh7 = PDM_FIFO_STAT_FIFOUND6_MASK, 
#endif
 
    kPDM_FifoStatusOverflowCh0 = PDM_FIFO_STAT_FIFOOVF0_MASK, 
    kPDM_FifoStatusOverflowCh1 = PDM_FIFO_STAT_FIFOOVF1_MASK, 
    kPDM_FifoStatusOverflowCh2 = PDM_FIFO_STAT_FIFOOVF2_MASK, 
    kPDM_FifoStatusOverflowCh3 = PDM_FIFO_STAT_FIFOOVF3_MASK, 
#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U)
    kPDM_FifoStatusOverflowCh4 = PDM_FIFO_STAT_FIFOOVF4_MASK, 
    kPDM_FifoStatusOverflowCh5 = PDM_FIFO_STAT_FIFOOVF5_MASK, 
    kPDM_FifoStatusOverflowCh6 = PDM_FIFO_STAT_FIFOOVF6_MASK, 
    kPDM_FifoStatusOverflowCh7 = PDM_FIFO_STAT_FIFOOVF7_MASK, 
#endif
};
 
#if defined(FSL_FEATURE_PDM_HAS_RANGE_CTRL) && FSL_FEATURE_PDM_HAS_RANGE_CTRL
enum _pdm_range_status
{
    kPDM_RangeStatusUnderFlowCh0 = PDM_RANGE_STAT_RANGEUNF0_MASK, 
    kPDM_RangeStatusUnderFlowCh1 = PDM_RANGE_STAT_RANGEUNF1_MASK, 
    kPDM_RangeStatusUnderFlowCh2 = PDM_RANGE_STAT_RANGEUNF2_MASK, 
    kPDM_RangeStatusUnderFlowCh3 = PDM_RANGE_STAT_RANGEUNF3_MASK, 
#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U)
    kPDM_RangeStatusUnderFlowCh4 = PDM_RANGE_STAT_RANGEUNF4_MASK, 
    kPDM_RangeStatusUnderFlowCh5 = PDM_RANGE_STAT_RANGEUNF5_MASK, 
    kPDM_RangeStatusUnderFlowCh6 = PDM_RANGE_STAT_RANGEUNF6_MASK, 
    kPDM_RangeStatusUnderFlowCh7 = PDM_RANGE_STAT_RANGEUNF7_MASK, 
#endif
    kPDM_RangeStatusOverFlowCh0 = PDM_RANGE_STAT_RANGEOVF0_MASK, 
    kPDM_RangeStatusOverFlowCh1 = PDM_RANGE_STAT_RANGEOVF1_MASK, 
    kPDM_RangeStatusOverFlowCh2 = PDM_RANGE_STAT_RANGEOVF2_MASK, 
    kPDM_RangeStatusOverFlowCh3 = PDM_RANGE_STAT_RANGEOVF3_MASK, 
#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U)
    kPDM_RangeStatusOverFlowCh4 = PDM_RANGE_STAT_RANGEOVF4_MASK, 
    kPDM_RangeStatusOverFlowCh5 = PDM_RANGE_STAT_RANGEOVF5_MASK, 
    kPDM_RangeStatusOverFlowCh6 = PDM_RANGE_STAT_RANGEOVF6_MASK, 
    kPDM_RangeStatusOverFlowCh7 = PDM_RANGE_STAT_RANGEOVF7_MASK, 
#endif
};
#else
enum _pdm_output_status
{
    kPDM_OutputStatusUnderFlowCh0 = PDM_OUT_STAT_OUTUNF0_MASK, 
    kPDM_OutputStatusUnderFlowCh1 = PDM_OUT_STAT_OUTUNF1_MASK, 
    kPDM_OutputStatusUnderFlowCh2 = PDM_OUT_STAT_OUTUNF2_MASK, 
    kPDM_OutputStatusUnderFlowCh3 = PDM_OUT_STAT_OUTUNF3_MASK, 
#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U)
    kPDM_OutputStatusUnderFlowCh4 = PDM_OUT_STAT_OUTUNF4_MASK, 
    kPDM_OutputStatusUnderFlowCh5 = PDM_OUT_STAT_OUTUNF5_MASK, 
    kPDM_OutputStatusUnderFlowCh6 = PDM_OUT_STAT_OUTUNF6_MASK, 
    kPDM_OutputStatusUnderFlowCh7 = PDM_OUT_STAT_OUTUNF7_MASK, 
#endif
    kPDM_OutputStatusOverFlowCh0 = PDM_OUT_STAT_OUTOVF0_MASK,  
    kPDM_OutputStatusOverFlowCh1 = PDM_OUT_STAT_OUTOVF1_MASK,  
    kPDM_OutputStatusOverFlowCh2 = PDM_OUT_STAT_OUTOVF2_MASK,  
    kPDM_OutputStatusOverFlowCh3 = PDM_OUT_STAT_OUTOVF3_MASK,  
#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U)
    kPDM_OutputStatusOverFlowCh4 = PDM_OUT_STAT_OUTOVF4_MASK,  
    kPDM_OutputStatusOverFlowCh5 = PDM_OUT_STAT_OUTOVF5_MASK,  
    kPDM_OutputStatusOverFlowCh6 = PDM_OUT_STAT_OUTOVF6_MASK,  
    kPDM_OutputStatusOverFlowCh7 = PDM_OUT_STAT_OUTOVF7_MASK,  
#endif
};
#endif
 
#if (defined(FSL_FEATURE_PDM_HAS_DC_OUT_CTRL) && (FSL_FEATURE_PDM_HAS_DC_OUT_CTRL))
typedef enum _pdm_dc_remover
{
    kPDM_DcRemoverCutOff20Hz = 0U, 
    kPDM_DcRemoverCutOff13Hz = 1U, 
    kPDM_DcRemoverCutOff40Hz = 2U, 
    kPDM_DcRemoverBypass     = 3U, 
} pdm_dc_remover_t;
#else
typedef enum _pdm_dc_remover
{
    kPDM_DcRemoverCutOff21Hz = 0U,  
    kPDM_DcRemoverCutOff83Hz = 1U,  
    kPDM_DcRemoverCutOff152Hz = 2U, 
    kPDM_DcRemoverBypass = 3U,      
} pdm_dc_remover_t;
#endif
 
typedef enum _pdm_df_quality_mode
{
    kPDM_QualityModeMedium   = 0U, 
    kPDM_QualityModeHigh     = 1U, 
    kPDM_QualityModeLow      = 7U, 
    kPDM_QualityModeVeryLow0 = 6U, 
    kPDM_QualityModeVeryLow1 = 5U, 
    kPDM_QualityModeVeryLow2 = 4U, 
} pdm_df_quality_mode_t;
 
enum _pdm_qulaity_mode_k_factor
{
    kPDM_QualityModeHighKFactor     = 1U, 
    kPDM_QualityModeMediumKFactor   = 2U, 
    kPDM_QualityModeLowKFactor      = 4U, 
    kPDM_QualityModeVeryLow2KFactor = 8U, 
};
 
typedef enum _pdm_df_output_gain
{
    kPDM_DfOutputGain0  = 0U,   
    kPDM_DfOutputGain1  = 1U,   
    kPDM_DfOutputGain2  = 2U,   
    kPDM_DfOutputGain3  = 3U,   
    kPDM_DfOutputGain4  = 4U,   
    kPDM_DfOutputGain5  = 5U,   
    kPDM_DfOutputGain6  = 6U,   
    kPDM_DfOutputGain7  = 7U,   
    kPDM_DfOutputGain8  = 8U,   
    kPDM_DfOutputGain9  = 9U,   
    kPDM_DfOutputGain10 = 0xAU, 
    kPDM_DfOutputGain11 = 0xBU, 
    kPDM_DfOutputGain12 = 0xCU, 
    kPDM_DfOutputGain13 = 0xDU, 
    kPDM_DfOutputGain14 = 0xEU, 
    kPDM_DfOutputGain15 = 0xFU, 
} pdm_df_output_gain_t;
 
enum _pdm_data_width
{
#if defined(FSL_FEATURE_PDM_FIFO_WIDTH) && (FSL_FEATURE_PDM_FIFO_WIDTH != 2U)
    kPDM_DataWwidth24 = 3U, 
    kPDM_DataWwidth32 = 4U, 
#else
    kPDM_DataWdith16 = 2U, 
#endif
};
 
typedef struct _pdm_channel_config
{
#if (defined(FSL_FEATURE_PDM_HAS_DC_OUT_CTRL) && (FSL_FEATURE_PDM_HAS_DC_OUT_CTRL))
    pdm_dc_remover_t outputCutOffFreq; 
#endif
 
#if !(defined(FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED) && (FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED))
    pdm_dc_remover_t cutOffFreq; 
#endif
 
    pdm_df_output_gain_t gain; 
} pdm_channel_config_t;
 
typedef struct _pdm_config
{
    bool
        enableDoze; 
    uint8_t fifoWatermark;             
    pdm_df_quality_mode_t qualityMode; 
    uint8_t cicOverSampleRate;         
} pdm_config_t;
 
#if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD)
enum _pdm_hwvad_interrupt_enable
{
    kPDM_HwvadErrorInterruptEnable = PDM_VAD0_CTRL_1_VADERIE_MASK, 
    kPDM_HwvadInterruptEnable      = PDM_VAD0_CTRL_1_VADIE_MASK,   
};
 
enum _pdm_hwvad_int_status
{
    kPDM_HwvadStatusInputSaturation = PDM_VAD0_STAT_VADINSATF_MASK, 
    kPDM_HwvadStatusVoiceDetectFlag = PDM_VAD0_STAT_VADIF_MASK,     
};
 
typedef enum _pdm_hwvad_hpf_config
{
    kPDM_HwvadHpfBypassed         = 0x0U, 
    kPDM_HwvadHpfCutOffFreq1750Hz = 0x1U, 
    kPDM_HwvadHpfCutOffFreq215Hz  = 0x2U, 
    kPDM_HwvadHpfCutOffFreq102Hz  = 0x3U, 
} pdm_hwvad_hpf_config_t;
 
typedef enum _pdm_hwvad_filter_status
{
    kPDM_HwvadInternalFilterNormalOperation = 0U, 
    kPDM_HwvadInternalFilterInitial         = PDM_VAD0_CTRL_1_VADST10_MASK, 
} pdm_hwvad_filter_status_t;
 
typedef struct _pdm_hwvad_config
{
    uint8_t channel;           
    uint8_t initializeTime;    
    uint8_t cicOverSampleRate; 
    uint8_t inputGain;                 
    uint32_t frameTime;                
    pdm_hwvad_hpf_config_t cutOffFreq; 
    bool enableFrameEnergy;            
    bool enablePreFilter;              
} pdm_hwvad_config_t;
 
typedef struct _pdm_hwvad_noise_filter
{
    bool enableAutoNoiseFilter;     
    bool enableNoiseMin;            
    bool enableNoiseDecimation;     
    bool enableNoiseDetectOR;       
    uint32_t noiseFilterAdjustment; 
    uint32_t noiseGain;             
} pdm_hwvad_noise_filter_t;
 
typedef enum _pdm_hwvad_zcd_result
{
    kPDM_HwvadResultOREnergyBasedDetection =
        0U, 
    kPDM_HwvadResultANDEnergyBasedDetection =
        1U, 
} pdm_hwvad_zcd_result_t;
 
typedef struct _pdm_hwvad_zero_cross_detector
{
    bool enableAutoThreshold;      
    pdm_hwvad_zcd_result_t zcdAnd; 
    uint32_t threshold;            
    uint32_t adjustmentThreshold;  
} pdm_hwvad_zero_cross_detector_t;
#endif
 
typedef struct _pdm_transfer
{
    volatile uint8_t *data;   
    volatile size_t dataSize; 
} pdm_transfer_t;
 
typedef struct _pdm_handle pdm_handle_t;
 
typedef void (*pdm_transfer_callback_t)(PDM_Type *base, pdm_handle_t *handle, status_t status, void *userData);
 
#if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD)
typedef void (*pdm_hwvad_callback_t)(status_t status, void *userData);
typedef struct _pdm_hwvad_notification
{
    pdm_hwvad_callback_t callback;
    void *userData;
} pdm_hwvad_notification_t;
#endif
 
struct _pdm_handle
{
    uint32_t state;                   
    pdm_transfer_callback_t callback; 
    void *userData;                   
    pdm_transfer_t pdmQueue[PDM_XFER_QUEUE_SIZE]; 
    size_t transferSize[PDM_XFER_QUEUE_SIZE];     
    volatile uint8_t queueUser;                   
    volatile uint8_t queueDriver;                 
    uint32_t format;      
    uint8_t watermark;    
    uint8_t startChannel; 
    uint8_t channelNums;  
};
 
/*******************************************************************************
 * API
 ******************************************************************************/
 
#if defined(__cplusplus)
extern "C" {
#endif /*_cplusplus*/
 
void PDM_Init(PDM_Type *base, const pdm_config_t *config);
 
void PDM_Deinit(PDM_Type *base);
 
static inline void PDM_Reset(PDM_Type *base)
{
    base->CTRL_1 |= PDM_CTRL_1_SRES_MASK;
}
 
static inline void PDM_Enable(PDM_Type *base, bool enable)
{
    if (enable)
    {
        base->CTRL_1 |= PDM_CTRL_1_PDMIEN_MASK;
    }
    else
    {
        base->CTRL_1 &= ~PDM_CTRL_1_PDMIEN_MASK;
    }
}
 
static inline void PDM_EnableDoze(PDM_Type *base, bool enable)
{
    if (enable)
    {
        base->CTRL_1 |= PDM_CTRL_1_DOZEN_MASK;
    }
    else
    {
        base->CTRL_1 &= ~PDM_CTRL_1_DOZEN_MASK;
    }
}
 
static inline void PDM_EnableDebugMode(PDM_Type *base, bool enable)
{
    if (enable)
    {
        base->CTRL_1 |= PDM_CTRL_1_DBG_MASK;
    }
    else
    {
        base->CTRL_1 &= ~PDM_CTRL_1_DBG_MASK;
    }
}
 
static inline void PDM_EnableInDebugMode(PDM_Type *base, bool enable)
{
    if (enable)
    {
        base->CTRL_1 |= PDM_CTRL_1_DBGE_MASK;
    }
    else
    {
        base->CTRL_1 &= ~PDM_CTRL_1_DBGE_MASK;
    }
}
 
static inline void PDM_EnterLowLeakageMode(PDM_Type *base, bool enable)
{
    if (enable)
    {
        base->CTRL_1 |= PDM_CTRL_1_MDIS_MASK;
    }
    else
    {
        base->CTRL_1 &= ~PDM_CTRL_1_MDIS_MASK;
    }
}
 
static inline void PDM_EnableChannel(PDM_Type *base, uint8_t channel, bool enable)
{
    if (enable)
    {
        base->CTRL_1 |= (1UL << channel);
    }
    else
    {
        base->CTRL_1 &= ~(1UL << channel);
    }
}
 
void PDM_SetChannelConfig(PDM_Type *base, uint32_t channel, const pdm_channel_config_t *config);
 
status_t PDM_SetSampleRateConfig(PDM_Type *base, uint32_t sourceClock_HZ, uint32_t sampleRate_HZ);
 
status_t PDM_SetSampleRate(
    PDM_Type *base, uint32_t enableChannelMask, pdm_df_quality_mode_t qualityMode, uint8_t osr, uint32_t clkDiv);
 
uint32_t PDM_GetInstance(PDM_Type *base);
static inline uint32_t PDM_GetStatus(PDM_Type *base)
{
    return base->STAT;
}
 
static inline uint32_t PDM_GetFifoStatus(PDM_Type *base)
{
    return base->FIFO_STAT;
}
 
#if defined(FSL_FEATURE_PDM_HAS_RANGE_CTRL) && FSL_FEATURE_PDM_HAS_RANGE_CTRL
static inline uint32_t PDM_GetRangeStatus(PDM_Type *base)
{
    return base->RANGE_STAT;
}
#else
static inline uint32_t PDM_GetOutputStatus(PDM_Type *base)
{
    return base->OUT_STAT;
}
#endif
 
static inline void PDM_ClearStatus(PDM_Type *base, uint32_t mask)
{
    base->STAT = mask;
}
 
static inline void PDM_ClearFIFOStatus(PDM_Type *base, uint32_t mask)
{
    base->FIFO_STAT = mask;
}
 
#if defined(FSL_FEATURE_PDM_HAS_RANGE_CTRL) && FSL_FEATURE_PDM_HAS_RANGE_CTRL
static inline void PDM_ClearRangeStatus(PDM_Type *base, uint32_t mask)
{
    base->RANGE_STAT = mask;
}
#else
static inline void PDM_ClearOutputStatus(PDM_Type *base, uint32_t mask)
{
    base->OUT_STAT = mask;
}
#endif
 
void PDM_EnableInterrupts(PDM_Type *base, uint32_t mask);
 
static inline void PDM_DisableInterrupts(PDM_Type *base, uint32_t mask)
{
    base->CTRL_1 &= ~mask;
}
 
static inline void PDM_EnableDMA(PDM_Type *base, bool enable)
{
    if (enable)
    {
        base->CTRL_1 = (base->CTRL_1 & (~PDM_CTRL_1_DISEL_MASK)) | PDM_CTRL_1_DISEL(0x1U);
    }
    else
    {
        base->CTRL_1 &= ~PDM_CTRL_1_DISEL_MASK;
    }
}
 
static inline uint32_t PDM_GetDataRegisterAddress(PDM_Type *base, uint32_t channel)
{
    return (uint32_t)(&(base->DATACH)[channel]);
}
 
#if defined(FSL_FEATURE_PDM_FIFO_WIDTH) && (FSL_FEATURE_PDM_FIFO_WIDTH == 2U)
static inline int16_t PDM_ReadData(PDM_Type *base, uint32_t channel)
{
    return (int16_t)(base->DATACH[channel]);
}
 
void PDM_ReadNonBlocking(PDM_Type *base, uint32_t startChannel, uint32_t channelNums, int16_t *buffer, size_t size);
#endif
 
void PDM_ReadFifo(
    PDM_Type *base, uint32_t startChannel, uint32_t channelNums, void *buffer, size_t size, uint32_t dataWidth);
 
#if defined(FSL_FEATURE_PDM_FIFO_WIDTH) && (FSL_FEATURE_PDM_FIFO_WIDTH == 4U)
static inline uint32_t PDM_ReadData(PDM_Type *base, uint32_t channel)
{
    return base->DATACH[channel];
}
#endif
 
void PDM_SetChannelGain(PDM_Type *base, uint32_t channel, pdm_df_output_gain_t gain);
 
#if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD)
void PDM_SetHwvadConfig(PDM_Type *base, const pdm_hwvad_config_t *config);
 
static inline void PDM_ForceHwvadOutputDisable(PDM_Type *base, bool enable)
{
    if (enable)
    {
        base->VAD0_CTRL_2 &= ~PDM_VAD0_CTRL_2_VADFOUTDIS_MASK;
    }
    else
    {
        base->VAD0_CTRL_2 |= PDM_VAD0_CTRL_2_VADFOUTDIS_MASK;
    }
}
 
static inline void PDM_ResetHwvad(PDM_Type *base)
{
    base->VAD0_CTRL_1 |= PDM_VAD0_CTRL_1_VADRST_MASK;
}
static inline void PDM_EnableHwvad(PDM_Type *base, bool enable)
{
    if (enable)
    {
        base->VAD0_CTRL_1 |= PDM_VAD0_CTRL_1_VADEN_MASK;
    }
    else
    {
        base->VAD0_CTRL_1 &= ~PDM_VAD0_CTRL_1_VADEN_MASK;
    }
}
 
static inline void PDM_EnableHwvadInterrupts(PDM_Type *base, uint32_t mask)
{
    base->VAD0_CTRL_1 |= mask;
}
 
static inline void PDM_DisableHwvadInterrupts(PDM_Type *base, uint32_t mask)
{
    base->VAD0_CTRL_1 &= ~mask;
}
 
static inline void PDM_ClearHwvadInterruptStatusFlags(PDM_Type *base, uint32_t mask)
{
    base->VAD0_STAT = mask;
}
 
static inline uint32_t PDM_GetHwvadInterruptStatusFlags(PDM_Type *base)
{
    return base->VAD0_STAT & (PDM_VAD0_STAT_VADIF_MASK | PDM_VAD0_STAT_VADINSATF_MASK);
}
 
static inline uint32_t PDM_GetHwvadInitialFlag(PDM_Type *base)
{
    return base->VAD0_STAT & PDM_VAD0_STAT_VADINITF_MASK;
}
 
#if !(defined(FSL_FEATURE_PDM_HAS_NO_VADEF) && (FSL_FEATURE_PDM_HAS_NO_VADEF))
static inline uint32_t PDM_GetHwvadVoiceDetectedFlag(PDM_Type *base)
{
    return base->VAD0_STAT & PDM_VAD0_STAT_VADEF_MASK;
}
#endif
 
static inline void PDM_EnableHwvadSignalFilter(PDM_Type *base, bool enable)
{
    if (enable)
    {
        base->VAD0_SCONFIG |= PDM_VAD0_SCONFIG_VADSFILEN_MASK;
    }
    else
    {
        base->VAD0_SCONFIG &= ~PDM_VAD0_SCONFIG_VADSFILEN_MASK;
    }
}
 
void PDM_SetHwvadSignalFilterConfig(PDM_Type *base, bool enableMaxBlock, uint32_t signalGain);
 
void PDM_SetHwvadNoiseFilterConfig(PDM_Type *base, const pdm_hwvad_noise_filter_t *config);
 
static inline void PDM_EnableHwvadZeroCrossDetector(PDM_Type *base, bool enable)
{
    if (enable)
    {
        base->VAD0_ZCD |= PDM_VAD0_ZCD_VADZCDEN_MASK;
    }
    else
    {
        base->VAD0_ZCD &= ~PDM_VAD0_ZCD_VADZCDEN_MASK;
    }
}
 
void PDM_SetHwvadZeroCrossDetectorConfig(PDM_Type *base, const pdm_hwvad_zero_cross_detector_t *config);
 
static inline uint16_t PDM_GetNoiseData(PDM_Type *base)
{
    return (uint16_t)base->VAD0_NDATA;
}
 
static inline void PDM_SetHwvadInternalFilterStatus(PDM_Type *base, pdm_hwvad_filter_status_t status)
{
    base->VAD0_CTRL_1 = (base->VAD0_CTRL_1 & (~PDM_VAD0_CTRL_1_VADST10_MASK)) | (uint32_t)status;
}
 
void PDM_SetHwvadInEnvelopeBasedMode(PDM_Type *base,
                                     const pdm_hwvad_config_t *hwvadConfig,
                                     const pdm_hwvad_noise_filter_t *noiseConfig,
                                     const pdm_hwvad_zero_cross_detector_t *zcdConfig,
                                     uint32_t signalGain);
 
void PDM_SetHwvadInEnergyBasedMode(PDM_Type *base,
                                   const pdm_hwvad_config_t *hwvadConfig,
                                   const pdm_hwvad_noise_filter_t *noiseConfig,
                                   const pdm_hwvad_zero_cross_detector_t *zcdConfig,
                                   uint32_t signalGain);
 
void PDM_EnableHwvadInterruptCallback(PDM_Type *base, pdm_hwvad_callback_t vadCallback, void *userData, bool enable);
#endif
 
void PDM_TransferCreateHandle(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_callback_t callback, void *userData);
 
status_t PDM_TransferSetChannelConfig(
    PDM_Type *base, pdm_handle_t *handle, uint32_t channel, const pdm_channel_config_t *config, uint32_t format);
 
status_t PDM_TransferReceiveNonBlocking(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_t *xfer);
 
void PDM_TransferAbortReceive(PDM_Type *base, pdm_handle_t *handle);
 
void PDM_TransferHandleIRQ(PDM_Type *base, pdm_handle_t *handle);
 
#if defined(__cplusplus)
}
#endif /*_cplusplus*/
 
#endif /* _FSL_PDM_H_ */