RTEMS 6.1-rc6
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dsu4-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * This file is part of the RTEMS quality process and was automatically
38 * generated. If you find something that needs to be fixed or
39 * worded better please post a report or patch to an RTEMS mailing list
40 * or raise a bug report:
41 *
42 * https://www.rtems.org/bugs.html
43 *
44 * For information on updating and regenerating please refer to the How-To
45 * section in the Software Requirements Engineering chapter of the
46 * RTEMS Software Engineering manual. The manual is provided as a part of
47 * a release. For development sources please refer to the online
48 * documentation at:
49 *
50 * https://docs.rtems.org
51 */
52
53/* Generated from spec:/dev/grlib/if/dsu4-header */
54
55#ifndef _GRLIB_DSU4_REGS_H
56#define _GRLIB_DSU4_REGS_H
57
58#include <stdint.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64/* Generated from spec:/dev/grlib/if/dsu4 */
65
84#define DSU4_CTRL_PW 0x800U
85
86#define DSU4_CTRL_HL 0x400U
87
88#define DSU4_CTRL_PE 0x200U
89
90#define DSU4_CTRL_EB 0x100U
91
92#define DSU4_CTRL_EE 0x80U
93
94#define DSU4_CTRL_DM 0x40U
95
96#define DSU4_CTRL_BZ 0x20U
97
98#define DSU4_CTRL_BX 0x10U
99
100#define DSU4_CTRL_BS 0x8U
101
102#define DSU4_CTRL_BW 0x4U
103
104#define DSU4_CTRL_BE 0x2U
105
106#define DSU4_CTRL_TE 0x1U
107
118#define DSU4_DTTC_TIMETAG_SHIFT 0
119#define DSU4_DTTC_TIMETAG_MASK 0xffffffffU
120#define DSU4_DTTC_TIMETAG_GET( _reg ) \
121 ( ( ( _reg ) & DSU4_DTTC_TIMETAG_MASK ) >> \
122 DSU4_DTTC_TIMETAG_SHIFT )
123#define DSU4_DTTC_TIMETAG_SET( _reg, _val ) \
124 ( ( ( _reg ) & ~DSU4_DTTC_TIMETAG_MASK ) | \
125 ( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & \
126 DSU4_DTTC_TIMETAG_MASK ) )
127#define DSU4_DTTC_TIMETAG( _val ) \
128 ( ( ( _val ) << DSU4_DTTC_TIMETAG_SHIFT ) & \
129 DSU4_DTTC_TIMETAG_MASK )
130
141#define DSU4_BRSS_SS_3_0_SHIFT 16
142#define DSU4_BRSS_SS_3_0_MASK 0xf0000U
143#define DSU4_BRSS_SS_3_0_GET( _reg ) \
144 ( ( ( _reg ) & DSU4_BRSS_SS_3_0_MASK ) >> \
145 DSU4_BRSS_SS_3_0_SHIFT )
146#define DSU4_BRSS_SS_3_0_SET( _reg, _val ) \
147 ( ( ( _reg ) & ~DSU4_BRSS_SS_3_0_MASK ) | \
148 ( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & \
149 DSU4_BRSS_SS_3_0_MASK ) )
150#define DSU4_BRSS_SS_3_0( _val ) \
151 ( ( ( _val ) << DSU4_BRSS_SS_3_0_SHIFT ) & \
152 DSU4_BRSS_SS_3_0_MASK )
153
154#define DSU4_BRSS_BN_3_0_SHIFT 0
155#define DSU4_BRSS_BN_3_0_MASK 0xfU
156#define DSU4_BRSS_BN_3_0_GET( _reg ) \
157 ( ( ( _reg ) & DSU4_BRSS_BN_3_0_MASK ) >> \
158 DSU4_BRSS_BN_3_0_SHIFT )
159#define DSU4_BRSS_BN_3_0_SET( _reg, _val ) \
160 ( ( ( _reg ) & ~DSU4_BRSS_BN_3_0_MASK ) | \
161 ( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & \
162 DSU4_BRSS_BN_3_0_MASK ) )
163#define DSU4_BRSS_BN_3_0( _val ) \
164 ( ( ( _val ) << DSU4_BRSS_BN_3_0_SHIFT ) & \
165 DSU4_BRSS_BN_3_0_MASK )
166
177#define DSU4_DBGM_DM_3_0_SHIFT 16
178#define DSU4_DBGM_DM_3_0_MASK 0xf0000U
179#define DSU4_DBGM_DM_3_0_GET( _reg ) \
180 ( ( ( _reg ) & DSU4_DBGM_DM_3_0_MASK ) >> \
181 DSU4_DBGM_DM_3_0_SHIFT )
182#define DSU4_DBGM_DM_3_0_SET( _reg, _val ) \
183 ( ( ( _reg ) & ~DSU4_DBGM_DM_3_0_MASK ) | \
184 ( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & \
185 DSU4_DBGM_DM_3_0_MASK ) )
186#define DSU4_DBGM_DM_3_0( _val ) \
187 ( ( ( _val ) << DSU4_DBGM_DM_3_0_SHIFT ) & \
188 DSU4_DBGM_DM_3_0_MASK )
189
190#define DSU4_DBGM_ED_3_0_SHIFT 0
191#define DSU4_DBGM_ED_3_0_MASK 0xfU
192#define DSU4_DBGM_ED_3_0_GET( _reg ) \
193 ( ( ( _reg ) & DSU4_DBGM_ED_3_0_MASK ) >> \
194 DSU4_DBGM_ED_3_0_SHIFT )
195#define DSU4_DBGM_ED_3_0_SET( _reg, _val ) \
196 ( ( ( _reg ) & ~DSU4_DBGM_ED_3_0_MASK ) | \
197 ( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & \
198 DSU4_DBGM_ED_3_0_MASK ) )
199#define DSU4_DBGM_ED_3_0( _val ) \
200 ( ( ( _val ) << DSU4_DBGM_ED_3_0_SHIFT ) & \
201 DSU4_DBGM_ED_3_0_MASK )
202
213#define DSU4_DTR_EM 0x1000U
214
215#define DSU4_DTR_TRAPTYPE_SHIFT 4
216#define DSU4_DTR_TRAPTYPE_MASK 0xff0U
217#define DSU4_DTR_TRAPTYPE_GET( _reg ) \
218 ( ( ( _reg ) & DSU4_DTR_TRAPTYPE_MASK ) >> \
219 DSU4_DTR_TRAPTYPE_SHIFT )
220#define DSU4_DTR_TRAPTYPE_SET( _reg, _val ) \
221 ( ( ( _reg ) & ~DSU4_DTR_TRAPTYPE_MASK ) | \
222 ( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & \
223 DSU4_DTR_TRAPTYPE_MASK ) )
224#define DSU4_DTR_TRAPTYPE( _val ) \
225 ( ( ( _val ) << DSU4_DTR_TRAPTYPE_SHIFT ) & \
226 DSU4_DTR_TRAPTYPE_MASK )
227
238#define DSU4_DASI_ASI_SHIFT 0
239#define DSU4_DASI_ASI_MASK 0xffU
240#define DSU4_DASI_ASI_GET( _reg ) \
241 ( ( ( _reg ) & DSU4_DASI_ASI_MASK ) >> \
242 DSU4_DASI_ASI_SHIFT )
243#define DSU4_DASI_ASI_SET( _reg, _val ) \
244 ( ( ( _reg ) & ~DSU4_DASI_ASI_MASK ) | \
245 ( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & \
246 DSU4_DASI_ASI_MASK ) )
247#define DSU4_DASI_ASI( _val ) \
248 ( ( ( _val ) << DSU4_DASI_ASI_SHIFT ) & \
249 DSU4_DASI_ASI_MASK )
250
261#define DSU4_ATBC_DCNT_SHIFT 16
262#define DSU4_ATBC_DCNT_MASK 0xff0000U
263#define DSU4_ATBC_DCNT_GET( _reg ) \
264 ( ( ( _reg ) & DSU4_ATBC_DCNT_MASK ) >> \
265 DSU4_ATBC_DCNT_SHIFT )
266#define DSU4_ATBC_DCNT_SET( _reg, _val ) \
267 ( ( ( _reg ) & ~DSU4_ATBC_DCNT_MASK ) | \
268 ( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & \
269 DSU4_ATBC_DCNT_MASK ) )
270#define DSU4_ATBC_DCNT( _val ) \
271 ( ( ( _val ) << DSU4_ATBC_DCNT_SHIFT ) & \
272 DSU4_ATBC_DCNT_MASK )
273
274#define DSU4_ATBC_DF 0x100U
275
276#define DSU4_ATBC_SF 0x80U
277
278#define DSU4_ATBC_TE 0x40U
279
280#define DSU4_ATBC_TF 0x20U
281
282#define DSU4_ATBC_BW_SHIFT 3
283#define DSU4_ATBC_BW_MASK 0x18U
284#define DSU4_ATBC_BW_GET( _reg ) \
285 ( ( ( _reg ) & DSU4_ATBC_BW_MASK ) >> \
286 DSU4_ATBC_BW_SHIFT )
287#define DSU4_ATBC_BW_SET( _reg, _val ) \
288 ( ( ( _reg ) & ~DSU4_ATBC_BW_MASK ) | \
289 ( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & \
290 DSU4_ATBC_BW_MASK ) )
291#define DSU4_ATBC_BW( _val ) \
292 ( ( ( _val ) << DSU4_ATBC_BW_SHIFT ) & \
293 DSU4_ATBC_BW_MASK )
294
295#define DSU4_ATBC_BR 0x4U
296
297#define DSU4_ATBC_DM 0x2U
298
299#define DSU4_ATBC_EN 0x1U
300
311#define DSU4_ATBI_INDEX_SHIFT 4
312#define DSU4_ATBI_INDEX_MASK 0xff0U
313#define DSU4_ATBI_INDEX_GET( _reg ) \
314 ( ( ( _reg ) & DSU4_ATBI_INDEX_MASK ) >> \
315 DSU4_ATBI_INDEX_SHIFT )
316#define DSU4_ATBI_INDEX_SET( _reg, _val ) \
317 ( ( ( _reg ) & ~DSU4_ATBI_INDEX_MASK ) | \
318 ( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & \
319 DSU4_ATBI_INDEX_MASK ) )
320#define DSU4_ATBI_INDEX( _val ) \
321 ( ( ( _val ) << DSU4_ATBI_INDEX_SHIFT ) & \
322 DSU4_ATBI_INDEX_MASK )
323
335#define DSU4_ATBFC_WPF_SHIFT 12
336#define DSU4_ATBFC_WPF_MASK 0x3000U
337#define DSU4_ATBFC_WPF_GET( _reg ) \
338 ( ( ( _reg ) & DSU4_ATBFC_WPF_MASK ) >> \
339 DSU4_ATBFC_WPF_SHIFT )
340#define DSU4_ATBFC_WPF_SET( _reg, _val ) \
341 ( ( ( _reg ) & ~DSU4_ATBFC_WPF_MASK ) | \
342 ( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & \
343 DSU4_ATBFC_WPF_MASK ) )
344#define DSU4_ATBFC_WPF( _val ) \
345 ( ( ( _val ) << DSU4_ATBFC_WPF_SHIFT ) & \
346 DSU4_ATBFC_WPF_MASK )
347
348#define DSU4_ATBFC_BPF_SHIFT 8
349#define DSU4_ATBFC_BPF_MASK 0x300U
350#define DSU4_ATBFC_BPF_GET( _reg ) \
351 ( ( ( _reg ) & DSU4_ATBFC_BPF_MASK ) >> \
352 DSU4_ATBFC_BPF_SHIFT )
353#define DSU4_ATBFC_BPF_SET( _reg, _val ) \
354 ( ( ( _reg ) & ~DSU4_ATBFC_BPF_MASK ) | \
355 ( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & \
356 DSU4_ATBFC_BPF_MASK ) )
357#define DSU4_ATBFC_BPF( _val ) \
358 ( ( ( _val ) << DSU4_ATBFC_BPF_SHIFT ) & \
359 DSU4_ATBFC_BPF_MASK )
360
361#define DSU4_ATBFC_PF 0x8U
362
363#define DSU4_ATBFC_AF 0x4U
364
365#define DSU4_ATBFC_FR 0x2U
366
367#define DSU4_ATBFC_FW 0x1U
368
380#define DSU4_ATBFM_SMASK_15_0_SHIFT 16
381#define DSU4_ATBFM_SMASK_15_0_MASK 0xffff0000U
382#define DSU4_ATBFM_SMASK_15_0_GET( _reg ) \
383 ( ( ( _reg ) & DSU4_ATBFM_SMASK_15_0_MASK ) >> \
384 DSU4_ATBFM_SMASK_15_0_SHIFT )
385#define DSU4_ATBFM_SMASK_15_0_SET( _reg, _val ) \
386 ( ( ( _reg ) & ~DSU4_ATBFM_SMASK_15_0_MASK ) | \
387 ( ( ( _val ) << DSU4_ATBFM_SMASK_15_0_SHIFT ) & \
388 DSU4_ATBFM_SMASK_15_0_MASK ) )
389#define DSU4_ATBFM_SMASK_15_0( _val ) \
390 ( ( ( _val ) << DSU4_ATBFM_SMASK_15_0_SHIFT ) & \
391 DSU4_ATBFM_SMASK_15_0_MASK )
392
393#define DSU4_ATBFM_MMASK_15_0_SHIFT 0
394#define DSU4_ATBFM_MMASK_15_0_MASK 0xffffU
395#define DSU4_ATBFM_MMASK_15_0_GET( _reg ) \
396 ( ( ( _reg ) & DSU4_ATBFM_MMASK_15_0_MASK ) >> \
397 DSU4_ATBFM_MMASK_15_0_SHIFT )
398#define DSU4_ATBFM_MMASK_15_0_SET( _reg, _val ) \
399 ( ( ( _reg ) & ~DSU4_ATBFM_MMASK_15_0_MASK ) | \
400 ( ( ( _val ) << DSU4_ATBFM_MMASK_15_0_SHIFT ) & \
401 DSU4_ATBFM_MMASK_15_0_MASK ) )
402#define DSU4_ATBFM_MMASK_15_0( _val ) \
403 ( ( ( _val ) << DSU4_ATBFM_MMASK_15_0_SHIFT ) & \
404 DSU4_ATBFM_MMASK_15_0_MASK )
405
417#define DSU4_ATBBA_BADDR_31_2_SHIFT 2
418#define DSU4_ATBBA_BADDR_31_2_MASK 0xfffffffcU
419#define DSU4_ATBBA_BADDR_31_2_GET( _reg ) \
420 ( ( ( _reg ) & DSU4_ATBBA_BADDR_31_2_MASK ) >> \
421 DSU4_ATBBA_BADDR_31_2_SHIFT )
422#define DSU4_ATBBA_BADDR_31_2_SET( _reg, _val ) \
423 ( ( ( _reg ) & ~DSU4_ATBBA_BADDR_31_2_MASK ) | \
424 ( ( ( _val ) << DSU4_ATBBA_BADDR_31_2_SHIFT ) & \
425 DSU4_ATBBA_BADDR_31_2_MASK ) )
426#define DSU4_ATBBA_BADDR_31_2( _val ) \
427 ( ( ( _val ) << DSU4_ATBBA_BADDR_31_2_SHIFT ) & \
428 DSU4_ATBBA_BADDR_31_2_MASK )
429
441#define DSU4_ATBBM_BMASK_31_2_SHIFT 2
442#define DSU4_ATBBM_BMASK_31_2_MASK 0xfffffffcU
443#define DSU4_ATBBM_BMASK_31_2_GET( _reg ) \
444 ( ( ( _reg ) & DSU4_ATBBM_BMASK_31_2_MASK ) >> \
445 DSU4_ATBBM_BMASK_31_2_SHIFT )
446#define DSU4_ATBBM_BMASK_31_2_SET( _reg, _val ) \
447 ( ( ( _reg ) & ~DSU4_ATBBM_BMASK_31_2_MASK ) | \
448 ( ( ( _val ) << DSU4_ATBBM_BMASK_31_2_SHIFT ) & \
449 DSU4_ATBBM_BMASK_31_2_MASK ) )
450#define DSU4_ATBBM_BMASK_31_2( _val ) \
451 ( ( ( _val ) << DSU4_ATBBM_BMASK_31_2_SHIFT ) & \
452 DSU4_ATBBM_BMASK_31_2_MASK )
453
454#define DSU4_ATBBM_LD 0x2U
455
456#define DSU4_ATBBM_ST 0x1U
457
468#define DSU4_ICNT_CE 0x80000000U
469
470#define DSU4_ICNT_IC 0x40000000U
471
472#define DSU4_ICNT_PE 0x20000000U
473
474#define DSU4_ICNT_ICOUNT_28_0_SHIFT 0
475#define DSU4_ICNT_ICOUNT_28_0_MASK 0x1fffffffU
476#define DSU4_ICNT_ICOUNT_28_0_GET( _reg ) \
477 ( ( ( _reg ) & DSU4_ICNT_ICOUNT_28_0_MASK ) >> \
478 DSU4_ICNT_ICOUNT_28_0_SHIFT )
479#define DSU4_ICNT_ICOUNT_28_0_SET( _reg, _val ) \
480 ( ( ( _reg ) & ~DSU4_ICNT_ICOUNT_28_0_MASK ) | \
481 ( ( ( _val ) << DSU4_ICNT_ICOUNT_28_0_SHIFT ) & \
482 DSU4_ICNT_ICOUNT_28_0_MASK ) )
483#define DSU4_ICNT_ICOUNT_28_0( _val ) \
484 ( ( ( _val ) << DSU4_ICNT_ICOUNT_28_0_SHIFT ) & \
485 DSU4_ICNT_ICOUNT_28_0_MASK )
486
498#define DSU4_AHBWPC_IN 0x40U
499
500#define DSU4_AHBWPC_CP 0x20U
501
502#define DSU4_AHBWPC_EN 0x10U
503
504#define DSU4_AHBWPC_IN 0x4U
505
506#define DSU4_AHBWPC_CP 0x2U
507
508#define DSU4_AHBWPC_EN 0x1U
509
520#define DSU4_AHBWPD_DATA_SHIFT 0
521#define DSU4_AHBWPD_DATA_MASK 0xffffffffU
522#define DSU4_AHBWPD_DATA_GET( _reg ) \
523 ( ( ( _reg ) & DSU4_AHBWPD_DATA_MASK ) >> \
524 DSU4_AHBWPD_DATA_SHIFT )
525#define DSU4_AHBWPD_DATA_SET( _reg, _val ) \
526 ( ( ( _reg ) & ~DSU4_AHBWPD_DATA_MASK ) | \
527 ( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & \
528 DSU4_AHBWPD_DATA_MASK ) )
529#define DSU4_AHBWPD_DATA( _val ) \
530 ( ( ( _val ) << DSU4_AHBWPD_DATA_SHIFT ) & \
531 DSU4_AHBWPD_DATA_MASK )
532
543#define DSU4_AHBWPM_MASK_SHIFT 0
544#define DSU4_AHBWPM_MASK_MASK 0xffffffffU
545#define DSU4_AHBWPM_MASK_GET( _reg ) \
546 ( ( ( _reg ) & DSU4_AHBWPM_MASK_MASK ) >> \
547 DSU4_AHBWPM_MASK_SHIFT )
548#define DSU4_AHBWPM_MASK_SET( _reg, _val ) \
549 ( ( ( _reg ) & ~DSU4_AHBWPM_MASK_MASK ) | \
550 ( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & \
551 DSU4_AHBWPM_MASK_MASK ) )
552#define DSU4_AHBWPM_MASK( _val ) \
553 ( ( ( _val ) << DSU4_AHBWPM_MASK_SHIFT ) & \
554 DSU4_AHBWPM_MASK_MASK )
555
567#define DSU4_ITBC0_TFILT_SHIFT 28
568#define DSU4_ITBC0_TFILT_MASK 0xf0000000U
569#define DSU4_ITBC0_TFILT_GET( _reg ) \
570 ( ( ( _reg ) & DSU4_ITBC0_TFILT_MASK ) >> \
571 DSU4_ITBC0_TFILT_SHIFT )
572#define DSU4_ITBC0_TFILT_SET( _reg, _val ) \
573 ( ( ( _reg ) & ~DSU4_ITBC0_TFILT_MASK ) | \
574 ( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & \
575 DSU4_ITBC0_TFILT_MASK ) )
576#define DSU4_ITBC0_TFILT( _val ) \
577 ( ( ( _val ) << DSU4_ITBC0_TFILT_SHIFT ) & \
578 DSU4_ITBC0_TFILT_MASK )
579
580#define DSU4_ITBC0_ITPOINTER_SHIFT 0
581#define DSU4_ITBC0_ITPOINTER_MASK 0xffffU
582#define DSU4_ITBC0_ITPOINTER_GET( _reg ) \
583 ( ( ( _reg ) & DSU4_ITBC0_ITPOINTER_MASK ) >> \
584 DSU4_ITBC0_ITPOINTER_SHIFT )
585#define DSU4_ITBC0_ITPOINTER_SET( _reg, _val ) \
586 ( ( ( _reg ) & ~DSU4_ITBC0_ITPOINTER_MASK ) | \
587 ( ( ( _val ) << DSU4_ITBC0_ITPOINTER_SHIFT ) & \
588 DSU4_ITBC0_ITPOINTER_MASK ) )
589#define DSU4_ITBC0_ITPOINTER( _val ) \
590 ( ( ( _val ) << DSU4_ITBC0_ITPOINTER_SHIFT ) & \
591 DSU4_ITBC0_ITPOINTER_MASK )
592
604#define DSU4_ITBC1_WO 0x8000000U
605
606#define DSU4_ITBC1_TLIM_SHIFT 24
607#define DSU4_ITBC1_TLIM_MASK 0x7000000U
608#define DSU4_ITBC1_TLIM_GET( _reg ) \
609 ( ( ( _reg ) & DSU4_ITBC1_TLIM_MASK ) >> \
610 DSU4_ITBC1_TLIM_SHIFT )
611#define DSU4_ITBC1_TLIM_SET( _reg, _val ) \
612 ( ( ( _reg ) & ~DSU4_ITBC1_TLIM_MASK ) | \
613 ( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & \
614 DSU4_ITBC1_TLIM_MASK ) )
615#define DSU4_ITBC1_TLIM( _val ) \
616 ( ( ( _val ) << DSU4_ITBC1_TLIM_SHIFT ) & \
617 DSU4_ITBC1_TLIM_MASK )
618
619#define DSU4_ITBC1_TOV 0x800000U
620
626typedef struct dsu4 {
630 uint32_t ctrl;
631
632 uint32_t reserved_4_8;
633
637 uint32_t dttc;
638
639 uint32_t reserved_c_20[ 5 ];
640
644 uint32_t brss;
645
649 uint32_t dbgm;
650
651 uint32_t reserved_28_40[ 6 ];
652
656 uint32_t atbc;
657
661 uint32_t atbi;
662
666 uint32_t atbfc;
667
671 uint32_t atbfm;
672
676 uint32_t atbba_0;
677
681 uint32_t atbbm_0;
682
686 uint32_t atbba_1;
687
691 uint32_t atbbm_1;
692
693 uint32_t reserved_60_70[ 4 ];
694
698 uint32_t icnt;
699
700 uint32_t reserved_74_80[ 3 ];
701
705 uint32_t ahbwpc;
706
707 uint32_t reserved_84_90[ 3 ];
708
712 uint32_t ahbwpd_0;
713
714 uint32_t reserved_94_9c[ 2 ];
715
719 uint32_t ahbwpd_1;
720
724 uint32_t ahbwpm_0;
725
726 uint32_t reserved_a4_ac[ 2 ];
727
731 uint32_t ahbwpm_1;
732
736 uint32_t ahbwpd_2;
737
738 uint32_t reserved_b4_bc[ 2 ];
739
743 uint32_t ahbwpd_3;
744
748 uint32_t ahbwpm_2;
749
750 uint32_t reserved_c4_cc[ 2 ];
751
755 uint32_t ahbwpm_3;
756
757 uint32_t reserved_d0_110000[ 278476 ];
758
762 uint32_t itbc0;
763
767 uint32_t itbc1;
768
769 uint32_t reserved_110008_400020[ 770054 ];
770
774 uint32_t dtr;
775
779 uint32_t dasi;
781
784#ifdef __cplusplus
785}
786#endif
787
788#endif /* _GRLIB_DSU4_REGS_H */
This structure defines the DSU4 register block memory map.
Definition: dsu4-regs.h:626
uint32_t atbbm_0
See AHB trace buffer break mask registers (ATBBM).
Definition: dsu4-regs.h:681
uint32_t itbc0
See Instruction trace buffer control register 0 (ITBC0).
Definition: dsu4-regs.h:762
uint32_t atbba_1
See AHB trace buffer break address registers (ATBBA).
Definition: dsu4-regs.h:686
uint32_t ahbwpm_1
See AHB watchpoint mask registers (AHBWPM).
Definition: dsu4-regs.h:731
uint32_t ahbwpm_2
See AHB watchpoint mask registers (AHBWPM).
Definition: dsu4-regs.h:748
uint32_t atbfc
See AHB trace buffer filter control register (ATBFC).
Definition: dsu4-regs.h:666
uint32_t ahbwpc
See AHB watchpoint control register (AHBWPC).
Definition: dsu4-regs.h:705
uint32_t ahbwpd_0
See AHB watchpoint data registers (AHBWPD).
Definition: dsu4-regs.h:712
uint32_t atbi
See AHB trace buffer index register (ATBI).
Definition: dsu4-regs.h:661
uint32_t ahbwpd_2
See AHB watchpoint data registers (AHBWPD).
Definition: dsu4-regs.h:736
uint32_t brss
See DSU break and single step register (BRSS).
Definition: dsu4-regs.h:644
uint32_t itbc1
See Instruction trace buffer control register 1 (ITBC1).
Definition: dsu4-regs.h:767
uint32_t dbgm
See DSU debug mode mask register (DBGM).
Definition: dsu4-regs.h:649
uint32_t dasi
See DSU ASI diagnostic access register (DASI).
Definition: dsu4-regs.h:779
uint32_t ahbwpd_1
See AHB watchpoint data registers (AHBWPD).
Definition: dsu4-regs.h:719
uint32_t dttc
See DSU time tag counter register (DTTC).
Definition: dsu4-regs.h:637
uint32_t ahbwpm_0
See AHB watchpoint mask registers (AHBWPM).
Definition: dsu4-regs.h:724
uint32_t ahbwpd_3
See AHB watchpoint data registers (AHBWPD).
Definition: dsu4-regs.h:743
uint32_t atbba_0
See AHB trace buffer break address registers (ATBBA).
Definition: dsu4-regs.h:676
uint32_t atbfm
See AHB trace buffer filter mask register (ATBFM).
Definition: dsu4-regs.h:671
uint32_t dtr
See DSU trap register (DTR).
Definition: dsu4-regs.h:774
uint32_t atbc
See AHB trace buffer control register (ATBC).
Definition: dsu4-regs.h:656
uint32_t ctrl
See DSU control register (CTRL).
Definition: dsu4-regs.h:630
uint32_t icnt
See Instruction trace count register (ICNT).
Definition: dsu4-regs.h:698
uint32_t ahbwpm_3
See AHB watchpoint mask registers (AHBWPM).
Definition: dsu4-regs.h:755
uint32_t atbbm_1
See AHB trace buffer break mask registers (ATBBM).
Definition: dsu4-regs.h:691