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RTEMS 6.1-rc5
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RTEMS 6.1-rc5
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Device configuration interface register definitions. More...
Go to the source code of this file.
Data Structures | |
| struct | zynq_devcfg_regs |
Macros | |
| #define | ZYNQ_DEVCFG_BASE_ADDR 0xF8007000UL |
| #define | ZYNQ_DEVCFG_BITSTREAM_ADDR 0xFFFFFFFFUL |
| #define | ZYNQ_DEVCFG_INTERRUPT_VECTOR 40 |
| #define | ZYNQ_DEVCFG_CTRL_FORCE_RST(val) BSP_FLD32( val, 31, 31 ) |
| #define | ZYNQ_DEVCFG_CTRL_FORCE_RST_GET(reg) BSP_FLD32GET( reg, 31, 31 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_PROG_B_GET(reg) BSP_FLD32GET( reg, 30, 30 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_PROG_B(val) BSP_FLD32( val, 30, 30 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K_GET(reg) BSP_FLD32GET( reg, 29, 29 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K(val) BSP_FLD32( val, 29, 29 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCAP_PR(val) BSP_FLD32( val, 27, 27 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCAP_PR_GET(reg) BSP_FLD32GET( reg, 27, 27 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCAP_PR_ICAP ( 0 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCAP_PR_PCAP ( 1 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCAP_MODE(val) BSP_FLD32( val, 26, 26 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCAP_MODE_GET(reg) BSP_FLD32GET( reg, 26, 26 ) |
| #define | ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN(val) BSP_FLD32( val, 25, 25 ) |
| #define | ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN_GET(reg) BSP_FLD32GET( reg, 25, 25 ) |
| #define | ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN(val) BSP_FLD32( val, 24, 24 ) |
| #define | ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN_GET(reg) BSP_FLD32GET( reg, 24, 24 ) |
| #define | ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS(val) BSP_FLD32( val, 23, 23 ) |
| #define | ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS_GET(reg) BSP_FLD32GET( reg, 23, 23 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE(val) BSP_FLD32( val, 12, 12 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_GET(reg) BSP_FLD32GET( reg, 12, 12 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_BBRAM ( 0 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_EFUSE ( 1 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_AES_EN(val) BSP_FLD32( val, 9, 11 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_GET(reg) BSP_FLD32GET( reg, 9, 11 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_ENABLE ( 0x3 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_DISABLE ( 0x0 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_LOCKDOWN ( 0x1 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN(val) BSP_FLD32( val, 8, 8 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN_GET(reg) BSP_FLD32GET( reg, 8, 8 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_SEC_EN_GET(reg) BSP_FLD32GET( reg, 7, 7 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN(val) BSP_FLD32( val, 6, 6 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN_GET(reg) BSP_FLD32GET( reg, 6, 6 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN(val) BSP_FLD32( val, 5, 5 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN_GET(reg) BSP_FLD32GET( reg, 5, 5 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_NIDEN(val) BSP_FLD32( val, 4, 4 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_NIDEN_GET(reg) BSP_FLD32GET( reg, 4, 4 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_DBGEN(val) BSP_FLD32( val, 3, 3 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_DBGEN_GET(reg) BSP_FLD32GET( reg, 3, 3 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN(val) BSP_FLD32( val, 0, 2 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_GET(reg) BSP_FLD32GET( reg, 0, 2 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_ENABLE ( 0x3 ) |
| #define | ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_BYPASS ( 0x0 ) |
| #define | ZYNQ_DEVCFG_CTRL_RESERVED_BITS ( 0x6000 ) |
| #define | ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT BSP_BIT32( 27 ) |
| #define | ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT_GET(reg) BSP_FLD32GET( reg, 27, 27 ) |
| #define | ZYNQ_DEVCFG_INT_AXI_WERR_INT_GET(reg) BSP_FLD32GET( reg, 22, 22 ) |
| #define | ZYNQ_DEVCFG_INT_AXI_RTO_INT_GET(reg) BSP_FLD32GET( reg, 21, 21 ) |
| #define | ZYNQ_DEVCFG_INT_AXI_RERR_INT_GET(reg) BSP_FLD32GET( reg, 20, 20 ) |
| #define | ZYNQ_DEVCFG_INT_RX_FIFO_OV_INT_GET(reg) BSP_FLD32GET( reg, 18, 18 ) |
| #define | ZYNQ_DEVCFG_INT_DMA_CMD_ERR_INT_GET(reg) BSP_FLD32GET( reg, 15, 15 ) |
| #define | ZYNQ_DEVCFG_INT_DMA_Q_OV_INT_GET(reg) BSP_FLD32GET( reg, 14, 14 ) |
| #define | ZYNQ_DEVCFG_INT_DMA_DONE_INT BSP_BIT32( 13 ) |
| #define | ZYNQ_DEVCFG_INT_DMA_DONE_INT_GET(reg) BSP_FLD32GET( reg, 13, 13 ) |
| #define | ZYNQ_DEVCFG_INT_D_P_DONE_INT BSP_BIT32( 12 ) |
| #define | ZYNQ_DEVCFG_INT_D_P_DONE_INT_GET(reg) BSP_FLD32GET( reg, 12, 12 ) |
| #define | ZYNQ_DEVCFG_INT_P2D_LEN_ERR_INT_GET(reg) BSP_FLD32GET( reg, 11, 11 ) |
| #define | ZYNQ_DEVCFG_INT_PCFG_HMAC_ERR_INT_GET(reg) BSP_FLD32GET( reg, 6, 6 ) |
| #define | ZYNQ_DEVCFG_INT_PCFG_SEU_ERR_INT_GET(reg) BSP_FLD32GET( reg, 5, 5 ) |
| #define | ZYNQ_DEVCFG_INT_PCFG_POR_B_INT_GET(reg) BSP_FLD32GET( reg, 4, 4 ) |
| #define | ZYNQ_DEVCFG_INT_PCFG_CFG_RST_INT_GET(reg) BSP_FLD32GET( reg, 3, 3 ) |
| #define | ZYNQ_DEVCFG_INT_PCFG_DONE_INT BSP_BIT32( 2 ) |
| #define | ZYNQ_DEVCFG_INT_PCFG_DONE_INT_GET(reg) BSP_FLD32GET( reg, 2, 2 ) |
| #define | ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT BSP_BIT32( 1 ) |
| #define | ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT_GET(reg) BSP_FLD32GET( reg, 1, 1 ) |
| #define | ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT BSP_BIT32( 0 ) |
| #define | ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT_GET(reg) BSP_FLD32GET( reg, 0, 0 ) |
| #define | ZYNQ_DEVCFG_INT_ALL ( 0xf8f7f87f ) |
| #define | ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F(val) BSP_FLD32( val, 31, 31 ) |
| #define | ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F_GET(reg) BSP_FLD32GET( reg, 31, 31 ) |
| #define | ZYNQ_DEVCFG_STATUS_PCFG_INIT_GET(reg) BSP_FLD32GET( reg, 4, 4 ) |
| #define | ZYNQ_DEVCFG_DMA_SRC_ADDR_DMA_DONE_INT_WAIT_PCAP ( 0x1 ) |
| #define | ZYNQ_DEVCFG_DMA_DST_ADDR_DMA_DONE_INT_WAIT_PCAP ( 0x1 ) |
| #define | ZYNQ_DEVCFG_DMA_SRC_LEN_LEN(val) BSP_FLD32( val, 0, 26 ) |
| #define | ZYNQ_DEVCFG_DMA_DEST_LEN_LEN(val) BSP_FLD32( val, 0, 26 ) |
| #define | ZYNQ_DEVCFG_MCTRL_PS_VERSION_GET(reg) BSP_FLD32GET( reg, 28, 31 ) |
| #define | ZYNQ_DEVCFG_MCTRL_PS_VERSION_1_0 0x0 |
| #define | ZYNQ_DEVCFG_MCTRL_PS_VERSION_2_0 0x1 |
| #define | ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_0 0x2 |
| #define | ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_1 0x3 |
| #define | ZYNQ_DEVCFG_MCTRL_PCFG_POR_B_GET(reg) BSP_FLD32GET( reg, 8, 8 ) |
| #define | ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK_GET(reg) BSP_FLD32GET( reg, 4, 4 ) |
| #define | ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK(val) BSP_FLD32( val, 4, 4 ) |
| #define | ZYNQ_DEVCFG_MCTRL_RESERVED_SET_BITS ( 0x800000 ) |
| #define | ZYNQ_DEVCFG_MCTRL_RESERVED_UNSET_BITS ( 0x3 ) |
| #define | ZYNQ_DEVCFG_MCTRL_SET(reg, val) |
Device configuration interface register definitions.
| #define ZYNQ_DEVCFG_MCTRL_SET | ( | reg, | |
| val | |||
| ) |
1.9.6