RTEMS 6.1-rc5
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xttcps_hw.h
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1/******************************************************************************
2* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
3* SPDX-License-Identifier: MIT
4******************************************************************************/
5
6/*****************************************************************************/
32#ifndef XTTCPS_HW_H /* prevent circular inclusions */
33#define XTTCPS_HW_H /* by using protection macros */
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
39/***************************** Include Files *********************************/
40
41#ifndef __rtems__
42#include "xil_types.h"
43#include "xil_assert.h"
44#include "xil_io.h"
45#else
46#include <bsp/xil-compat.h>
47#endif
48
49/************************** Constant Definitions *****************************/
50/*
51 * Flag for a9 processor
52 */
53 #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
54 #define ARMA9
55 #endif
56
63#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U
64#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU
65#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U
66#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U
67#define XTTCPS_MATCH_0_OFFSET 0x00000030U
68#define XTTCPS_MATCH_1_OFFSET 0x0000003CU
69#define XTTCPS_MATCH_2_OFFSET 0x00000048U
70#define XTTCPS_ISR_OFFSET 0x00000054U
71#define XTTCPS_IER_OFFSET 0x00000060U
72/* @} */
73
78#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U
79#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU
80#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U
81#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U
82#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U
83#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U
84/* @} */
85
90#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U
91#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U
92#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U
93#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U
94#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U
95#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U
96#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U
97#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U
98/* @} */
99
104#if defined(ARMA9)
105#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU
106#else
107#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU
108#endif
109/* @} */
110
116#if defined(ARMA9)
117#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU
118#else
119#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU
120#endif
121/* @} */
122
128#if defined(ARMA9)
129#define XTTCPS_MATCH_MASK 0x0000FFFFU
130#else
131#define XTTCPS_MATCH_MASK 0xFFFFFFFFU
132#endif
133#define XTTCPS_NUM_MATCH_REG 3U
134/* @} */
135
141#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U
142#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U
143#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U
144#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U
145#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U
146#define XTTCPS_IXR_ALL_MASK 0x0000001FU
147/* @} */
148
149
150/***************** Macros (Inline Functions) Definitions *********************/
151
152/****************************************************************************/
166#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
167 (Xil_In32((BaseAddress) + (u32)(RegOffset)))
168
169/****************************************************************************/
185#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
186 (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
187
188/****************************************************************************/
201#define XTtcPs_Match_N_Offset(MatchIndex) \
202 ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
203
204/************************** Function Prototypes ******************************/
205
206/************************** Variable Definitions *****************************/
207#ifdef __cplusplus
208}
209#endif
210#endif /* end of protection macro */