Xilinx Triple Timer Counter (TTC) Clock Driver

This group contains the Xilinx Triple Timer Counter (TTC) Clock Driver implementation. More...

Files
file	xttcps_hw.h
file	xil-ttc.c
	This source file contains a Clock Driver implementation using the Xilinx Triple Timer Counter (TTC).

Data Structures
struct	xil_ttc_timecounter

Macros
#define	XTTCPS_HW_H   /* by using protection macros */
#define	ARMA9
#define	Clock_driver_support_at_tick(arg)    xil_ttc_clock_driver_support_at_tick(arg)
#define	Clock_driver_support_initialize_hardware    xil_ttc_clock_driver_support_initialize_hardware
#define	Clock_driver_support_install_isr(isr)    xil_ttc_clock_driver_support_install_isr(isr)

Functions
uint32_t	_CPU_Counter_frequency (void)
	Gets the current CPU counter frequency in Hz.
CPU_Counter_ticks	_CPU_Counter_read (void)
	Gets the current CPU counter value.
	RTEMS_SYSINIT_ITEM (xil_ttc_initialize, RTEMS_SYSINIT_CPU_COUNTER, RTEMS_SYSINIT_ORDER_MIDDLE)

Register Map
Register offsets from the base address of the device.
#define	XTTCPS_CLK_CNTRL_OFFSET   0x00000000U
#define	XTTCPS_CNT_CNTRL_OFFSET   0x0000000CU
#define	XTTCPS_COUNT_VALUE_OFFSET   0x00000018U
#define	XTTCPS_INTERVAL_VAL_OFFSET   0x00000024U
#define	XTTCPS_MATCH_0_OFFSET   0x00000030U
#define	XTTCPS_MATCH_1_OFFSET   0x0000003CU
#define	XTTCPS_MATCH_2_OFFSET   0x00000048U
#define	XTTCPS_ISR_OFFSET   0x00000054U
#define	XTTCPS_IER_OFFSET   0x00000060U

Clock Control Register
Clock Control Register definitions
#define	XTTCPS_CLK_CNTRL_PS_EN_MASK   0x00000001U
#define	XTTCPS_CLK_CNTRL_PS_VAL_MASK   0x0000001EU
#define	XTTCPS_CLK_CNTRL_PS_VAL_SHIFT   1U
#define	XTTCPS_CLK_CNTRL_PS_DISABLE   16U
#define	XTTCPS_CLK_CNTRL_SRC_MASK   0x00000020U
#define	XTTCPS_CLK_CNTRL_EXT_EDGE_MASK   0x00000040U

Counter Control Register
Counter Control Register definitions
#define	XTTCPS_CNT_CNTRL_DIS_MASK   0x00000001U
#define	XTTCPS_CNT_CNTRL_INT_MASK   0x00000002U
#define	XTTCPS_CNT_CNTRL_DECR_MASK   0x00000004U
#define	XTTCPS_CNT_CNTRL_MATCH_MASK   0x00000008U
#define	XTTCPS_CNT_CNTRL_RST_MASK   0x00000010U
#define	XTTCPS_CNT_CNTRL_EN_WAVE_MASK   0x00000020U
#define	XTTCPS_CNT_CNTRL_POL_WAVE_MASK   0x00000040U
#define	XTTCPS_CNT_CNTRL_RESET_VALUE   0x00000021U

Current Counter Value Register
Current Counter Value Register definitions
#define	XTTCPS_COUNT_VALUE_MASK   0x0000FFFFU

Interval Value Register
Interval Value Register is the maximum value the counter will count up or down to.
#define	XTTCPS_INTERVAL_VAL_MASK   0x0000FFFFU

Match Registers
Definitions for Match registers, each timer counter has three match registers.
#define	XTTCPS_MATCH_MASK   0x0000FFFFU
#define	XTTCPS_NUM_MATCH_REG   3U

Interrupt Registers
Following register bit mask is for all interrupt registers.
#define	XTTCPS_IXR_INTERVAL_MASK   0x00000001U
#define	XTTCPS_IXR_MATCH_0_MASK   0x00000002U
#define	XTTCPS_IXR_MATCH_1_MASK   0x00000004U
#define	XTTCPS_IXR_MATCH_2_MASK   0x00000008U
#define	XTTCPS_IXR_CNT_OVR_MASK   0x00000010U
#define	XTTCPS_IXR_ALL_MASK   0x0000001FU
#define	XTtcPs_ReadReg(BaseAddress, RegOffset)    (Xil_In32((BaseAddress) + (u32)(RegOffset)))
#define	XTtcPs_WriteReg(BaseAddress, RegOffset, Data)    (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
#define	XTtcPs_Match_N_Offset(MatchIndex)    ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))

Detailed Description

This group contains the Xilinx Triple Timer Counter (TTC) Clock Driver implementation.

Macro Definition Documentation

XTTCPS_CLK_CNTRL_EXT_EDGE_MASK

#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK   0x00000040U

External Clock edge

XTTCPS_CLK_CNTRL_OFFSET

#define XTTCPS_CLK_CNTRL_OFFSET   0x00000000U

Clock Control Register

XTTCPS_CLK_CNTRL_PS_DISABLE

#define XTTCPS_CLK_CNTRL_PS_DISABLE   16U

Prescale disable

XTTCPS_CLK_CNTRL_PS_EN_MASK

#define XTTCPS_CLK_CNTRL_PS_EN_MASK   0x00000001U

Prescale enable

XTTCPS_CLK_CNTRL_PS_VAL_MASK

#define XTTCPS_CLK_CNTRL_PS_VAL_MASK   0x0000001EU

Prescale value

XTTCPS_CLK_CNTRL_PS_VAL_SHIFT

#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT   1U

Prescale shift

XTTCPS_CLK_CNTRL_SRC_MASK

#define XTTCPS_CLK_CNTRL_SRC_MASK   0x00000020U

Clock source

XTTCPS_CNT_CNTRL_DECR_MASK

#define XTTCPS_CNT_CNTRL_DECR_MASK   0x00000004U

Decrement mode

XTTCPS_CNT_CNTRL_DIS_MASK

#define XTTCPS_CNT_CNTRL_DIS_MASK   0x00000001U

Disable the counter

XTTCPS_CNT_CNTRL_EN_WAVE_MASK

#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK   0x00000020U

Enable waveform

XTTCPS_CNT_CNTRL_INT_MASK

#define XTTCPS_CNT_CNTRL_INT_MASK   0x00000002U

Interval mode

XTTCPS_CNT_CNTRL_MATCH_MASK

#define XTTCPS_CNT_CNTRL_MATCH_MASK   0x00000008U

Match mode

XTTCPS_CNT_CNTRL_OFFSET

#define XTTCPS_CNT_CNTRL_OFFSET   0x0000000CU

Counter Control Register

XTTCPS_CNT_CNTRL_POL_WAVE_MASK

#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK   0x00000040U

Waveform polarity

XTTCPS_CNT_CNTRL_RESET_VALUE

#define XTTCPS_CNT_CNTRL_RESET_VALUE   0x00000021U

Reset value

XTTCPS_CNT_CNTRL_RST_MASK

#define XTTCPS_CNT_CNTRL_RST_MASK   0x00000010U

Reset counter

XTTCPS_COUNT_VALUE_MASK

#define XTTCPS_COUNT_VALUE_MASK   0x0000FFFFU

16-bit counter value

XTTCPS_COUNT_VALUE_OFFSET

#define XTTCPS_COUNT_VALUE_OFFSET   0x00000018U

Current Counter Value

XTTCPS_IER_OFFSET

#define XTTCPS_IER_OFFSET   0x00000060U

Interrupt Enable Register

XTTCPS_INTERVAL_VAL_MASK

#define XTTCPS_INTERVAL_VAL_MASK   0x0000FFFFU

16-bit Interval value

XTTCPS_INTERVAL_VAL_OFFSET

#define XTTCPS_INTERVAL_VAL_OFFSET   0x00000024U

Interval Count Value

XTTCPS_ISR_OFFSET

#define XTTCPS_ISR_OFFSET   0x00000054U

Interrupt Status Register

XTTCPS_IXR_ALL_MASK

#define XTTCPS_IXR_ALL_MASK   0x0000001FU

All valid Interrupts

XTTCPS_IXR_CNT_OVR_MASK

#define XTTCPS_IXR_CNT_OVR_MASK   0x00000010U

Counter Overflow

XTTCPS_IXR_INTERVAL_MASK

#define XTTCPS_IXR_INTERVAL_MASK   0x00000001U

Interval Interrupt

XTTCPS_IXR_MATCH_0_MASK

#define XTTCPS_IXR_MATCH_0_MASK   0x00000002U

Match 1 Interrupt

XTTCPS_IXR_MATCH_1_MASK

#define XTTCPS_IXR_MATCH_1_MASK   0x00000004U

Match 2 Interrupt

XTTCPS_IXR_MATCH_2_MASK

#define XTTCPS_IXR_MATCH_2_MASK   0x00000008U

Match 3 Interrupt

XTTCPS_MATCH_0_OFFSET

#define XTTCPS_MATCH_0_OFFSET   0x00000030U

Match 1 value

XTTCPS_MATCH_1_OFFSET

#define XTTCPS_MATCH_1_OFFSET   0x0000003CU

Match 2 value

XTTCPS_MATCH_2_OFFSET

#define XTTCPS_MATCH_2_OFFSET   0x00000048U

Match 3 value

XTTCPS_MATCH_MASK

#define XTTCPS_MATCH_MASK   0x0000FFFFU

16-bit Match value

XTtcPs_Match_N_Offset

#define XTtcPs_Match_N_Offset

(

MatchIndex

)

((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))

Calculate a match register offset using the Match Register index.

Parameters

MatchIndex

is the 0-2 value of the match register

Returns

MATCH_N_OFFSET.

Note

C-style signature: u32 XTtcPs_Match_N_Offset(u8 MatchIndex)

XTTCPS_NUM_MATCH_REG

#define XTTCPS_NUM_MATCH_REG   3U

Num of Match reg

XTtcPs_ReadReg

#define XTtcPs_ReadReg	(		BaseAddress,
			RegOffset
	)		(Xil_In32((BaseAddress) + (u32)(RegOffset)))

Read the given Timer Counter register.

Parameters

BaseAddress	is the base address of the timer counter device.
RegOffset	is the register offset to be read

Returns

The 32-bit value of the register

Note

C-style signature: u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)

XTtcPs_WriteReg

#define XTtcPs_WriteReg	(		BaseAddress,
			RegOffset,
			Data
	)		(Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))

Write the given Timer Counter register.

Parameters

BaseAddress	is the base address of the timer counter device.
RegOffset	is the register offset to be written
Data	is the 32-bit value to write to the register

Returns

None.

Note

C-style signature: void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset, u32 Data)

Function Documentation

_CPU_Counter_frequency()

uint32_t _CPU_Counter_frequency

(

void

)

Gets the current CPU counter frequency in Hz.

Returns

Returns the current CPU counter frequency in Hz.

_CPU_Counter_read()

CPU_Counter_ticks _CPU_Counter_read

(

void

)

Gets the current CPU counter value.

A CPU counter should be some monotonically increasing free-running counter. It ticks usually with a frequency close to the CPU or system bus clock. The counter should not be affected by power saving states so that it can be used for timestamps. The CPU counter should be initialized at the RTEMS_SYSINIT_CPU_COUNTER initialization step if necessary. If RTEMS_PROFILING is enabled, the CPU counter may have to work very early in the system initialization to avoid invalid profiling statistics.

Returns

Returns the current CPU counter value.