xqspipsu_flash_config.h File Reference

#include "xparameters.h"
#include "xqspipsu.h"

Go to the source code of this file.

Data Structures
struct	FlashInfo

Macros
#define	XQSPIPSU_FLASH_CONFIG_H_   /* by using protection macros */
#define	WRITE_STATUS_CMD   0x01
#define	WRITE_CMD   0x02
#define	READ_CMD   0x03
#define	WRITE_DISABLE_CMD   0x04
#define	READ_STATUS_CMD   0x05
#define	WRITE_ENABLE_CMD   0x06
#define	VOLATILE_WRITE_ENABLE_CMD   0x50
#define	QUAD_MODE_ENABLE_BIT   0x06
#define	FAST_READ_CMD   0x0B
#define	DUAL_READ_CMD   0x3B
#define	QUAD_READ_CMD   0x6B
#define	BULK_ERASE_CMD   0xC7
#define	SEC_ERASE_CMD   0xD8
#define	READ_ID   0x9F
#define	READ_SFDP   0x5A
#define	READ_CONFIG_CMD   0x35
#define	WRITE_CONFIG_CMD   0x01
#define	ENTER_4B_ADDR_MODE   0xB7
#define	EXIT_4B_ADDR_MODE   0xE9
#define	EXIT_4B_ADDR_MODE_ISSI   0x29
#define	READ_CMD_4B   0x13
#define	FAST_READ_CMD_4B   0x0C
#define	DUAL_READ_CMD_4B   0x3C
#define	QUAD_READ_CMD_4B   0x6C
#define	WRITE_CMD_4B   0x12
#define	SEC_ERASE_CMD_4B   0xDC
#define	BANK_REG_RD   0x16
#define	BANK_REG_WR   0x17
#define	READ_ECCSR   0x18
#define	EXTADD_REG_RD   0xC8
#define	EXTADD_REG_WR   0xC5
#define	DIE_ERASE_CMD   0xC4
#define	READ_FLAG_STATUS_CMD   0x70
#define	WRITE_STATUS_REG_2_CMD   0x31
#define	READ_STATUS_REG_2_CMD   0x35
#define	WB_QUAD_MODE_ENABLE_BIT   0x01
#define	COMMAND_OFFSET   0 /* Flash instruction */
#define	ADDRESS_1_OFFSET   1 /* MSB byte of address to read or write */
#define	ADDRESS_2_OFFSET   2 /* Middle byte of address to read or write */
#define	ADDRESS_3_OFFSET   3 /* LSB byte of address to read or write */
#define	ADDRESS_4_OFFSET
#define	DATA_OFFSET   5 /* Start of Data for Read/Write */
#define	DUMMY_OFFSET
#define	DUMMY_SIZE
#define	DUMMY_CLOCKS
#define	RD_ID_SIZE   4 /* Read ID command + 3 bytes ID response */
#define	BULK_ERASE_SIZE   1 /* Bulk Erase command size */
#define	SEC_ERASE_SIZE   4 /* Sector Erase command + Sector address */
#define	BANK_SEL_SIZE
#define	RD_CFG_SIZE
#define	WR_CFG_SIZE
#define	DIE_ERASE_SIZE   4 /* Die Erase command + Die address */
#define	OVERHEAD_SIZE   4
#define	FLASH1BASE   0x0000000
#define	SIXTEENMB   0x1000000
#define	FLASH_QUAD_EN_MASK   0x02
#define	FLASH_SRWD_MASK   0x80
#define	BANKMASK   0xF000000
#define	BUSWIDTH_SINGLE   0
#define	BUSWIDTH_DOUBLE   1
#define	MICRON_ID_BYTE0   0x20
#define	SPANSION_ID_BYTE0   0x01
#define	WINBOND_ID_BYTE0   0xEF
#define	MACRONIX_ID_BYTE0   0xC2
#define	ISSI_ID_BYTE0   0x9D

Variables
FlashInfo	Flash_Config_Table []

Detailed Description

This file contains flash configuration table and flash related defines. This file should be included in the example files and compiled along with the examples (*.c).

Note

None.

  MODIFICATION HISTORY:

  Ver   Who Date     Changes
  ----- --- -------- -----------------------------------------------
  1.12  akm 07/07/20 First release
  1.12  akm 07/07/20 Add support for Macronix flash(MX66U2G45G, MX66L2G45G)
                     and ISSI flash(IS25LP01G, IS25WP01G) parts.
  1.13  akm 12/10/20 Set Read command as per the qspi bus width.
  1.14  akm 07/16/21 Enable Quad Mode for Winbond flashes.
  1.15  akm 11/19/21 Fix read/write failures on Spansion flash parts.

*

Macro Definition Documentation

ADDRESS_4_OFFSET

#define ADDRESS_4_OFFSET

Value:

                   4 /* LSB byte of address to read or write
                   * when 4 byte address
                   */

BANK_SEL_SIZE

#define BANK_SEL_SIZE

Value:

                   2 /* BRWR or EARWR command + 1 byte bank
                   * value
                   */

DUMMY_CLOCKS

#define DUMMY_CLOCKS

Value:

                   8 /* Number of dummy bytes for fast, dual and
                   * quad reads
                   */

DUMMY_OFFSET

#define DUMMY_OFFSET

Value:

                   4 /* Dummy byte offset for fast, dual and quad
                   * reads
                   */

DUMMY_SIZE

#define DUMMY_SIZE

Value:

                   1 /* Number of dummy bytes for fast, dual and
                   * quad reads
                   */

RD_CFG_SIZE

#define RD_CFG_SIZE

Value:

                   2 /* 1 byte Configuration register + RD CFG
                   * command
                   */

WR_CFG_SIZE

#define WR_CFG_SIZE

Value:

                   3 /* WRR command + 1 byte each Status and
                   * Config Reg
                   */