xnandpsu.h

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/******************************************************************************
* Copyright (C) 2015 - 2022 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
 
/*****************************************************************************/
#ifndef XNANDPSU_H      /* prevent circular inclusions */
#define XNANDPSU_H      /* by using protection macros */
 
#ifdef __cplusplus
extern "C" {
#endif
 
/***************************** Include Files *********************************/
#ifndef __rtems__
#include "xil_types.h"
#include <string.h>
#include "xstatus.h"
#include "xil_assert.h"
#include "xnandpsu_hw.h"
#include "xnandpsu_onfi.h"
#include "xil_cache.h"
#if defined  (XCLOCKING)
#include "xil_clocking.h"
#endif
#else
#include <bsp/xil-compat.h>
#include <string.h>
#include "xnandpsu_hw.h"
#include "xnandpsu_onfi.h"
#endif
/************************** Constant Definitions *****************************/
 
#define XNANDPSU_DEBUG
 
#ifdef __rtems__
#define XNANDPSU_MAX_TARGETS        2U  
#else
#define XNANDPSU_MAX_TARGETS        1U  
#endif
#define XNANDPSU_MAX_PKT_SIZE       0x7FFU  
#define XNANDPSU_MAX_PKT_COUNT      0xFFFU  
#define XNANDPSU_PAGE_SIZE_512      512U    
#define XNANDPSU_PAGE_SIZE_2K       2048U   
#define XNANDPSU_PAGE_SIZE_4K       4096U   
#define XNANDPSU_PAGE_SIZE_8K       8192U   
#define XNANDPSU_PAGE_SIZE_16K      16384U  
#define XNANDPSU_PAGE_SIZE_1K_16BIT 1024U   
#define XNANDPSU_MAX_PAGE_SIZE      16384U  
#define XNANDPSU_HAMMING        0x1U    
#define XNANDPSU_BCH            0x2U    
#define XNANDPSU_MAX_BLOCKS     16384U  
#define XNANDPSU_MAX_SPARE_SIZE     0x800U  
#define XNANDPSU_MAX_LUNS       8U  
#define XNANDPSU_MAX_PAGES_PER_BLOCK    512U    
#define XNANDPSU_INTR_POLL_TIMEOUT  0xF000000U
 
#define XNANDPSU_SDR_CLK        ((u16)100U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_0        ((u16)20U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_1        ((u16)33U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_2        ((u16)50U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_3        ((u16)66U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_4        ((u16)83U * (u16)1000U * (u16)1000U)
#define XNANDPSU_NVDDR_CLK_5        ((u16)100U * (u16)1000U * (u16)1000U)
 
#define XNANDPSU_MAX_TIMING_MODE    5
 
#ifdef __rtems__
#define XNANDPSU_PAGE_CACHE_UNAVAILABLE -2
#define XNANDPSU_PAGE_CACHE_NONE    -1
#endif
 
typedef struct {
    u16 DeviceId;       
    u32 BaseAddress;    
    u8 IsCacheCoherent; 
#if defined  (XCLOCKING)
    u32 RefClk;     
#endif
} XNandPsu_Config;
 
typedef enum {
    XNANDPSU_SDR = 0U,      
    XNANDPSU_NVDDR          
} XNandPsu_DataInterface;
 
typedef enum {
    XNANDPSU_SDR0 = 0U,
    XNANDPSU_SDR1,
    XNANDPSU_SDR2,
    XNANDPSU_SDR3,
    XNANDPSU_SDR4,
    XNANDPSU_SDR5,
    XNANDPSU_NVDDR0,
    XNANDPSU_NVDDR1,
    XNANDPSU_NVDDR2,
    XNANDPSU_NVDDR3,
    XNANDPSU_NVDDR4,
    XNANDPSU_NVDDR5
} XNandPsu_TimingMode;
 
typedef enum {
    XNANDPSU_POLLING = 0,       
    XNANDPSU_INTERRUPT      
} XNandPsu_SWMode;
 
typedef enum {
    XNANDPSU_PIO = 0,       
    XNANDPSU_SDMA,          
    XNANDPSU_MDMA           
} XNandPsu_DmaMode;
 
typedef enum {
    XNANDPSU_NONE = 0,
    XNANDPSU_HWECC,
    XNANDPSU_EZNAND,
    XNANDPSU_ONDIE
} XNandPsu_EccMode;
 
typedef struct {
    u32 PageOffset[XNANDPSU_MAX_TARGETS];
    u32 SigOffset;      
    u32 VerOffset;      
    u32 SigLength;      
    u32 MaxBlocks;      
    char Signature[5];  
    u8 Version[XNANDPSU_MAX_TARGETS];
    u32 Valid;      
} XNandPsu_BbtDesc;
 
typedef struct {
    u32 Options;        
    u32 Offset;     
    u32 Length;     
    u8 Pattern[2];      
} XNandPsu_BadBlockPattern;
 
typedef struct {
    /* Parameter page information */
    u32 BytesPerPage;   
    u16 SpareBytesPerPage;  
    u32 PagesPerBlock;  
    u32 BlocksPerLun;   
    u8 NumLuns;     
    u8 RowAddrCycles;   
    u8 ColAddrCycles;   
    u8 NumBitsPerCell;  
    u8 NumBitsECC;      
    u32 EccCodeWordSize;    
    /* Driver specific information */
    u32 BlockSize;      
    u32 NumTargetPages; 
    u32 NumTargetBlocks;    
    u64 TargetSize;     
    u8 NumTargets;      
    u32 NumPages;       
    u32 NumBlocks;      
    u64 DeviceSize;     
} XNandPsu_Geometry;
 
typedef struct {
    u32 NvDdr;
    u32 EzNand;
    u32 OnDie;
    u32 ExtPrmPage;
} XNandPsu_Features;
 
typedef struct {
    u16 PageSize;
    u16 CodeWordSize;
    u8 NumEccBits;
    u8 IsBCH;
    u16 EccAddr;
    u16 EccSize;
} XNandPsu_EccMatrix;
 
typedef struct {
    u16 EccAddr;
    u16 EccSize;
    u16 CodeWordSize;
    u8 NumEccBits;
    u8 IsBCH;
} XNandPsu_EccCfg;
 
#ifdef __ICCARM__
#pragma pack(push, 1)
#endif
typedef struct {
    u32 IsReady;        
    XNandPsu_Config Config;
    u32 Ecc_Stat_PerPage_flips; 
    u32 Ecc_Stats_total_flips;     
    XNandPsu_DataInterface DataInterface;
    XNandPsu_TimingMode TimingMode;
    XNandPsu_SWMode Mode;       
    XNandPsu_DmaMode DmaMode;   
    XNandPsu_EccMode EccMode;   
    XNandPsu_EccCfg EccCfg;     
    XNandPsu_Geometry Geometry; 
    XNandPsu_Features Features; 
#ifdef __rtems__
    int32_t PartialDataPageIndex;   
#endif
#ifdef __ICCARM__
    u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE];  
#pragma pack(pop)
#else
    u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE] __attribute__ ((aligned(64)));
#endif
    /* Bad block table definitions */
    XNandPsu_BbtDesc BbtDesc;   
    XNandPsu_BbtDesc BbtMirrorDesc; 
    XNandPsu_BadBlockPattern BbPattern; 
    u8 Bbt[XNANDPSU_MAX_BLOCKS >> 2];   
} XNandPsu;
 
/******************* Macro Definitions (Inline Functions) *******************/
 
/*****************************************************************************/
#define XNandPsu_SetBits(InstancePtr, RegOffset, BitMask)       \
    XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,        \
        (RegOffset),                        \
    ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,  \
        (RegOffset)) | (BitMask))))
 
/*****************************************************************************/
#define XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask)       \
    XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,        \
        (RegOffset),                        \
    ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,  \
        (RegOffset)) & ~(BitMask))))
 
/*****************************************************************************/
#define XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value)   \
    XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,        \
        (RegOffset),                        \
    ((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\
        (u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value))))
 
/*****************************************************************************/
#define XNandPsu_IntrSigEnable(InstancePtr, Mask)           \
        XNandPsu_SetBits((InstancePtr),             \
            XNANDPSU_INTR_SIG_EN_OFFSET,            \
            (Mask))
 
/*****************************************************************************/
#define XNandPsu_IntrSigClear(InstancePtr, Mask)            \
        XNandPsu_ClrBits((InstancePtr),             \
            XNANDPSU_INTR_SIG_EN_OFFSET,            \
            (Mask))
 
/*****************************************************************************/
#define XNandPsu_IntrStsEnable(InstancePtr, Mask)           \
        XNandPsu_SetBits((InstancePtr),             \
            XNANDPSU_INTR_STS_EN_OFFSET,            \
            (Mask))
 
/*****************************************************************************/
#define IS_ONFI(Buff)                   \
    ((Buff)[0] == (u8)'O') && ((Buff)[1] == (u8)'N') && \
    ((Buff)[2] == (u8)'F') && ((Buff)[3] == (u8)'I')
 
/************************** Function Prototypes *****************************/
 
s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
                u32 EffectiveAddr);
 
s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length);
 
s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length,
                            u8 *SrcBuf);
 
s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length,
                            u8 *DestBuf);
 
s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block);
 
s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
 
s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
 
s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
                XNandPsu_DataInterface NewIntf,
                XNandPsu_TimingMode NewMode);
 
s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
                                u8 *Buf);
 
s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
                                u8 *Buf);
 
s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr);
 
s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block);
 
#ifdef __rtems__
#include <stdbool.h>
/*****************************************************************************/
s32 XNandPsu_MarkBlock(XNandPsu *InstancePtr, u32 Block, u8 BlockMark);
 
/*****************************************************************************/
bool XNandPsu_StageBlockMark(XNandPsu *InstancePtr, u32 Block, u8 BlockMark);
 
/*****************************************************************************/
s32 XNandPsu_UpdateBbt(XNandPsu *InstancePtr, u32 Target);
#endif
 
void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr);
 
void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr);
 
void XNandPsu_EnableEccMode(XNandPsu *InstancePtr);
 
void XNandPsu_DisableEccMode(XNandPsu *InstancePtr);
 
void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
            u8 DmaMode, u8 AddrCycles);
 
/* XNandPsu_LookupConfig in xnandpsu_sinit.c */
XNandPsu_Config *XNandPsu_LookupConfig(u16 DevID);
 
 
#ifdef __cplusplus
}
#endif
 
#endif /* XNANDPSU_H end of protection macro */