RTEMS 6.1-rc5
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PLL configuration for ARM. More...
#include <fsl_clock.h>
Data Fields | |
uint32_t | loopDivider |
uint8_t | src |
clock_pll_post_div_t | postDivider |
PLL configuration for ARM.
The output clock frequency is:
Fout=Fin*loopDivider /(2 * postDivider).
Fin is always 24MHz.
uint8_t _clock_arm_pll_config::src |
Pll clock source, reference _clock_pll_clk_src