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RTEMS 6.1-rc5
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RTEMS 6.1-rc5
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Afec hardware registers. More...
#include <component_afec.h>
Data Fields | |
| __O uint32_t | AFEC_CR |
| (Afec Offset: 0x00) AFEC Control Register | |
| __IO uint32_t | AFEC_MR |
| (Afec Offset: 0x04) AFEC Mode Register | |
| __IO uint32_t | AFEC_EMR |
| (Afec Offset: 0x08) AFEC Extended Mode Register | |
| __IO uint32_t | AFEC_SEQ1R |
| (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register | |
| __IO uint32_t | AFEC_SEQ2R |
| (Afec Offset: 0x10) AFEC Channel Sequence 2 Register | |
| __O uint32_t | AFEC_CHER |
| (Afec Offset: 0x14) AFEC Channel Enable Register | |
| __O uint32_t | AFEC_CHDR |
| (Afec Offset: 0x18) AFEC Channel Disable Register | |
| __I uint32_t | AFEC_CHSR |
| (Afec Offset: 0x1C) AFEC Channel Status Register | |
| __I uint32_t | AFEC_LCDR |
| (Afec Offset: 0x20) AFEC Last Converted Data Register | |
| __O uint32_t | AFEC_IER |
| (Afec Offset: 0x24) AFEC Interrupt Enable Register | |
| __O uint32_t | AFEC_IDR |
| (Afec Offset: 0x28) AFEC Interrupt Disable Register | |
| __I uint32_t | AFEC_IMR |
| (Afec Offset: 0x2C) AFEC Interrupt Mask Register | |
| __I uint32_t | AFEC_ISR |
| (Afec Offset: 0x30) AFEC Interrupt Status Register | |
| __I uint32_t | Reserved1 [6] |
| __I uint32_t | AFEC_OVER |
| (Afec Offset: 0x4C) AFEC Overrun Status Register | |
| __IO uint32_t | AFEC_CWR |
| (Afec Offset: 0x50) AFEC Compare Window Register | |
| __IO uint32_t | AFEC_CGR |
| (Afec Offset: 0x54) AFEC Channel Gain Register | |
| __I uint32_t | Reserved2 [2] |
| __IO uint32_t | AFEC_DIFFR |
| (Afec Offset: 0x60) AFEC Channel Differential Register | |
| __IO uint32_t | AFEC_CSELR |
| (Afec Offset: 0x64) AFEC Channel Selection Register | |
| __I uint32_t | AFEC_CDR |
| (Afec Offset: 0x68) AFEC Channel Data Register | |
| __IO uint32_t | AFEC_COCR |
| (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register | |
| __IO uint32_t | AFEC_TEMPMR |
| (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register | |
| __IO uint32_t | AFEC_TEMPCWR |
| (Afec Offset: 0x74) AFEC Temperature Compare Window Register | |
| __I uint32_t | Reserved3 [7] |
| __IO uint32_t | AFEC_ACR |
| (Afec Offset: 0x94) AFEC Analog Control Register | |
| __I uint32_t | Reserved4 [2] |
| __IO uint32_t | AFEC_SHMR |
| (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register | |
| __I uint32_t | Reserved5 [11] |
| __IO uint32_t | AFEC_COSR |
| (Afec Offset: 0xD0) AFEC Correction Select Register | |
| __IO uint32_t | AFEC_CVR |
| (Afec Offset: 0xD4) AFEC Correction Values Register | |
| __IO uint32_t | AFEC_CECR |
| (Afec Offset: 0xD8) AFEC Channel Error Correction Register | |
| __I uint32_t | Reserved6 [2] |
| __IO uint32_t | AFEC_WPMR |
| (Afec Offset: 0xE4) AFEC Write Protection Mode Register | |
| __I uint32_t | AFEC_WPSR |
| (Afec Offset: 0xE8) AFEC Write Protection Status Register | |
| __I uint32_t | Reserved7 [4] |
| __I uint32_t | AFEC_VERSION |
| (Afec Offset: 0xFC) AFEC Version Register | |
Afec hardware registers.
1.9.6