#include <alt_qspi.h>

Data Fields
ALT_QSPI_CLK_PHASE_t	clk_phase

ALT_QSPI_CLK_POLARITY_t	clk_pol

uint32_t	cs_da

uint32_t	cs_dads

uint32_t	cs_eot

uint32_t	cs_sot

uint32_t	rd_datacap

Detailed Description

QSPI Controller Timing Configuration

This type defines the structure used to configure timing paramaters used by the QSPI controller to communicate with a target flash device.

All timing values are defined in cycles of the SPI master ref clock.

Field Documentation

◆ clk_phase

ALT_QSPI_CLK_PHASE_t ALT_QSPI_TIMING_CONFIG_s::clk_phase

Selects whether the clock is in an active or inactive phase outside the SPI word.

◆ clk_pol

ALT_QSPI_CLK_POLARITY_t ALT_QSPI_TIMING_CONFIG_s::clk_pol

Selects whether the clock is quiescent low or high outside the SPI word.

◆ cs_da

uint32_t ALT_QSPI_TIMING_CONFIG_s::cs_da

Chip Select De-Assert. Added delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. If CSDA = X, then the chip select de-assert time will be: 1 sclk_out + 1 ref_clk + X ref_clks.

◆ cs_dads

uint32_t ALT_QSPI_TIMING_CONFIG_s::cs_dads

Chip Select De-Assert Different Slaves. Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves. CSDADS is only relevant when switching between 2 different external flash devices. If CSDADS = X, then the delay will be: 1 sclk_out + 3 ref_clks + X ref_clks.

◆ cs_eot

uint32_t ALT_QSPI_TIMING_CONFIG_s::cs_eot

Chip Select End Of Transfer. Delay in master reference clocks between last bit of current transaction and de-asserting the device chip select (n_ss_out). By default (when CSEOT=0), the chip select will be de-asserted on the last falling edge of sclk_out at the completion of the current transaction. If CSEOT = X, then chip selected will de-assert X ref_clks after the last falling edge of sclk_out.

◆ cs_sot

uint32_t ALT_QSPI_TIMING_CONFIG_s::cs_sot

Chip Select Start Of Transfer. Delay in master reference clocks between setting n_ss_out low and first bit transfer. By default (CSSOT=0), chip select will be asserted half a SCLK period before the first rising edge of sclk_out. If CSSOT = X, chip select will be asserted half an sclk_out period before the first rising edge of sclk_out + X ref_clks.

◆ rd_datacap

uint32_t ALT_QSPI_TIMING_CONFIG_s::rd_datacap

The additional number of read data capture cycles (ref_clk) that should be applied to the internal read data capture circuit. The large clock-to-out delay of the flash memory together with trace delays as well as other device delays may impose a maximum flash clock frequency which is less than the flash memory device itself can operate at. To compensate, software should set this register to a value that guarantees robust data captures.

The documentation for this struct was generated from the following file:

bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_qspi.h

Data Fields