RTEMS 6.1-rc5
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stm32h7xx_ll_swpmi.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_SWPMI_H
21#define STM32H7xx_LL_SWPMI_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42/* Private constants ---------------------------------------------------------*/
43/* Private macros ------------------------------------------------------------*/
44#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
52#endif /*USE_FULL_LL_DRIVER*/
53
54/* Exported types ------------------------------------------------------------*/
55#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
64typedef struct
65{
66 uint32_t VoltageClass;
71 uint32_t BitRatePrescaler;
78 uint32_t TxBufferingMode;
83 uint32_t RxBufferingMode;
87} LL_SWPMI_InitTypeDef;
88
92#endif /* USE_FULL_LL_DRIVER */
93
94/* Exported constants --------------------------------------------------------*/
105#define LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF
106#define LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF
107#define LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF
108#define LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF
109#define LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF
110#define LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF
111#define LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF
121#define LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF
122#define LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF
123#define LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF
124#define LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF
125#define LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF
126#define LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE
127#define LL_SWPMI_ISR_TXE SWPMI_ISR_TXE
128#define LL_SWPMI_ISR_TCF SWPMI_ISR_TCF
129#define LL_SWPMI_ISR_SRF SWPMI_ISR_SRF
130#define LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP
131#define LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF
141#define LL_SWPMI_IER_SRIE SWPMI_IER_SRIE
142#define LL_SWPMI_IER_TCIE SWPMI_IER_TCIE
143#define LL_SWPMI_IER_TIE SWPMI_IER_TIE
144#define LL_SWPMI_IER_RIE SWPMI_IER_RIE
145#define LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE
146#define LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE
147#define LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE
148#define LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE
149#define LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE
158#define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)
159#define LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE
168#define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)
169#define LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE
178#define LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
179#define LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS
188#define LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0
189#define LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1
198/* Exported macro ------------------------------------------------------------*/
216#define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
217
224#define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
241#define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
242
251/* Exported functions --------------------------------------------------------*/
272__STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
273{
274 MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode);
275}
276
285__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx)
286{
287 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));
288}
289
300__STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
301{
302 MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode);
303}
304
313__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx)
314{
315 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));
316}
317
324__STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
325{
326 SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
327}
328
335__STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
336{
337 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
338}
339
347__STATIC_INLINE void LL_SWPMI_EnableTransceiver(SWPMI_TypeDef *SWPMIx)
348{
349 SET_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);
350}
351
359__STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx)
360{
361 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);
362}
363
370__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef *SWPMIx)
371{
372 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPEN) == (SWPMI_CR_SWPEN)) ? 1UL : 0UL);
373}
374
385__STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
386{
387 /* In order to activate SWP again, the software must clear DEACT bit*/
388 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
389
390 /* Set SWACT bit */
391 SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
392}
393
400__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx)
401{
402 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL);
403}
404
412__STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
413{
414 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
415}
416
424__STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
425{
426 SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
427}
428
436__STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
437{
438 WRITE_REG(SWPMIx->BRR, BitRatePrescaler);
439}
440
447__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx)
448{
449 return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));
450}
451
461__STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
462{
463 MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass);
464}
465
474__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx)
475{
476 return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));
477}
478
494__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx)
495{
496 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL);
497}
498
505__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx)
506{
507 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL);
508}
509
516__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx)
517{
518 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL);
519}
520
527__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
528{
529 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL);
530}
531
538__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
539{
540 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL);
541}
542
550__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx)
551{
552 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL);
553}
554
562__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx)
563{
564 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL);
565}
566
574__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx)
575{
576 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL);
577}
578
586__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx)
587{
588 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL);
589}
590
597__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx)
598{
599 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL);
600}
601
608__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx)
609{
610 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL);
611}
612
619__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef *SWPMIx)
620{
621 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RDYF) == (SWPMI_ISR_RDYF)) ? 1UL : 0UL);
622}
623
630__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
631{
632 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);
633}
634
641__STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
642{
643 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);
644}
645
652__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
653{
654 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);
655}
656
663__STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
664{
665 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);
666}
667
674__STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
675{
676 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);
677}
678
685__STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
686{
687 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);
688}
689
696__STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
697{
698 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);
699}
700
707__STATIC_INLINE void LL_SWPMI_ClearFlag_RDY(SWPMI_TypeDef *SWPMIx)
708{
709 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRDYF);
710}
711
727__STATIC_INLINE void LL_SWPMI_EnableIT_RDY(SWPMI_TypeDef *SWPMIx)
728{
729 SET_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);
730}
731
738__STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
739{
740 SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
741}
742
749__STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
750{
751 SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
752}
753
760__STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
761{
762 SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);
763}
764
771__STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
772{
773 SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);
774}
775
782__STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
783{
784 SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
785}
786
793__STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
794{
795 SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
796}
797
804__STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
805{
806 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
807}
808
815__STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
816{
817 SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
818}
819
826__STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
827{
828 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
829}
830
837__STATIC_INLINE void LL_SWPMI_DisableIT_RDY(SWPMI_TypeDef *SWPMIx)
838{
839 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);
840}
841
848__STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
849{
850 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
851}
852
859__STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
860{
861 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
862}
863
870__STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
871{
872 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);
873}
874
881__STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
882{
883 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);
884}
885
892__STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
893{
894 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
895}
896
903__STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
904{
905 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
906}
907
914__STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
915{
916 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
917}
918
925__STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
926{
927 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
928}
929
936__STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
937{
938 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
939}
940
947__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx)
948{
949 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RDYIE) == (SWPMI_IER_RDYIE)) ? 1UL : 0UL);
950}
951
958__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx)
959{
960 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL);
961}
962
969__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx)
970{
971 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL);
972}
973
980__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx)
981{
982 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL);
983}
984
991__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx)
992{
993 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL);
994}
995
1002__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx)
1003{
1004 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL);
1005}
1006
1013__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx)
1014{
1015 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL);
1016}
1017
1024__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx)
1025{
1026 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL);
1027}
1028
1035__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx)
1036{
1037 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL);
1038}
1039
1046__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx)
1047{
1048 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL);
1049}
1050
1066__STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
1067{
1068 SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
1069}
1070
1077__STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
1078{
1079 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
1080}
1081
1088__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx)
1089{
1090 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL);
1091}
1092
1099__STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1100{
1101 SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
1102}
1103
1110__STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1111{
1112 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
1113}
1114
1121__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1122{
1123 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL);
1124}
1125
1136__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction)
1137{
1138 uint32_t data_reg_addr;
1139
1140 if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)
1141 {
1142 /* return address of TDR register */
1143 data_reg_addr = (uint32_t)&(SWPMIx->TDR);
1144 }
1145 else
1146 {
1147 /* return address of RDR register */
1148 data_reg_addr = (uint32_t)&(SWPMIx->RDR);
1149 }
1150
1151 return data_reg_addr;
1152}
1153
1169__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx)
1170{
1171 return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));
1172}
1173
1181__STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
1182{
1183 WRITE_REG(SWPMIx->TDR, TxData);
1184}
1185
1192__STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
1193{
1194 return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));
1195}
1196
1205__STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
1206{
1207 CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1208}
1209
1219__STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
1220{
1221 SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1222}
1223
1228#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
1234ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx);
1235ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1236void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1237
1241#endif /*USE_FULL_LL_DRIVER*/
1242
1256#ifdef __cplusplus
1257}
1258#endif
1259
1260#endif /* STM32H7xx_LL_SWPMI_H */
#define SWPMI_ICR_CRDYF
Definition: stm32h723xx.h:21438
#define SWPMI_OR_CLASS
Definition: stm32h723xx.h:21495
#define SWPMI_ISR_TCF
Definition: stm32h723xx.h:21400
#define SWPMI_RFL_RFL
Definition: stm32h723xx.h:21475
#define SWPMI_ISR_RXBERF
Definition: stm32h723xx.h:21385
#define SWPMI_IER_TXBEIE
Definition: stm32h723xx.h:21446
#define SWPMI_CR_RXMODE
Definition: stm32h723xx.h:21354
#define SWPMI_ISR_TXE
Definition: stm32h723xx.h:21397
#define SWPMI_IER_TIE
Definition: stm32h723xx.h:21461
#define SWPMI_IER_RDYIE
Definition: stm32h723xx.h:21470
#define SWPMI_ICR_CRXOVRF
Definition: stm32h723xx.h:21426
#define SWPMI_ICR_CTXBEF
Definition: stm32h723xx.h:21420
#define SWPMI_ISR_RXOVRF
Definition: stm32h723xx.h:21388
#define SWPMI_ICR_CSRF
Definition: stm32h723xx.h:21435
#define SWPMI_IER_RIE
Definition: stm32h723xx.h:21458
#define SWPMI_ISR_RXNE
Definition: stm32h723xx.h:21394
#define SWPMI_IER_TXUNRIE
Definition: stm32h723xx.h:21455
#define SWPMI_CR_RXDMA
Definition: stm32h723xx.h:21348
#define SWPMI_ISR_RDYF
Definition: stm32h723xx.h:21412
#define SWPMI_IER_TCIE
Definition: stm32h723xx.h:21464
#define SWPMI_ICR_CTCF
Definition: stm32h723xx.h:21432
#define SWPMI_ISR_DEACTF
Definition: stm32h723xx.h:21409
#define SWPMI_IER_RXBFIE
Definition: stm32h723xx.h:21443
#define SWPMI_CR_DEACT
Definition: stm32h723xx.h:21366
#define SWPMI_ISR_TXBEF
Definition: stm32h723xx.h:21382
#define SWPMI_BRR_BR
Definition: stm32h723xx.h:21374
#define SWPMI_RDR_RD
Definition: stm32h723xx.h:21486
#define SWPMI_IER_RXBERIE
Definition: stm32h723xx.h:21449
#define SWPMI_IER_RXOVRIE
Definition: stm32h723xx.h:21452
#define SWPMI_OR_TBYP
Definition: stm32h723xx.h:21492
#define SWPMI_ISR_RXBFF
Definition: stm32h723xx.h:21379
#define SWPMI_CR_LPBK
Definition: stm32h723xx.h:21360
#define SWPMI_ICR_CRXBERF
Definition: stm32h723xx.h:21423
#define SWPMI_CR_SWPEN
Definition: stm32h723xx.h:21369
#define SWPMI_CR_TXDMA
Definition: stm32h723xx.h:21351
#define SWPMI_ICR_CRXBFF
Definition: stm32h723xx.h:21417
#define SWPMI_CR_SWPACT
Definition: stm32h723xx.h:21363
#define SWPMI_ISR_SUSP
Definition: stm32h723xx.h:21406
#define SWPMI_ISR_SRF
Definition: stm32h723xx.h:21403
#define SWPMI_ICR_CTXUNRF
Definition: stm32h723xx.h:21429
#define SWPMI_ISR_TXUNRF
Definition: stm32h723xx.h:21391
#define SWPMI_IER_SRIE
Definition: stm32h723xx.h:21467
#define SWPMI_CR_TXMODE
Definition: stm32h723xx.h:21357
#define LL_SWPMI_DMA_REG_DATA_TRANSMIT
Definition: stm32h7xx_ll_swpmi.h:188
__STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
Set SWP Voltage Class @rmtoll OR CLASS LL_SWPMI_SetVoltageClass.
Definition: stm32h7xx_ll_swpmi.h:461
__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx)
Get Bitrate prescaler @rmtoll BRR BR LL_SWPMI_GetBitRatePrescaler.
Definition: stm32h7xx_ll_swpmi.h:447
__STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx)
Disable SWPMI transceiver.
Definition: stm32h7xx_ll_swpmi.h:359
__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx)
Get Transmission buffering mode @rmtoll CR TXMODE LL_SWPMI_GetTransmissionMode.
Definition: stm32h7xx_ll_swpmi.h:313
__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx)
Get SWP Voltage Class @rmtoll OR CLASS LL_SWPMI_GetVoltageClass.
Definition: stm32h7xx_ll_swpmi.h:474
__STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4) @rmtoll BRR BR LL_SWPMI_SetBitRa...
Definition: stm32h7xx_ll_swpmi.h:436
__STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED state if no resume f...
Definition: stm32h7xx_ll_swpmi.h:424
__STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
Set Transmission buffering mode.
Definition: stm32h7xx_ll_swpmi.h:300
__STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
Deactivate immediately Single wire protocol bus (immediate transition to DEACTIVATED state) @rmtoll C...
Definition: stm32h7xx_ll_swpmi.h:412
__STATIC_INLINE void LL_SWPMI_EnableTransceiver(SWPMI_TypeDef *SWPMIx)
Enable SWPMI transceiver.
Definition: stm32h7xx_ll_swpmi.h:347
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef *SWPMIx)
Check if SWPMI transceiver is enabled @rmtoll CR SWPEN LL_SWPMI_IsEnabledTransceiver.
Definition: stm32h7xx_ll_swpmi.h:370
__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx)
Get Reception buffering mode @rmtoll CR RXMODE LL_SWPMI_GetReceptionMode.
Definition: stm32h7xx_ll_swpmi.h:285
__STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
Set Reception buffering mode.
Definition: stm32h7xx_ll_swpmi.h:272
__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx)
Check if Single wire protocol bus is in ACTIVATED state. @rmtoll CR SWPACT LL_SWPMI_Activate.
Definition: stm32h7xx_ll_swpmi.h:400
__STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
Definition: stm32h7xx_ll_swpmi.h:385
__STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
Enable loopback mode @rmtoll CR LPBK LL_SWPMI_EnableLoopback.
Definition: stm32h7xx_ll_swpmi.h:324
__STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
Disable loopback mode @rmtoll CR LPBK LL_SWPMI_DisableLoopback.
Definition: stm32h7xx_ll_swpmi.h:335
__STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
Enable DMA mode for reception @rmtoll CR RXDMA LL_SWPMI_EnableDMAReq_RX.
Definition: stm32h7xx_ll_swpmi.h:1066
__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction)
Get the data register address used for DMA transfer @rmtoll TDR TD LL_SWPMI_DMA_GetRegAddr RDR RD LL...
Definition: stm32h7xx_ll_swpmi.h:1136
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx)
Check if DMA mode for reception is enabled @rmtoll CR RXDMA LL_SWPMI_IsEnabledDMAReq_RX.
Definition: stm32h7xx_ll_swpmi.h:1088
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx)
Check if DMA mode for transmission is enabled @rmtoll CR TXDMA LL_SWPMI_IsEnabledDMAReq_TX.
Definition: stm32h7xx_ll_swpmi.h:1121
__STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
Disable DMA mode for transmission @rmtoll CR TXDMA LL_SWPMI_DisableDMAReq_TX.
Definition: stm32h7xx_ll_swpmi.h:1110
__STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
Enable DMA mode for transmission @rmtoll CR TXDMA LL_SWPMI_EnableDMAReq_TX.
Definition: stm32h7xx_ll_swpmi.h:1099
__STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
Disable DMA mode for reception @rmtoll CR RXDMA LL_SWPMI_DisableDMAReq_RX.
Definition: stm32h7xx_ll_swpmi.h:1077
__STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
Disable SWP Transceiver Bypass.
Definition: stm32h7xx_ll_swpmi.h:1219
__STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
Receive Data Register @rmtoll RDR RD LL_SWPMI_ReceiveData32.
Definition: stm32h7xx_ll_swpmi.h:1192
__STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
Enable SWP Transceiver Bypass.
Definition: stm32h7xx_ll_swpmi.h:1205
__STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
Transmit Data Register @rmtoll TDR TD LL_SWPMI_TransmitData32.
Definition: stm32h7xx_ll_swpmi.h:1181
__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx)
Retrieve number of data bytes present in payload of received frame @rmtoll RFL RFL LL_SWPMI_GetReceiv...
Definition: stm32h7xx_ll_swpmi.h:1169
__STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
Clear transfer complete flag @rmtoll ICR CTCF LL_SWPMI_ClearFlag_TC.
Definition: stm32h7xx_ll_swpmi.h:685
__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
Clear receive CRC error flag @rmtoll ICR CRXBERF LL_SWPMI_ClearFlag_RXBER.
Definition: stm32h7xx_ll_swpmi.h:652
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx)
Check if CRC error in reception has been detected @rmtoll ISR RXBERF LL_SWPMI_IsActiveFlag_RXBER.
Definition: stm32h7xx_ll_swpmi.h:516
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
Check if Overrun in reception has been detected @rmtoll ISR RXOVRF LL_SWPMI_IsActiveFlag_RXOVR.
Definition: stm32h7xx_ll_swpmi.h:527
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx)
Check if Transmit data register is empty (it means that Data written in transmit data register SWPMI_...
Definition: stm32h7xx_ll_swpmi.h:562
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
Check if underrun error in transmission has been detected @rmtoll ISR TXUNRF LL_SWPMI_IsActiveFlag_TX...
Definition: stm32h7xx_ll_swpmi.h:538
__STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
Clear transmit buffer empty flag @rmtoll ICR CTXBEF LL_SWPMI_ClearFlag_TXBE.
Definition: stm32h7xx_ll_swpmi.h:641
__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
Clear receive buffer full flag @rmtoll ICR CRXBFF LL_SWPMI_ClearFlag_RXBF.
Definition: stm32h7xx_ll_swpmi.h:630
__STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
Clear receive overrun error flag @rmtoll ICR CRXOVRF LL_SWPMI_ClearFlag_RXOVR.
Definition: stm32h7xx_ll_swpmi.h:663
__STATIC_INLINE void LL_SWPMI_ClearFlag_RDY(SWPMI_TypeDef *SWPMIx)
Clear SWPMI transceiver ready flag @rmtoll ISR CRDYF LL_SWPMI_ClearFlag_RDY.
Definition: stm32h7xx_ll_swpmi.h:707
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx)
Check if SWP bus is in DEACTIVATED state @rmtoll ISR DEACTF LL_SWPMI_IsActiveFlag_DEACT.
Definition: stm32h7xx_ll_swpmi.h:608
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx)
Check if Both transmission and reception are completed and SWP is switched to the SUSPENDED state @rm...
Definition: stm32h7xx_ll_swpmi.h:574
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx)
Check if Frame transmission buffer has been emptied @rmtoll ISR TXBEF LL_SWPMI_IsActiveFlag_TXBE.
Definition: stm32h7xx_ll_swpmi.h:505
__STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
Clear transmit underrun error flag @rmtoll ICR CTXUNRF LL_SWPMI_ClearFlag_TXUNR.
Definition: stm32h7xx_ll_swpmi.h:674
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx)
Check if SWP bus is in SUSPENDED or DEACTIVATED state @rmtoll ISR SUSP LL_SWPMI_IsActiveFlag_SUSP.
Definition: stm32h7xx_ll_swpmi.h:597
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx)
Check if Receive data register not empty (it means that Received data is ready to be read in the SWPM...
Definition: stm32h7xx_ll_swpmi.h:550
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef *SWPMIx)
Check if SWPMI transceiver is ready @rmtoll ISR RDYF LL_SWPMI_IsActiveFlag_RDYF.
Definition: stm32h7xx_ll_swpmi.h:619
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx)
Check if the last word of the frame under reception has arrived in SWPMI_RDR. @rmtoll ISR RXBFF LL_SW...
Definition: stm32h7xx_ll_swpmi.h:494
__STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
Clear slave resume flag @rmtoll ICR CSRF LL_SWPMI_ClearFlag_SR.
Definition: stm32h7xx_ll_swpmi.h:696
__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx)
Check if a Resume by slave state has been detected during the SWP bus SUSPENDED state @rmtoll ISR SRF...
Definition: stm32h7xx_ll_swpmi.h:586
__STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
Enable Transmit underrun error interrupt @rmtoll IER TXUNRIE LL_SWPMI_EnableIT_TXUNR.
Definition: stm32h7xx_ll_swpmi.h:782
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx)
Check if Receive overrun error interrupt is enabled @rmtoll IER RXOVRIE LL_SWPMI_IsEnabledIT_RXOVR.
Definition: stm32h7xx_ll_swpmi.h:1013
__STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
Enable Receive CRC error interrupt @rmtoll IER RXBERIE LL_SWPMI_EnableIT_RXBER.
Definition: stm32h7xx_ll_swpmi.h:804
__STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
Enable Transmit buffer empty interrupt @rmtoll IER TXBEIE LL_SWPMI_EnableIT_TXBE.
Definition: stm32h7xx_ll_swpmi.h:815
__STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
Disable Receive buffer full interrupt @rmtoll IER RXBFIE LL_SWPMI_DisableIT_RXBF.
Definition: stm32h7xx_ll_swpmi.h:936
__STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
Disable Slave resume interrupt @rmtoll IER SRIE LL_SWPMI_DisableIT_SR.
Definition: stm32h7xx_ll_swpmi.h:848
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx)
Check if Receive buffer full interrupt is enabled @rmtoll IER RXBFIE LL_SWPMI_IsEnabledIT_RXBF.
Definition: stm32h7xx_ll_swpmi.h:1046
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx)
Check if SWPMI transceiver ready interrupt is enabled @rmtoll IER RDYIE LL_SWPMI_IsEnabledIT_RDY.
Definition: stm32h7xx_ll_swpmi.h:947
__STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
Disable Transmit buffer empty interrupt @rmtoll IER TXBEIE LL_SWPMI_DisableIT_TXBE.
Definition: stm32h7xx_ll_swpmi.h:925
__STATIC_INLINE void LL_SWPMI_EnableIT_RDY(SWPMI_TypeDef *SWPMIx)
Enable SWPMI transceiver ready interrupt @rmtoll IER RDYIE LL_SWPMI_EnableIT_RDY.
Definition: stm32h7xx_ll_swpmi.h:727
__STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
Enable Receive overrun error interrupt @rmtoll IER RXOVRIE LL_SWPMI_EnableIT_RXOVR.
Definition: stm32h7xx_ll_swpmi.h:793
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx)
Check if Receive CRC error interrupt is enabled @rmtoll IER RXBERIE LL_SWPMI_IsEnabledIT_RXBER.
Definition: stm32h7xx_ll_swpmi.h:1024
__STATIC_INLINE void LL_SWPMI_DisableIT_RDY(SWPMI_TypeDef *SWPMIx)
Disable SWPMI transceiver ready interrupt @rmtoll IER RDYIE LL_SWPMI_DisableIT_RDY.
Definition: stm32h7xx_ll_swpmi.h:837
__STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
Enable Receive interrupt @rmtoll IER RIE LL_SWPMI_EnableIT_RX.
Definition: stm32h7xx_ll_swpmi.h:771
__STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
Disable Transmit complete interrupt @rmtoll IER TCIE LL_SWPMI_DisableIT_TC.
Definition: stm32h7xx_ll_swpmi.h:859
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx)
Check if Transmit underrun error interrupt is enabled @rmtoll IER TXUNRIE LL_SWPMI_IsEnabledIT_TXUNR.
Definition: stm32h7xx_ll_swpmi.h:1002
__STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
Disable Transmit underrun error interrupt @rmtoll IER TXUNRIE LL_SWPMI_DisableIT_TXUNR.
Definition: stm32h7xx_ll_swpmi.h:892
__STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
Enable Transmit complete interrupt @rmtoll IER TCIE LL_SWPMI_EnableIT_TC.
Definition: stm32h7xx_ll_swpmi.h:749
__STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
Disable Receive overrun error interrupt @rmtoll IER RXOVRIE LL_SWPMI_DisableIT_RXOVR.
Definition: stm32h7xx_ll_swpmi.h:903
__STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
Enable Slave resume interrupt @rmtoll IER SRIE LL_SWPMI_EnableIT_SR.
Definition: stm32h7xx_ll_swpmi.h:738
__STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
Disable Receive CRC error interrupt @rmtoll IER RXBERIE LL_SWPMI_DisableIT_RXBER.
Definition: stm32h7xx_ll_swpmi.h:914
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx)
Check if Receive interrupt is enabled @rmtoll IER RIE LL_SWPMI_IsEnabledIT_RX.
Definition: stm32h7xx_ll_swpmi.h:991
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx)
Check if Transmit interrupt is enabled @rmtoll IER TIE LL_SWPMI_IsEnabledIT_TX.
Definition: stm32h7xx_ll_swpmi.h:980
__STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
Enable Transmit interrupt @rmtoll IER TIE LL_SWPMI_EnableIT_TX.
Definition: stm32h7xx_ll_swpmi.h:760
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx)
Check if Slave resume interrupt is enabled @rmtoll IER SRIE LL_SWPMI_IsEnabledIT_SR.
Definition: stm32h7xx_ll_swpmi.h:958
__STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
Disable Receive interrupt @rmtoll IER RIE LL_SWPMI_DisableIT_RX.
Definition: stm32h7xx_ll_swpmi.h:881
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx)
Check if Transmit buffer empty interrupt is enabled @rmtoll IER TXBEIE LL_SWPMI_IsEnabledIT_TXBE.
Definition: stm32h7xx_ll_swpmi.h:1035
__STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
Disable Transmit interrupt @rmtoll IER TIE LL_SWPMI_DisableIT_TX.
Definition: stm32h7xx_ll_swpmi.h:870
__STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
Enable Receive buffer full interrupt @rmtoll IER RXBFIE LL_SWPMI_EnableIT_RXBF.
Definition: stm32h7xx_ll_swpmi.h:826
__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx)
Check if Transmit complete interrupt is enabled @rmtoll IER TCIE LL_SWPMI_IsEnabledIT_TC.
Definition: stm32h7xx_ll_swpmi.h:969
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
Single Wire Protocol Master Interface SPWMI.
Definition: stm32h723xx.h:1615
__IO uint32_t RFL
Definition: stm32h723xx.h:1622
__IO uint32_t BRR
Definition: stm32h723xx.h:1617
__IO uint32_t RDR
Definition: stm32h723xx.h:1624
__IO uint32_t TDR
Definition: stm32h723xx.h:1623
__IO uint32_t ISR
Definition: stm32h723xx.h:1619
__IO uint32_t OR
Definition: stm32h723xx.h:1625
__IO uint32_t IER
Definition: stm32h723xx.h:1621
__IO uint32_t CR
Definition: stm32h723xx.h:1616
__IO uint32_t ICR
Definition: stm32h723xx.h:1620