RTEMS 6.1-rc5
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stm32h7xx_ll_rtc.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_RTC_H
21#define STM32H7xx_LL_RTC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
34#if defined(RTC)
35
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43/* Private constants ---------------------------------------------------------*/
48/* Masks Definition */
49#define RTC_LL_INIT_MASK 0xFFFFFFFFU
50#define RTC_LL_RSF_MASK 0xFFFFFF5FU
51
52/* Write protection defines */
53#define RTC_WRITE_PROTECTION_DISABLE 0xFFU
54#define RTC_WRITE_PROTECTION_ENABLE_1 0xCAU
55#define RTC_WRITE_PROTECTION_ENABLE_2 0x53U
56
57/* Defines used to combine date & time */
58#define RTC_OFFSET_WEEKDAY 24U
59#define RTC_OFFSET_DAY 16U
60#define RTC_OFFSET_MONTH 8U
61#define RTC_OFFSET_HOUR 16U
62#define RTC_OFFSET_MINUTE 8U
63
68/* Private macros ------------------------------------------------------------*/
69#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
77#endif /*USE_FULL_LL_DRIVER*/
78
79/* Exported types ------------------------------------------------------------*/
80#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
89typedef struct
90{
91 uint32_t HourFormat;
97 uint32_t AsynchPrescaler;
103 uint32_t SynchPrescaler;
108} LL_RTC_InitTypeDef;
109
113typedef struct
114{
115 uint32_t TimeFormat;
120 uint8_t Hours;
126 uint8_t Minutes;
131 uint8_t Seconds;
135} LL_RTC_TimeTypeDef;
136
140typedef struct
141{
142 uint8_t WeekDay;
147 uint8_t Month;
152 uint8_t Day;
157 uint8_t Year;
161} LL_RTC_DateTypeDef;
162
166typedef struct
167{
168 LL_RTC_TimeTypeDef AlarmTime;
170 uint32_t AlarmMask;
177 uint32_t AlarmDateWeekDaySel;
184 uint8_t AlarmDateWeekDay;
195} LL_RTC_AlarmTypeDef;
196
200#endif /* USE_FULL_LL_DRIVER */
201
202/* Exported constants --------------------------------------------------------*/
208#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
213#define LL_RTC_FORMAT_BIN 0x00000000U
214#define LL_RTC_FORMAT_BCD 0x00000001U
223#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U
224#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
233#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U
234#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL
239#endif /* USE_FULL_LL_DRIVER */
240
246#if defined(TAMP)
247#define LL_RTC_SCR_ITSF RTC_SCR_CITSF
248#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
249#define LL_RTC_SCR_TSF RTC_SCR_CTSF
250#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF
251#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
252#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF
253
254#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
255#define LL_RTC_ICSR_INITF RTC_ICSR_INITF
256#define LL_RTC_ICSR_RSF RTC_ICSR_RSF
257#define LL_RTC_ICSR_INITS RTC_ICSR_INITS
258#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
259#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF
260#else
261#define LL_RTC_ISR_ITSF RTC_ISR_ITSF
262#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
263#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
264#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
265#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
266#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
267#define LL_RTC_ISR_TSF RTC_ISR_TSF
268#define LL_RTC_ISR_WUTF RTC_ISR_WUTF
269#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
270#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
271#define LL_RTC_ISR_INITF RTC_ISR_INITF
272#define LL_RTC_ISR_RSF RTC_ISR_RSF
273#define LL_RTC_ISR_INITS RTC_ISR_INITS
274#define LL_RTC_ISR_SHPF RTC_ISR_SHPF
275#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
276#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
277#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF
278#endif /* TAMP */
288#define LL_RTC_CR_TSIE RTC_CR_TSIE
289#define LL_RTC_CR_WUTIE RTC_CR_WUTIE
290#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
291#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
292#if !defined(TAMP)
293#define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE
294#define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE
295#define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE
296#define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE
297#endif /* !TAMP */
306#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01
307#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02
308#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03
309#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04
310#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05
311#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06
312#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07
321#define LL_RTC_MONTH_JANUARY (uint8_t)0x01
322#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02
323#define LL_RTC_MONTH_MARCH (uint8_t)0x03
324#define LL_RTC_MONTH_APRIL (uint8_t)0x04
325#define LL_RTC_MONTH_MAY (uint8_t)0x05
326#define LL_RTC_MONTH_JUNE (uint8_t)0x06
327#define LL_RTC_MONTH_JULY (uint8_t)0x07
328#define LL_RTC_MONTH_AUGUST (uint8_t)0x08
329#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09
330#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10
331#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11
332#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12
341#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U
342#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT
351#define LL_RTC_ALARMOUT_DISABLE 0x00000000U
352#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0
353#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1
354#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL
363#if defined(TAMP)
364#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
365#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U
366#else
367#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U
368#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE
369#endif /* TAMP */
378#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U
379#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL
388#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U
389#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM
398#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
399#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
408#define LL_RTC_ALMA_MASK_NONE 0x00000000U
409#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4
410#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3
411#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2
412#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1
413#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)
422#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U
423#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM
432#define LL_RTC_ALMB_MASK_NONE 0x00000000U
433#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4
434#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3
435#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2
436#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1
437#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)
446#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U
447#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM
456#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U
457#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE
466#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U
467#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM
472#if defined(TAMP)
477#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E
478#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E
479#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E
488#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK
489#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK
490#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK
499#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE
500#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE
501#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE
510#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
511#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0
512#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1
513#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH
522#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
523#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0
524#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1
525#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT
534#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
535#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0
536#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1
537#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0)
538#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2
539#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0)
540#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1)
541#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ
550#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG
551#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG
552#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG
556#else
561#define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E
562#define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E
563#define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E
572#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF
573#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF
574#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF
583#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE
584#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE
585#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE
594#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U
595#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0
596#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1
597#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH
606#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U
607#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0
608#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1
609#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT
618#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U
619#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0
620#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1
621#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0)
622#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2
623#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0)
624#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1)
625#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ
634#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG
635#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG
636#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG
640#endif /* TAMP */
641
642#if defined(TAMP)
647#define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM
648#define LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM
649#define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM
658#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U
659#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0
660#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1
661#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
662#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2
663#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)
664#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)
665#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)
674#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL1_Pos)
675#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL1_Pos)
676#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL1_Pos)
677
678#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL2_Pos)
679#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL2_Pos)
680#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL2_Pos)
681
682#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL3_Pos)
683#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL3_Pos)
684#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL3_Pos)
688#endif /* TAMP */
689
694#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U
695#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0
696#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1
697#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0)
698#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2
699#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1)
708#define LL_RTC_BKP_DR0 0x00000000U
709#define LL_RTC_BKP_DR1 0x00000001U
710#define LL_RTC_BKP_DR2 0x00000002U
711#define LL_RTC_BKP_DR3 0x00000003U
712#define LL_RTC_BKP_DR4 0x00000004U
713#define LL_RTC_BKP_DR5 0x00000005U
714#define LL_RTC_BKP_DR6 0x00000006U
715#define LL_RTC_BKP_DR7 0x00000007U
716#define LL_RTC_BKP_DR8 0x00000008U
717#define LL_RTC_BKP_DR9 0x00000009U
718#define LL_RTC_BKP_DR10 0x0000000AU
719#define LL_RTC_BKP_DR11 0x0000000BU
720#define LL_RTC_BKP_DR12 0x0000000CU
721#define LL_RTC_BKP_DR13 0x0000000DU
722#define LL_RTC_BKP_DR14 0x0000000EU
723#define LL_RTC_BKP_DR15 0x0000000FU
724#define LL_RTC_BKP_DR16 0x00000010U
725#define LL_RTC_BKP_DR17 0x00000011U
726#define LL_RTC_BKP_DR18 0x00000012U
727#define LL_RTC_BKP_DR19 0x00000013U
728#define LL_RTC_BKP_DR20 0x00000014U
729#define LL_RTC_BKP_DR21 0x00000015U
730#define LL_RTC_BKP_DR22 0x00000016U
731#define LL_RTC_BKP_DR23 0x00000017U
732#define LL_RTC_BKP_DR24 0x00000018U
733#define LL_RTC_BKP_DR25 0x00000019U
734#define LL_RTC_BKP_DR26 0x0000001AU
735#define LL_RTC_BKP_DR27 0x0000001BU
736#define LL_RTC_BKP_DR28 0x0000001CU
737#define LL_RTC_BKP_DR29 0x0000001DU
738#define LL_RTC_BKP_DR30 0x0000001EU
739#define LL_RTC_BKP_DR31 0x0000001FU
748#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U
749#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL)
750#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE
759#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U
760#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP
769#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U
770#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16
771#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8
780/* Exported macro ------------------------------------------------------------*/
798#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, __VALUE__)
799
806#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
821#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
822
828#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U) + ((__VALUE__) & (uint8_t)0x0F)))
829
851#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
852
858#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
859
877#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
878
884#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
885
900#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
901
907#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
908
914#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
915
924/* Exported functions --------------------------------------------------------*/
946__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
947{
948 MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
949}
950
959__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
960{
961 return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
962}
963
976__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
977{
978 MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
979}
980
991__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
992{
993 return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
994}
995
996#if defined(TAMP)
1006__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
1007{
1008 MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output);
1009}
1010
1019__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
1020{
1021 return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE));
1022}
1023#else
1034__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
1035{
1036 MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output);
1037}
1038
1048__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
1049{
1050 return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE));
1051}
1052#endif /* TAMP */
1053
1054#if defined(TAMP)
1064__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
1065{
1066 /* Set the Initialization mode */
1067 WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK);
1068}
1069
1076__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
1077{
1078 /* Exit Initialization mode */
1079 WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT);
1080}
1081
1082#else
1092__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
1093{
1094 /* Set the Initialization mode */
1095 WRITE_REG(RTCx->ISR, RTC_LL_INIT_MASK);
1096}
1097
1104__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
1105{
1106 /* Exit Initialization mode */
1107 WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
1108}
1109#endif /* TAMP */
1110
1121__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
1122{
1123 MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
1124}
1125
1134__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
1135{
1136 return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
1137}
1138
1146__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
1147{
1148 SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
1149}
1150
1157__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
1158{
1159 CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
1160}
1161
1168__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
1169{
1170 return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL);
1171}
1172
1181__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
1182{
1183 SET_BIT(RTCx->CR, RTC_CR_REFCKON);
1184}
1185
1194__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
1195{
1196 CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
1197}
1198
1206__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
1207{
1208 MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
1209}
1210
1218__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
1219{
1220 MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
1221}
1222
1229__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
1230{
1231 return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
1232}
1233
1240__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
1241{
1242 return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
1243}
1244
1251__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
1252{
1253 WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
1254}
1255
1262__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
1263{
1264 WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
1265 WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
1266}
1267
1268#if defined(TAMP)
1277__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx)
1278{
1279 SET_BIT(RTCx->CR, RTC_CR_TAMPOE);
1280}
1281
1288__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx)
1289{
1290 CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE);
1291}
1292
1299__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx)
1300{
1301 return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1UL : 0UL);
1302}
1303
1310__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx)
1311{
1312 SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
1313}
1314
1321__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx)
1322{
1323 CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
1324}
1325
1332__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx)
1333{
1334 return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1UL : 0UL);
1335}
1336
1346__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx)
1347{
1348 SET_BIT(RTCx->CR, RTC_CR_OUT2EN);
1349}
1350
1357__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx)
1358{
1359 CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN);
1360}
1361
1368__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx)
1369{
1370 return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1UL : 0UL);
1371}
1372#else
1379__STATIC_INLINE void LL_RTC_EnableOutRemap(RTC_TypeDef *RTCx)
1380{
1381 SET_BIT(RTCx->OR, RTC_OR_OUT_RMP);
1382}
1383
1390__STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx)
1391{
1392 CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP);
1393}
1394#endif /* TAMP */
1395
1416__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
1417{
1418 MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
1419}
1420
1433__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
1434{
1435 return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
1436}
1437
1449__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
1450{
1451 MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
1452 (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
1453}
1454
1468__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
1469{
1470 return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
1471}
1472
1484__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
1485{
1486 MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
1487 (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
1488}
1489
1503__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
1504{
1505 return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
1506}
1507
1519__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
1520{
1521 MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
1522 (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
1523}
1524
1538__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
1539{
1540 return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
1541}
1542
1564__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
1565{
1566 uint32_t temp;
1567
1568 temp = Format12_24 | \
1569 (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
1570 (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
1571 (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
1572 MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
1573}
1574
1592__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
1593{
1594 uint32_t temp;
1595
1596 temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
1597 return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
1598 (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
1599 ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
1600}
1601
1609__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
1610{
1611 SET_BIT(RTCx->CR, RTC_CR_BKP);
1612}
1613
1621__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
1622{
1623 CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
1624}
1625
1632__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
1633{
1634 return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL);
1635}
1636
1644__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
1645{
1646 SET_BIT(RTCx->CR, RTC_CR_SUB1H);
1647}
1648
1656__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
1657{
1658 SET_BIT(RTCx->CR, RTC_CR_ADD1H);
1659}
1660
1674__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
1675{
1676 return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
1677}
1678
1693__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
1694{
1695 WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
1696}
1697
1716__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
1717{
1718 MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
1719 (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
1720}
1721
1732__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
1733{
1734 return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
1735}
1736
1751__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
1752{
1753 MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
1754}
1755
1771__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
1772{
1773 return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
1774}
1775
1797__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
1798{
1799 MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
1800 (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
1801}
1802
1825__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
1826{
1827 return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
1828}
1829
1839__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
1840{
1841 MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
1842 (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
1843}
1844
1855__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
1856{
1857 return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
1858}
1859
1895__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
1896{
1897 uint32_t temp;
1898
1899 temp = (WeekDay << RTC_DR_WDU_Pos) | \
1900 (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
1901 (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
1902 (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
1903
1904 MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
1905}
1906
1923__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
1924{
1925 uint32_t temp;
1926
1927 temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
1928 return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
1929 (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
1930 (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
1931 ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
1932}
1933
1950__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
1951{
1952 SET_BIT(RTCx->CR, RTC_CR_ALRAE);
1953}
1954
1962__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
1963{
1964 CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
1965}
1966
1983__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
1984{
1985 MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
1986}
1987
2003__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
2004{
2005 return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
2006}
2007
2014__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
2015{
2016 SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
2017}
2018
2025__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
2026{
2027 CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
2028}
2029
2039__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
2040{
2041 MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
2042 (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
2043}
2044
2053__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
2054{
2055 return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
2056}
2057
2072__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
2073{
2074 MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
2075}
2076
2090__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
2091{
2092 return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
2093}
2094
2104__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
2105{
2106 MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
2107}
2108
2117__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
2118{
2119 return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
2120}
2121
2131__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
2132{
2133 MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
2134 (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
2135}
2136
2145__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
2146{
2147 return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
2148}
2149
2159__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
2160{
2161 MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
2162 (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
2163}
2164
2173__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
2174{
2175 return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
2176}
2177
2187__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
2188{
2189 MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
2190 (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
2191}
2192
2201__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
2202{
2203 return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
2204}
2205
2224__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
2225{
2226 uint32_t temp;
2227
2228 temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
2229 (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
2230 (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
2231
2232 MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
2233}
2234
2248__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
2249{
2250 return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
2251}
2252
2262__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
2263{
2264 MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
2265}
2266
2273__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
2274{
2275 return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
2276}
2277
2285__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
2286{
2287 MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
2288}
2289
2296__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
2297{
2298 return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
2299}
2300
2317__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
2318{
2319 SET_BIT(RTCx->CR, RTC_CR_ALRBE);
2320}
2321
2329__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
2330{
2331 CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
2332}
2333
2350__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
2351{
2352 MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
2353}
2354
2370__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
2371{
2372 return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
2373}
2374
2381__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
2382{
2383 SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
2384}
2385
2392__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
2393{
2394 CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
2395}
2396
2406__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
2407{
2408 MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
2409 (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
2410}
2411
2420__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
2421{
2422 return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
2423}
2424
2439__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
2440{
2441 MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
2442}
2443
2457__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
2458{
2459 return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
2460}
2461
2471__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
2472{
2473 MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
2474}
2475
2484__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
2485{
2486 return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
2487}
2488
2498__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
2499{
2500 MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
2501 (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
2502}
2503
2512__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
2513{
2514 return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
2515}
2516
2526__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
2527{
2528 MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
2529 (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
2530}
2531
2540__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
2541{
2542 return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
2543}
2544
2554__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
2555{
2556 MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
2557 (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
2558}
2559
2568__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
2569{
2570 return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
2571}
2572
2591__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
2592{
2593 uint32_t temp;
2594
2595 temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
2596 (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
2597 (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
2598
2599 MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
2600}
2601
2615__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
2616{
2617 return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
2618}
2619
2629__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
2630{
2631 MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
2632}
2633
2640__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
2641{
2642 return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos);
2643}
2644
2652__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
2653{
2654 MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
2655}
2656
2663__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
2664{
2665 return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
2666}
2667
2684__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)
2685{
2686 SET_BIT(RTCx->CR, RTC_CR_ITSE);
2687}
2688
2696__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)
2697{
2698 CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);
2699}
2700
2708__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
2709{
2710 SET_BIT(RTCx->CR, RTC_CR_TSE);
2711}
2712
2720__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
2721{
2722 CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
2723}
2724
2736__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
2737{
2738 MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
2739}
2740
2750__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
2751{
2752 return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
2753}
2754
2763__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
2764{
2765 return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
2766}
2767
2776__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
2777{
2778 return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
2779}
2780
2789__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
2790{
2791 return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
2792}
2793
2802__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
2803{
2804 return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
2805}
2806
2820__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
2821{
2822 return (uint32_t)(READ_BIT(RTCx->TSTR,
2823 RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
2824}
2825
2839__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
2840{
2841 return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
2842}
2843
2864__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
2865{
2866 return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
2867}
2868
2877__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
2878{
2879 return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
2880}
2881
2894__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
2895{
2896 return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
2897}
2898
2905__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
2906{
2907 return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
2908}
2909
2919#if !defined(TAMP)
2926__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
2927{
2928 SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
2929}
2930
2937__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
2938{
2939 CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
2940}
2941#else
2949__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
2950{
2951 SET_BIT(RTCx->CR, RTC_CR_TAMPTS);
2952}
2953
2960__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
2961{
2962 CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS);
2963}
2964#endif /* !TAMP */
2965
2975#if !defined(TAMP)
2989__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
2990{
2991 SET_BIT(RTCx->TAMPCR, Tamper);
2992}
2993
3007__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
3008{
3009 CLEAR_BIT(RTCx->TAMPCR, Tamper);
3010}
3011
3026__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
3027{
3028 SET_BIT(RTCx->TAMPCR, Mask);
3029}
3030
3044__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
3045{
3046 CLEAR_BIT(RTCx->TAMPCR, Mask);
3047}
3048
3062__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
3063{
3064 CLEAR_BIT(RTCx->TAMPCR, Tamper);
3065}
3066
3080__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
3081{
3082 SET_BIT(RTCx->TAMPCR, Tamper);
3083}
3084
3091__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
3092{
3093 SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
3094}
3095
3102__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
3103{
3104 CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
3105}
3106
3118__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
3119{
3120 MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration);
3121}
3122
3133__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
3134{
3135 return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH));
3136}
3137
3149__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
3150{
3151 MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount);
3152}
3153
3164__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
3165{
3166 return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT));
3167}
3168
3184__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
3185{
3186 MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq);
3187}
3188
3203__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
3204{
3205 return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ));
3206}
3207
3221__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
3222{
3223 SET_BIT(RTCx->TAMPCR, Tamper);
3224}
3225
3239__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
3240{
3241 CLEAR_BIT(RTCx->TAMPCR, Tamper);
3242}
3243#endif /* !TAMP */
3244
3245#if defined(TAMP)
3259__STATIC_INLINE void LL_RTC_TAMPER_Enable(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3260{
3261 SET_BIT(TAMPx->CR1, Tamper);
3262}
3263
3277__STATIC_INLINE void LL_RTC_TAMPER_Disable(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3278{
3279 CLEAR_BIT(TAMPx->CR1, Tamper);
3280}
3281
3296__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(TAMP_TypeDef *TAMPx, uint32_t Mask)
3297{
3298 SET_BIT(TAMPx->CR2, Mask);
3299}
3300
3314__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(TAMP_TypeDef *TAMPx, uint32_t Mask)
3315{
3316 CLEAR_BIT(TAMPx->CR2, Mask);
3317}
3318
3332__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3333{
3334 CLEAR_BIT(TAMPx->CR2, Tamper);
3335}
3336
3350__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3351{
3352 SET_BIT(TAMPx->CR2, Tamper);
3353}
3354
3368__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3369{
3370 SET_BIT(TAMPx->CR2, Tamper);
3371}
3372
3386__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper)
3387{
3388 CLEAR_BIT(TAMPx->CR2, Tamper);
3389}
3390
3397__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(TAMP_TypeDef *TAMPx)
3398{
3399 SET_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS);
3400}
3401
3408__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(TAMP_TypeDef *TAMPx)
3409{
3410 CLEAR_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS);
3411}
3412
3424__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(TAMP_TypeDef *TAMPx, uint32_t Duration)
3425{
3426 MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration);
3427}
3428
3439__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(TAMP_TypeDef *TAMPx)
3440{
3441 return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH));
3442}
3443
3455__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(TAMP_TypeDef *TAMPx, uint32_t FilterCount)
3456{
3457 MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount);
3458}
3459
3470__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(TAMP_TypeDef *TAMPx)
3471{
3472 return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT));
3473}
3474
3490__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(TAMP_TypeDef *TAMPx, uint32_t SamplingFreq)
3491{
3492 MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq);
3493}
3494
3509__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef *TAMPx)
3510{
3511 return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ));
3512}
3513#endif /* TAMP */
3514
3531__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
3532{
3533 SET_BIT(RTCx->CR, RTC_CR_WUTE);
3534}
3535
3543__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
3544{
3545 CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
3546}
3547
3554__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
3555{
3556 return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL);
3557}
3558
3574__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
3575{
3576 MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
3577}
3578
3591__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
3592{
3593 return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
3594}
3595
3604__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
3605{
3606 MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
3607}
3608
3615__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
3616{
3617 return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
3618}
3619
3630#if !defined(TAMP)
3671__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
3672{
3673 uint32_t tmp;
3674
3675 tmp = (uint32_t)(&(RTCx->BKP0R));
3676 tmp += (BackupRegister * 4U);
3677
3678 /* Write the specified register */
3679 *(__IO uint32_t *)tmp = (uint32_t)Data;
3680}
3681
3721__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
3722{
3723 uint32_t tmp;
3724
3725 tmp = (uint32_t)(&(RTCx->BKP0R));
3726 tmp += (BackupRegister * 4U);
3727
3728 /* Read the specified register */
3729 return (*(__IO uint32_t *)tmp);
3730}
3731#else
3772__STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data)
3773{
3774 uint32_t tmp;
3775
3776 tmp = (uint32_t)(&(TAMPx->BKP0R));
3777 tmp += (BackupRegister * 4U);
3778
3779 /* Write the specified register */
3780 *(__IO uint32_t *)tmp = (uint32_t)Data;
3781}
3782
3822__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister)
3823{
3824 uint32_t tmp;
3825
3826 tmp = (uint32_t)(&(TAMPx->BKP0R));
3827 tmp += (BackupRegister * 4U);
3828
3829 /* Read the specified register */
3830 return (*(__IO uint32_t *)tmp);
3831}
3832#endif /* !TAMP */
3833
3856__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
3857{
3858 MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
3859}
3860
3871__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
3872{
3873 return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
3874}
3875
3887__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
3888{
3889 MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
3890}
3891
3898__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
3899{
3900 return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL);
3901}
3902
3916__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
3917{
3918 MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
3919}
3920
3931__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
3932{
3933 return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
3934}
3935
3945__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
3946{
3947 MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
3948}
3949
3956__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
3957{
3958 return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
3959}
3960
3971#if !defined(TAMP)
3978__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
3979{
3980 return ((READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL);
3981}
3982
3989__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
3990{
3991 return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL);
3992}
3993
4000__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
4001{
4002 return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL);
4003}
4004
4011__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
4012{
4013 return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL);
4014}
4015
4022__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
4023{
4024 return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL);
4025}
4026
4033__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
4034{
4035 return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL);
4036}
4037
4044__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
4045{
4046 return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL);
4047}
4048
4055__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
4056{
4057 return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL);
4058}
4059
4066__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
4067{
4068 return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL);
4069}
4070
4077__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
4078{
4079 return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL);
4080}
4081
4088__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
4089{
4090 WRITE_REG(RTCx->ISR, (~((RTC_ISR_ITSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
4091}
4092
4099__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
4100{
4101 WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
4102}
4103
4110__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
4111{
4112 WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
4113}
4114
4121__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
4122{
4123 WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
4124}
4125
4132__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
4133{
4134 WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
4135}
4136
4143__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
4144{
4145 WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
4146}
4147
4154__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
4155{
4156 WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
4157}
4158
4165__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
4166{
4167 WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
4168}
4169
4176__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
4177{
4178 WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
4179}
4180
4187__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
4188{
4189 return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL);
4190}
4191
4198__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
4199{
4200 return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL);
4201}
4202
4209__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
4210{
4211 WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
4212}
4213
4220__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
4221{
4222 return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL);
4223}
4224
4231__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
4232{
4233 return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL);
4234}
4235
4242__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
4243{
4244 return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL);
4245}
4246
4253__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
4254{
4255 return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL);
4256}
4257
4264__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
4265{
4266 return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL);
4267}
4268#endif /* !TAMP */
4269
4270#if defined(TAMP)
4277__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
4278{
4279 return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1UL : 0UL);
4280}
4281
4288__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
4289{
4290 return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1UL : 0UL);
4291}
4292
4299__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
4300{
4301 return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1UL : 0UL);
4302}
4303
4310__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
4311{
4312 return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1UL : 0UL);
4313}
4314
4321__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
4322{
4323 return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1UL : 0UL);
4324}
4325
4332__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
4333{
4334 return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1UL : 0UL);
4335}
4336
4343__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
4344{
4345 SET_BIT(RTCx->SCR, RTC_SCR_CITSF);
4346}
4347
4354__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
4355{
4356 SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF);
4357}
4358
4365__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
4366{
4367 SET_BIT(RTCx->SCR, RTC_SCR_CTSF);
4368}
4369
4376__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
4377{
4378 SET_BIT(RTCx->SCR, RTC_SCR_CWUTF);
4379}
4380
4387__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
4388{
4389 SET_BIT(RTCx->SCR, RTC_SCR_CALRBF);
4390}
4391
4398__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
4399{
4400 SET_BIT(RTCx->SCR, RTC_SCR_CALRAF);
4401}
4402
4409__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
4410{
4411 return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1UL : 0UL);
4412}
4413
4420__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
4421{
4422 return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1UL : 0UL);
4423}
4424
4431__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
4432{
4433 return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1UL : 0UL);
4434}
4435
4442__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
4443{
4444 WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT)));
4445}
4446
4453__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
4454{
4455 return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1UL : 0UL);
4456}
4457
4464__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
4465{
4466 return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1UL : 0UL);
4467}
4468
4475__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
4476{
4477 return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1UL : 0UL);
4478}
4479
4486__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
4487{
4488 return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)) ? 1UL : 0UL);
4489}
4490
4497__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
4498{
4499 return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1UL : 0UL);
4500}
4501
4508__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx)
4509{
4510 return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1UL : 0UL);
4511}
4512
4519__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx)
4520{
4521 return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1UL : 0UL);
4522}
4523
4530__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx)
4531{
4532 return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1UL : 0UL);
4533}
4534
4541__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx)
4542{
4543 return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1UL : 0UL);
4544}
4545
4552__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx)
4553{
4554 return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1UL : 0UL);
4555}
4556
4563__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx)
4564{
4565 return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1UL : 0UL);
4566}
4567
4574__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx)
4575{
4576 return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1UL : 0UL);
4577}
4578
4585__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef *TAMPx)
4586{
4587 return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1UL : 0UL);
4588}
4589
4596__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(TAMP_TypeDef *TAMPx)
4597{
4598 return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1UL : 0UL);
4599}
4600
4607__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx)
4608{
4609 return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1UL : 0UL);
4610}
4611
4618__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef *TAMPx)
4619{
4620 return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1UL : 0UL);
4621}
4622
4629__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(TAMP_TypeDef *TAMPx)
4630{
4631 return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1UL : 0UL);
4632}
4633
4640__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(TAMP_TypeDef *TAMPx)
4641{
4642 SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F);
4643}
4644
4651__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(TAMP_TypeDef *TAMPx)
4652{
4653 SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F);
4654}
4655
4662__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(TAMP_TypeDef *TAMPx)
4663{
4664 SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP3F);
4665}
4666#endif /* TAMP */
4667
4684__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
4685{
4686 SET_BIT(RTCx->CR, RTC_CR_TSIE);
4687}
4688
4696__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
4697{
4698 CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
4699}
4700
4708__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
4709{
4710 SET_BIT(RTCx->CR, RTC_CR_WUTIE);
4711}
4712
4720__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
4721{
4722 CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
4723}
4724
4732__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
4733{
4734 SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
4735}
4736
4744__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
4745{
4746 CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
4747}
4748
4756__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
4757{
4758 SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
4759}
4760
4768__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
4769{
4770 CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
4771}
4772
4773#if !defined(TAMP)
4780__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
4781{
4782 SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
4783}
4784
4791__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
4792{
4793 CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
4794}
4795
4802__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
4803{
4804 SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
4805}
4806
4813__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
4814{
4815 CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
4816}
4817
4824__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
4825{
4826 SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
4827}
4828
4835__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
4836{
4837 CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
4838}
4839
4846__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
4847{
4848 SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
4849}
4850
4857__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
4858{
4859 CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
4860}
4861#endif /* !TAMP */
4862
4869__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
4870{
4871 return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL);
4872}
4873
4880__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
4881{
4882 return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL);
4883}
4884
4891__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
4892{
4893 return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL);
4894}
4895
4902__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
4903{
4904 return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);
4905}
4906
4907#if !defined(TAMP)
4914__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
4915{
4916 return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL);
4917}
4918
4925__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
4926{
4927 return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL);
4928
4929}
4930
4937__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
4938{
4939 return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL);
4940}
4941
4948__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
4949{
4950 return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL);
4951}
4952#endif /* !TAMP */
4953
4954#if defined(TAMP)
4961__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(TAMP_TypeDef *TAMPx)
4962{
4963 SET_BIT(TAMPx->IER, TAMP_IER_TAMP1IE);
4964}
4965
4972__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(TAMP_TypeDef *TAMPx)
4973{
4974 CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP1IE);
4975}
4976
4983__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(TAMP_TypeDef *TAMPx)
4984{
4985 SET_BIT(TAMPx->IER, TAMP_IER_TAMP2IE);
4986}
4987
4994__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(TAMP_TypeDef *TAMPx)
4995{
4996 CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP2IE);
4997}
4998
5005__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(TAMP_TypeDef *TAMPx)
5006{
5007 SET_BIT(TAMPx->IER, TAMP_IER_TAMP3IE);
5008}
5009
5016__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(TAMP_TypeDef *TAMPx)
5017{
5018 CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP3IE);
5019}
5020
5027__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef *TAMPx)
5028{
5029 return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1UL : 0UL);
5030}
5031
5038__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(TAMP_TypeDef *TAMPx)
5039{
5040 return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1UL : 0UL);
5041}
5042
5049__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(TAMP_TypeDef *TAMPx)
5050{
5051 return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1UL : 0UL);
5052}
5053
5072__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper)
5073{
5074 SET_BIT(TAMP->ATCR1, Tamper);
5075}
5076
5087__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper)
5088{
5089 CLEAR_BIT(TAMP->ATCR1, Tamper);
5090}
5091
5097__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableFilter(void)
5098{
5099 SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
5100}
5101
5107__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableFilter(void)
5108{
5109 CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
5110}
5111
5118__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod)
5119{
5120 MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos));
5121}
5122
5128__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(void)
5129{
5130 return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos);
5131}
5132
5141__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler)
5142{
5143 MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler);
5144}
5145
5151__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler(void)
5152{
5153 return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL));
5154}
5155
5161__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableOutputSharing(void)
5162{
5163 SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
5164}
5165
5171__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableOutputSharing(void)
5172{
5173 CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
5174}
5175
5184__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection(uint32_t OutputSelection)
5185{
5186 MODIFY_REG(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3), \
5187 OutputSelection);
5188}
5189
5195__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void)
5196{
5197 return (READ_BIT(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3)));
5198}
5199
5206__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed)
5207{
5208 WRITE_REG(TAMP->ATSEEDR, Seed);
5209}
5210
5216__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS(void)
5217{
5218 return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U);
5219}
5220
5226__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void)
5227{
5228 return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U);
5229}
5230#endif /* TAMP */
5231
5237#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
5243ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
5244ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
5245void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
5246ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
5247void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
5248ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
5249void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
5250ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
5251ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
5252void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
5253void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
5254ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
5255ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
5256ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
5257
5261#endif /* USE_FULL_LL_DRIVER */
5262
5271#endif /* defined(RTC) */
5272
5277#ifdef __cplusplus
5278}
5279#endif
5280
5281#endif /* STM32H7xx_LL_RTC_H */
5282
#define __IO
Definition: core_cm4.h:239
#define RTC_CR_OUT2EN
Definition: stm32h7a3xx.h:14660
#define RTC_CR_TAMPOE
Definition: stm32h7a3xx.h:14669
#define RTC_CR_TAMPALRM_PU
Definition: stm32h7a3xx.h:14666
#define RTC_CR_TAMPALRM_TYPE
Definition: stm32h7a3xx.h:14663
#define RTC_CR_TAMPTS
Definition: stm32h7a3xx.h:14672
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
Real-Time Clock.
Definition: stm32h723xx.h:1307
__IO uint32_t SCR
Definition: stm32h7a3xx.h:1176
__IO uint32_t TSTR
Definition: stm32h723xx.h:1320
__IO uint32_t TSSSR
Definition: stm32h723xx.h:1322
__IO uint32_t ALRMBSSR
Definition: stm32h723xx.h:1326
__IO uint32_t TR
Definition: stm32h723xx.h:1308
__IO uint32_t SR
Definition: stm32h7a3xx.h:1173
__IO uint32_t ISR
Definition: stm32h723xx.h:1311
__IO uint32_t PRER
Definition: stm32h723xx.h:1312
__IO uint32_t SHIFTR
Definition: stm32h723xx.h:1319
__IO uint32_t CR
Definition: stm32h723xx.h:1310
__IO uint32_t DR
Definition: stm32h723xx.h:1309
__IO uint32_t MISR
Definition: stm32h7a3xx.h:1174
__IO uint32_t ALRMBR
Definition: stm32h723xx.h:1316
__IO uint32_t TSDR
Definition: stm32h723xx.h:1321
__IO uint32_t BKP0R
Definition: stm32h723xx.h:1328
__IO uint32_t TAMPCR
Definition: stm32h723xx.h:1324
__IO uint32_t OR
Definition: stm32h723xx.h:1327
__IO uint32_t ALRMASSR
Definition: stm32h723xx.h:1325
__IO uint32_t WPR
Definition: stm32h723xx.h:1317
__IO uint32_t ALRMAR
Definition: stm32h723xx.h:1315
__IO uint32_t WUTR
Definition: stm32h723xx.h:1313
__IO uint32_t CALR
Definition: stm32h723xx.h:1323
__IO uint32_t SSR
Definition: stm32h723xx.h:1318
__IO uint32_t ICSR
Definition: stm32h7a3xx.h:1156
Tamper and backup registers.
Definition: stm32h7a3xx.h:1184
__IO uint32_t MISR
Definition: stm32h7a3xx.h:1195
__IO uint32_t SR
Definition: stm32h7a3xx.h:1194
__IO uint32_t FLTCR
Definition: stm32h7a3xx.h:1188
__IO uint32_t SCR
Definition: stm32h7a3xx.h:1197
__IO uint32_t IER
Definition: stm32h7a3xx.h:1193
__IO uint32_t CR2
Definition: stm32h7a3xx.h:1186
__IO uint32_t CR1
Definition: stm32h7a3xx.h:1185
__IO uint32_t BKP0R
Definition: stm32h7a3xx.h:1202