stm32h7xx_ll_pwr.h

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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_LL_PWR_H
#define STM32H7xx_LL_PWR_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx.h"
 
#if defined (PWR)
 
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Wake-Up Pins PWR register offsets */
#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET    2UL
#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK       0x1FU
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#define LL_PWR_FLAG_CPU_CSSF          PWR_CPUCR_CSSF      
#if defined (DUAL_CORE)
#define LL_PWR_FLAG_CPU2_CSSF         PWR_CPU2CR_CSSF     
#endif /* DUAL_CORE */
#define LL_PWR_FLAG_WKUPCR_WKUPC6     PWR_WKUPCR_WKUPC6   
#if defined (PWR_WKUPCR_WKUPC5)
#define LL_PWR_FLAG_WKUPCR_WKUPC5     PWR_WKUPCR_WKUPC5   
#endif /* defined (PWR_WKUPCR_WKUPC5) */
#define LL_PWR_FLAG_WKUPCR_WKUPC4     PWR_WKUPCR_WKUPC4   
#if defined (PWR_WKUPCR_WKUPC3)
#define LL_PWR_FLAG_WKUPCR_WKUPC3     PWR_WKUPCR_WKUPC3   
#endif /* defined (PWR_WKUPCR_WKUPC3) */
#define LL_PWR_FLAG_WKUPCR_WKUPC2     PWR_WKUPCR_WKUPC2   
#define LL_PWR_FLAG_WKUPCR_WKUPC1     PWR_WKUPCR_WKUPC1   
#define LL_PWR_FLAG_AVDO              PWR_CSR1_AVDO       
#define LL_PWR_FLAG_PVDO              PWR_CSR1_PVDO       
#define LL_PWR_FLAG_ACTVOS            PWR_CSR1_ACTVOS     
#define LL_PWR_FLAG_ACTVOSRDY         PWR_CSR1_ACTVOSRDY  
#if defined (PWR_CSR1_MMCVDO)
#define LL_PWR_FLAG_MMCVDO            PWR_CSR1_MMCVDO     
#endif /* PWR_CSR1_MMCVDO */
 
#define LL_PWR_FLAG_TEMPH             PWR_CR2_TEMPH       
#define LL_PWR_FLAG_TEMPL             PWR_CR2_TEMPL       
#define LL_PWR_FLAG_VBATH             PWR_CR2_VBATH       
#define LL_PWR_FLAG_VBATL             PWR_CR2_VBATL       
#define LL_PWR_FLAG_BRRDY             PWR_CR2_BRRDY       
#define LL_PWR_FLAG_USBRDY            PWR_CR3_USB33RDY    
#define LL_PWR_FLAG_SMPSEXTRDY        PWR_CR3_SMPSEXTRDY  
#if defined (PWR_CPUCR_SBF_D2)
#define LL_PWR_FLAG_CPU_SBF_D2        PWR_CPUCR_SBF_D2    
#endif /* PWR_CPUCR_SBF_D2 */
#if defined (PWR_CPUCR_SBF_D1)
#define LL_PWR_FLAG_CPU_SBF_D1        PWR_CPUCR_SBF_D1    
#endif /* PWR_CPUCR_SBF_D1 */
#define LL_PWR_FLAG_CPU_SBF           PWR_CPUCR_SBF       
#define LL_PWR_FLAG_CPU_STOPF         PWR_CPUCR_STOPF     
#if defined (DUAL_CORE)
#define LL_PWR_FLAG_CPU_HOLD2F        PWR_CPUCR_HOLD2F    
#endif /* DUAL_CORE */
 
#if defined (DUAL_CORE)
#define LL_PWR_FLAG_CPU2_SBF_D2       PWR_CPU2CR_SBF_D2   
#define LL_PWR_FLAG_CPU2_SBF_D1       PWR_CPU2CR_SBF_D1   
#define LL_PWR_FLAG_CPU2_SBF          PWR_CPU2CR_SBF      
#define LL_PWR_FLAG_CPU2_STOPF        PWR_CPU2CR_STOPF    
#define LL_PWR_FLAG_CPU2_HOLD1F       PWR_CPU2CR_HOLD1F   
#endif /* DUAL_CORE */
 
#if defined (PWR_CPUCR_PDDS_D2)
#define LL_PWR_D3CR_VOSRDY            PWR_D3CR_VOSRDY     
#else
#define LL_PWR_SRDCR_VOSRDY           PWR_SRDCR_VOSRDY    
#endif /* PWR_CPUCR_PDDS_D2 */
 
#define LL_PWR_WKUPFR_WKUPF6          PWR_WKUPFR_WKUPF6   
#if defined (PWR_WKUPFR_WKUPF5)
#define LL_PWR_WKUPFR_WKUPF5          PWR_WKUPFR_WKUPF5   
#endif /* defined (PWR_WKUPFR_WKUPF5) */
#define LL_PWR_WKUPFR_WKUPF4          PWR_WKUPFR_WKUPF4   
#if defined (PWR_WKUPFR_WKUPF3)
#define LL_PWR_WKUPFR_WKUPF3          PWR_WKUPFR_WKUPF3   
#endif /* defined (PWR_WKUPFR_WKUPF3) */
#define LL_PWR_WKUPFR_WKUPF2          PWR_WKUPFR_WKUPF2   
#define LL_PWR_WKUPFR_WKUPF1          PWR_WKUPFR_WKUPF1   
#if defined (PWR_CPUCR_PDDS_D2)
#define LL_PWR_CPU_MODE_D1STOP        0x00000000U           
#define LL_PWR_CPU_MODE_D1STANDBY     PWR_CPUCR_PDDS_D1     
#else
#define LL_PWR_CPU_MODE_CDSTOP        0x00000000U           
#define LL_PWR_CPU_MODE_CDSTOP2       PWR_CPUCR_RETDS_CD    
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (PWR_CPUCR_PDDS_D2)
#define LL_PWR_CPU_MODE_D2STOP        0x00000000U           
#define LL_PWR_CPU_MODE_D2STANDBY     PWR_CPUCR_PDDS_D2     
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (PWR_CPUCR_PDDS_D2)
#define LL_PWR_CPU_MODE_D3RUN         PWR_CPUCR_RUN_D3      
#define LL_PWR_CPU_MODE_D3STOP        0x00000000U           
#define LL_PWR_CPU_MODE_D3STANDBY     PWR_CPUCR_PDDS_D3     
#else
#define LL_PWR_CPU_MODE_SRDRUN        PWR_CPUCR_RUN_SRD     
#define LL_PWR_CPU_MODE_SRDSTOP       0x00000000U           
#define LL_PWR_CPU_MODE_SRDSTANDBY    PWR_CPUCR_PDDS_SRD    
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (DUAL_CORE)
#define LL_PWR_CPU2_MODE_D1STOP       0x00000000U           
#define LL_PWR_CPU2_MODE_D1STANDBY    PWR_CPU2CR_PDDS_D1    
#define LL_PWR_CPU2_MODE_D2STOP       0x00000000U           
#define LL_PWR_CPU2_MODE_D2STANDBY    PWR_CPU2CR_PDDS_D2    
#define LL_PWR_CPU2_MODE_D3RUN        PWR_CPU2CR_RUN_D3     
#define LL_PWR_CPU2_MODE_D3STOP       0x00000000U           
#define LL_PWR_CPU2_MODE_D3STANDBY    PWR_CPU2CR_PDDS_D3    
#endif /* DUAL_CORE */
#if defined (PWR_CPUCR_PDDS_D2)
#define LL_PWR_REGU_VOLTAGE_SCALE3      PWR_D3CR_VOS_0                    
#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_1                    
#define LL_PWR_REGU_VOLTAGE_SCALE1      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) 
#if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) 
#else
#define LL_PWR_REGU_VOLTAGE_SCALE0      0x00000000U                       
#endif /* defined (SYSCFG_PWRCR_ODEN) */
#else
#define LL_PWR_REGU_VOLTAGE_SCALE3      0x00000000U                       
#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_0                    
#define LL_PWR_REGU_VOLTAGE_SCALE1      PWR_D3CR_VOS_1                    
#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) 
#endif /* PWR_CPUCR_PDDS_D2 */
#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5   PWR_CR1_SVOS_0                    
#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4   PWR_CR1_SVOS_1                    
#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3   (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) 
#define LL_PWR_REGU_DSMODE_MAIN           0x00000000U   
#define LL_PWR_REGU_DSMODE_LOW_POWER      PWR_CR1_LPDS  
#define LL_PWR_PVDLEVEL_0   PWR_CR1_PLS_LEV0  
#define LL_PWR_PVDLEVEL_1   PWR_CR1_PLS_LEV1  
#define LL_PWR_PVDLEVEL_2   PWR_CR1_PLS_LEV2  
#define LL_PWR_PVDLEVEL_3   PWR_CR1_PLS_LEV3  
#define LL_PWR_PVDLEVEL_4   PWR_CR1_PLS_LEV4  
#define LL_PWR_PVDLEVEL_5   PWR_CR1_PLS_LEV5  
#define LL_PWR_PVDLEVEL_6   PWR_CR1_PLS_LEV6  
#define LL_PWR_PVDLEVEL_7   PWR_CR1_PLS_LEV7  
#define LL_PWR_AVDLEVEL_0   PWR_CR1_ALS_LEV0  
#define LL_PWR_AVDLEVEL_1   PWR_CR1_ALS_LEV1  
#define LL_PWR_AVDLEVEL_2   PWR_CR1_ALS_LEV2  
#define LL_PWR_AVDLEVEL_3   PWR_CR1_ALS_LEV3  
#define LL_PWR_BATT_CHARG_RESISTOR_5K     0x00000000U   
#define LL_PWR_BATT_CHARGRESISTOR_1_5K    PWR_CR3_VBRS  
#define LL_PWR_WAKEUP_PIN1    PWR_WKUPEPR_WKUPEN1  
#define LL_PWR_WAKEUP_PIN2    PWR_WKUPEPR_WKUPEN2  
#if defined (PWR_WKUPEPR_WKUPEN3)
#define LL_PWR_WAKEUP_PIN3    PWR_WKUPEPR_WKUPEN3  
#endif /* defined (PWR_WKUPEPR_WKUPEN3) */
#define LL_PWR_WAKEUP_PIN4    PWR_WKUPEPR_WKUPEN4  
#if defined (PWR_WKUPEPR_WKUPEN5)
#define LL_PWR_WAKEUP_PIN5    PWR_WKUPEPR_WKUPEN5  
#endif /* defined (PWR_WKUPEPR_WKUPEN5) */
#define LL_PWR_WAKEUP_PIN6    PWR_WKUPEPR_WKUPEN6  
#define LL_PWR_WAKEUP_PIN_NOPULL      0x00000000UL   
#define LL_PWR_WAKEUP_PIN_PULLUP      0x00000001UL   
#define LL_PWR_WAKEUP_PIN_PULLDOWN    0x00000002UL   
#define LL_PWR_LDO_SUPPLY                     PWR_CR3_LDOEN                                                               
#if defined (SMPS)
#define LL_PWR_DIRECT_SMPS_SUPPLY             PWR_CR3_SMPSEN                                                              
#define LL_PWR_SMPS_1V8_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      
#define LL_PWR_SMPS_2V5_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      
#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  
#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  
#define LL_PWR_SMPS_1V8_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) 
#define LL_PWR_SMPS_2V5_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) 
#endif /* SMPS */
#define LL_PWR_EXTERNAL_SOURCE_SUPPLY         PWR_CR3_BYPASS                                                              
/* Exported macro ------------------------------------------------------------*/
#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
 
#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
/* Exported functions --------------------------------------------------------*/
__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
{
  MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
}
 
__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
{
  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
}
 
__STATIC_INLINE void LL_PWR_EnablePVD(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
}
 
__STATIC_INLINE void LL_PWR_DisablePVD(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
}
 
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
{
  MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
}
 
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
{
  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
}
 
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_DBP);
}
 
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
}
 
__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_FLPS);
}
 
__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
}
 
#if defined (PWR_CR1_BOOSTE)
__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_BOOSTE);
}
 
__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL);
}
#endif /* PWR_CR1_BOOSTE */
 
#if defined (PWR_CR1_AVD_READY)
__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_AVD_READY);
}
 
__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL);
}
#endif /* PWR_CR1_AVD_READY */
 
__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
{
  MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
}
 
__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
{
  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));
}
 
__STATIC_INLINE void LL_PWR_EnableAVD(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
}
 
__STATIC_INLINE void LL_PWR_DisableAVD(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
}
 
__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
{
  MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
}
 
__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
{
  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
}
 
#if defined (PWR_CR1_AXIRAM1SO)
__STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
}
 
__STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL);
}
#endif /* PWR_CR1_AXIRAM1SO */
 
#if defined (PWR_CR1_AXIRAM2SO)
__STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
}
 
__STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL);
}
#endif /* PWR_CR1_AXIRAM2SO */
 
#if defined (PWR_CR1_AXIRAM3SO)
__STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
}
 
__STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL);
}
#endif /* PWR_CR1_AXIRAM3SO */
 
#if defined (PWR_CR1_AHBRAM1SO)
__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
}
 
__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL);
}
#endif /* PWR_CR1_AHBRAM1SO */
 
#if defined (PWR_CR1_AHBRAM2SO)
__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
}
 
__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL);
}
#endif /* PWR_CR1_AHBRAM2SO */
 
#if defined (PWR_CR1_ITCMSO)
__STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_ITCMSO);
}
 
__STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL);
}
#endif /* PWR_CR1_ITCMSO */
 
#if defined (PWR_CR1_HSITFSO)
__STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_HSITFSO);
}
 
__STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL);
}
#endif /* PWR_CR1_HSITFSO */
 
#if defined (PWR_CR1_SRDRAMSO)
__STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void)
{
  SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
}
 
__STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void)
{
  CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void)
{
  return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL);
}
#endif /* PWR_CR1_SRDRAMSO */
 
__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
{
  SET_BIT(PWR->CR2, PWR_CR2_BREN);
}
 
__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
{
  CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
{
  return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
}
 
__STATIC_INLINE void LL_PWR_EnableMonitoring(void)
{
  SET_BIT(PWR->CR2, PWR_CR2_MONEN);
}
 
__STATIC_INLINE void LL_PWR_DisableMonitoring(void)
{
  CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
{
  return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
}
 
#if defined (SMPS)
__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
{
  /* Set the power supply configuration */
  MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
}
#else
__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
{
  /* Set the power supply configuration */
  MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
}
#endif /* defined (SMPS) */
 
#if defined (SMPS)
__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
{
  /* Get the power supply configuration */
  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
}
#else
__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
{
  /* Get the power supply configuration */
  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
}
#endif /* defined (SMPS) */
 
__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
{
  SET_BIT(PWR->CR3, PWR_CR3_VBE);
}
 
__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
{
  CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
{
  return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
}
 
__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
{
  MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
}
 
__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
{
  return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
}
 
__STATIC_INLINE void LL_PWR_EnableUSBReg(void)
{
  SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
}
 
__STATIC_INLINE void LL_PWR_DisableUSBReg(void)
{
  CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
{
  return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);
}
 
__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
{
  SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
}
 
__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
{
  CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
{
  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
}
 
#if defined (PWR_CPUCR_PDDS_D2)
__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)
{
  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);
}
#else
__STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode)
{
  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode);
}
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (DUAL_CORE)
__STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode)
{
  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode);
}
#endif /* DUAL_CORE */
 
#if defined (PWR_CPUCR_PDDS_D2)
__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)
{
  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));
}
#else
__STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void)
{
  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD));
}
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (DUAL_CORE)
__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void)
{
  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1));
}
#endif /* DUAL_CORE */
 
#if defined (PWR_CPUCR_PDDS_D2)
__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)
{
  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);
}
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (DUAL_CORE)
__STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode)
{
  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode);
}
#endif /* DUAL_CORE */
 
#if defined (PWR_CPUCR_PDDS_D2)
__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)
{
  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));
}
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (DUAL_CORE)
__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void)
{
  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2));
}
#endif /* DUAL_CORE */
 
#if defined (PWR_CPUCR_PDDS_D2)
__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)
{
  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);
}
#else
__STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode)
{
  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode);
}
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (DUAL_CORE)
__STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode)
{
  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode);
}
#endif /* DUAL_CORE */
 
#if defined (PWR_CPUCR_PDDS_D2)
__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)
{
  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));
}
#else
__STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void)
{
  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));
}
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (DUAL_CORE)
__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void)
{
  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3));
}
#endif /* DUAL_CORE */
 
#if defined (DUAL_CORE)
__STATIC_INLINE void LL_PWR_HoldCPU1(void)
{
  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
}
 
__STATIC_INLINE void LL_PWR_ReleaseCPU1(void)
{
  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void)
{
  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1))  ? 1UL : 0UL);
}
 
__STATIC_INLINE void LL_PWR_HoldCPU2(void)
{
  SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
}
 
__STATIC_INLINE void LL_PWR_ReleaseCPU2(void)
{
  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void)
{
  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL);
}
#endif /* DUAL_CORE */
 
#if defined (PWR_CPUCR_PDDS_D2)
__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)
{
  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
}
#else
__STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void)
{
  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
}
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (DUAL_CORE)
__STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void)
{
  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
}
#endif /* DUAL_CORE */
 
#if defined (PWR_CPUCR_PDDS_D2)
__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)
{
  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
}
#else
__STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void)
{
  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
}
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (DUAL_CORE)
__STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void)
{
  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
}
#endif /* DUAL_CORE */
 
#if defined (PWR_CPUCR_PDDS_D2)
__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)
{
  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);
}
#else
__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void)
{
  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL);
}
#endif /* PWR_CPUCR_PDDS_D2 */
 
#if defined (DUAL_CORE)
__STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void)
{
  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL);
}
#endif /* DUAL_CORE */
 
__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
{
#if defined (PWR_CPUCR_PDDS_D2)
  MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
#else
  MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
#endif /* PWR_CPUCR_PDDS_D2 */
}
 
__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
{
#if defined (PWR_CPUCR_PDDS_D2)
  return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));
#else
  return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS));
#endif /* PWR_CPUCR_PDDS_D2 */
}
 
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
{
  SET_BIT(PWR->WKUPEPR, WakeUpPin);
}
 
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
{
  CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
{
  return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
}
 
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
{
  SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
}
 
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
{
  CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
}
 
__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
{
  return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
}
 
__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
{
  MODIFY_REG(PWR->WKUPEPR, \
            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
            (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
}
 
__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
{
  MODIFY_REG(PWR->WKUPEPR, \
            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
            (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
}
 
__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
{
  MODIFY_REG(PWR->WKUPEPR, \
            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
            (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
}
 
__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
{
  uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
 
  return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
}
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
{
  return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
{
  return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
{
  return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
}
 
#if defined (PWR_CSR1_MMCVDO)
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void)
{
  return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL);
}
#endif /* PWR_CSR1_MMCVDO */
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
{
  return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
{
  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
{
  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
{
  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
{
  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
}
 
#if defined (SMPS)
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void)
{
  return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL);
}
#endif /* SMPS */
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
{
  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
}
 
#if defined (DUAL_CORE)
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void)
{
  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void)
{
  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL);
}
#endif /* DUAL_CORE */
 
__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)
{
  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
}
 
#if defined (DUAL_CORE)
__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void)
{
  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL);
}
#endif /* DUAL_CORE */
 
__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)
{
  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
}
 
#if defined (DUAL_CORE)
__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void)
{
  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL);
}
#endif /* DUAL_CORE */
 
#if defined (PWR_CPUCR_SBF_D1)
__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)
{
  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);
}
#endif /* PWR_CPUCR_SBF_D1 */
 
#if defined (DUAL_CORE)
__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void)
{
  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL);
}
#endif /* DUAL_CORE */
 
#if defined (PWR_CPUCR_SBF_D2)
__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)
{
  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);
}
#endif /* PWR_CPUCR_SBF_D2 */
 
#if defined (DUAL_CORE)
__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void)
{
  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL);
}
#endif /* DUAL_CORE */
 
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
{
#if defined (PWR_CPUCR_PDDS_D2)
  return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);
#else
  return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL);
#endif /* PWR_CPUCR_PDDS_D2 */
}
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
{
  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
}
 
#if defined (PWR_WKUPFR_WKUPF5)
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
{
  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
}
#endif /* defined (PWR_WKUPFR_WKUPF5) */
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
{
  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
}
 
#if defined (PWR_WKUPFR_WKUPF3)
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
{
  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
}
#endif /* defined (PWR_WKUPFR_WKUPF3) */
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
{
  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
}
 
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
{
  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
}
 
__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)
{
  SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
}
 
#if defined (DUAL_CORE)
__STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void)
{
  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);
}
#endif /* DUAL_CORE */
 
__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
{
  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
}
 
#if defined (PWR_WKUPCR_WKUPC5)
__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
{
  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
}
#endif /* defined (PWR_WKUPCR_WKUPC5) */
 
__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
{
  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
}
 
#if defined (PWR_WKUPCR_WKUPC3)
__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
{
  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
}
#endif /* defined (PWR_WKUPCR_WKUPC3) */
 
__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
{
  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
}
 
__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
{
  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
}
 
#if defined (USE_FULL_LL_DRIVER)
ErrorStatus LL_PWR_DeInit(void);
#endif /* defined (USE_FULL_LL_DRIVER) */
 
 
#endif /* defined (PWR) */
 
#ifdef __cplusplus
}
#endif
 
#endif /* STM32H7xx_LL_PWR_H */