RTEMS 6.1-rc5
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stm32h7xx_hal_rcc.h
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1
18/* Define to prevent recursive inclusion -------------------------------------*/
19#ifndef STM32H7xx_HAL_RCC_H
20#define STM32H7xx_HAL_RCC_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/* Includes ------------------------------------------------------------------*/
27#include "stm32h7xx_hal_def.h"
28
37/* Exported types ------------------------------------------------------------*/
38
47typedef struct
48{
49 uint32_t PLLState;
52 uint32_t PLLSource;
55 uint32_t PLLM;
58 uint32_t PLLN;
63 uint32_t PLLP;
67 uint32_t PLLQ;
70 uint32_t PLLR;
72 uint32_t PLLRGE;
74 uint32_t PLLVCOSEL;
77 uint32_t PLLFRACN;
80} RCC_PLLInitTypeDef;
81
85typedef struct
86{
87 uint32_t OscillatorType;
90 uint32_t HSEState;
93 uint32_t LSEState;
96 uint32_t HSIState;
99 uint32_t HSICalibrationValue;
103 uint32_t LSIState;
106 uint32_t HSI48State;
109 uint32_t CSIState;
112 uint32_t CSICalibrationValue;
116 RCC_PLLInitTypeDef PLL;
118} RCC_OscInitTypeDef;
119
123typedef struct
124{
125 uint32_t ClockType;
128 uint32_t SYSCLKSource;
131 uint32_t SYSCLKDivider;
134 uint32_t AHBCLKDivider;
137 uint32_t APB3CLKDivider;
140 uint32_t APB1CLKDivider;
142 uint32_t APB2CLKDivider;
144 uint32_t APB4CLKDivider;
146} RCC_ClkInitTypeDef;
147
152/* Exported constants --------------------------------------------------------*/
153
163#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
164#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
165#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
166#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
167#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
168#define RCC_OSCILLATORTYPE_CSI (0x00000010U)
169#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U)
170
179#define RCC_HSE_OFF (0x00000000U)
180#define RCC_HSE_ON RCC_CR_HSEON
181#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
182#if defined(RCC_CR_HSEEXT)
183#define RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))
184#endif /* RCC_CR_HSEEXT */
185
194#define RCC_LSE_OFF (0x00000000U)
195#define RCC_LSE_ON RCC_BDCR_LSEON
196#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
197#if defined(RCC_BDCR_LSEEXT)
198#define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
199#endif /* RCC_BDCR_LSEEXT */
200
209#define RCC_HSI_OFF (0x00000000U)
210#define RCC_HSI_ON RCC_CR_HSION
212#define RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 | RCC_CR_HSION)
213#define RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 | RCC_CR_HSION)
214#define RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 | RCC_CR_HSION)
215#define RCC_HSI_DIV8 (RCC_CR_HSIDIV | RCC_CR_HSION)
218#define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value for STM32H7 rev.V and above. (0x20 value for rev.Y handled within __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST macro ) */
227#define RCC_HSI48_OFF ((uint8_t)0x00)
228#define RCC_HSI48_ON ((uint8_t)0x01)
229
238#define RCC_LSI_OFF (0x00000000U)
239#define RCC_LSI_ON RCC_CSR_LSION
240
249#define RCC_CSI_OFF (0x00000000U)
250#define RCC_CSI_ON RCC_CR_CSION
251
252#define RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value for STM32H7 rev.V and above. (0x10 value for rev.Y handled within __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST macro ) */
261#define RCC_PLL_NONE (0x00000000U)
262#define RCC_PLL_OFF (0x00000001U)
263#define RCC_PLL_ON (0x00000002U)
264
274#define RCC_PLLSOURCE_HSI (0x00000000U)
275#define RCC_PLLSOURCE_CSI (0x00000001U)
276#define RCC_PLLSOURCE_HSE (0x00000002U)
277#define RCC_PLLSOURCE_NONE (0x00000003U)
286#define RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN
287#define RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN
288#define RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN
289
300#define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0
301#define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1
302#define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2
303#define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3
315#define RCC_PLL1VCOWIDE (0x00000000U)
316#define RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL
317
327#define RCC_CLOCKTYPE_SYSCLK (0x00000001U)
328#define RCC_CLOCKTYPE_HCLK (0x00000002U)
329#define RCC_CLOCKTYPE_D1PCLK1 (0x00000004U)
330#define RCC_CLOCKTYPE_PCLK1 (0x00000008U)
331#define RCC_CLOCKTYPE_PCLK2 (0x00000010U)
332#define RCC_CLOCKTYPE_D3PCLK1 (0x00000020U)
333
342#define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI
343#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
344#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
345#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1
346
355#define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI
356#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
357#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
358#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1
367#if defined(RCC_D1CFGR_D1CPRE_DIV1)
368#define RCC_SYSCLK_DIV1 RCC_D1CFGR_D1CPRE_DIV1
369#define RCC_SYSCLK_DIV2 RCC_D1CFGR_D1CPRE_DIV2
370#define RCC_SYSCLK_DIV4 RCC_D1CFGR_D1CPRE_DIV4
371#define RCC_SYSCLK_DIV8 RCC_D1CFGR_D1CPRE_DIV8
372#define RCC_SYSCLK_DIV16 RCC_D1CFGR_D1CPRE_DIV16
373#define RCC_SYSCLK_DIV64 RCC_D1CFGR_D1CPRE_DIV64
374#define RCC_SYSCLK_DIV128 RCC_D1CFGR_D1CPRE_DIV128
375#define RCC_SYSCLK_DIV256 RCC_D1CFGR_D1CPRE_DIV256
376#define RCC_SYSCLK_DIV512 RCC_D1CFGR_D1CPRE_DIV512
377#else
378#define RCC_SYSCLK_DIV1 RCC_CDCFGR1_CDCPRE_DIV1
379#define RCC_SYSCLK_DIV2 RCC_CDCFGR1_CDCPRE_DIV2
380#define RCC_SYSCLK_DIV4 RCC_CDCFGR1_CDCPRE_DIV4
381#define RCC_SYSCLK_DIV8 RCC_CDCFGR1_CDCPRE_DIV8
382#define RCC_SYSCLK_DIV16 RCC_CDCFGR1_CDCPRE_DIV16
383#define RCC_SYSCLK_DIV64 RCC_CDCFGR1_CDCPRE_DIV64
384#define RCC_SYSCLK_DIV128 RCC_CDCFGR1_CDCPRE_DIV128
385#define RCC_SYSCLK_DIV256 RCC_CDCFGR1_CDCPRE_DIV256
386#define RCC_SYSCLK_DIV512 RCC_CDCFGR1_CDCPRE_DIV512
387#endif
397#if defined(RCC_D1CFGR_HPRE_DIV1)
398#define RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1
399#define RCC_HCLK_DIV2 RCC_D1CFGR_HPRE_DIV2
400#define RCC_HCLK_DIV4 RCC_D1CFGR_HPRE_DIV4
401#define RCC_HCLK_DIV8 RCC_D1CFGR_HPRE_DIV8
402#define RCC_HCLK_DIV16 RCC_D1CFGR_HPRE_DIV16
403#define RCC_HCLK_DIV64 RCC_D1CFGR_HPRE_DIV64
404#define RCC_HCLK_DIV128 RCC_D1CFGR_HPRE_DIV128
405#define RCC_HCLK_DIV256 RCC_D1CFGR_HPRE_DIV256
406#define RCC_HCLK_DIV512 RCC_D1CFGR_HPRE_DIV512
407#else
408#define RCC_HCLK_DIV1 RCC_CDCFGR1_HPRE_DIV1
409#define RCC_HCLK_DIV2 RCC_CDCFGR1_HPRE_DIV2
410#define RCC_HCLK_DIV4 RCC_CDCFGR1_HPRE_DIV4
411#define RCC_HCLK_DIV8 RCC_CDCFGR1_HPRE_DIV8
412#define RCC_HCLK_DIV16 RCC_CDCFGR1_HPRE_DIV16
413#define RCC_HCLK_DIV64 RCC_CDCFGR1_HPRE_DIV64
414#define RCC_HCLK_DIV128 RCC_CDCFGR1_HPRE_DIV128
415#define RCC_HCLK_DIV256 RCC_CDCFGR1_HPRE_DIV256
416#define RCC_HCLK_DIV512 RCC_CDCFGR1_HPRE_DIV512
417#endif
426#if defined (RCC_D1CFGR_D1PPRE_DIV1)
427#define RCC_APB3_DIV1 RCC_D1CFGR_D1PPRE_DIV1
428#define RCC_APB3_DIV2 RCC_D1CFGR_D1PPRE_DIV2
429#define RCC_APB3_DIV4 RCC_D1CFGR_D1PPRE_DIV4
430#define RCC_APB3_DIV8 RCC_D1CFGR_D1PPRE_DIV8
431#define RCC_APB3_DIV16 RCC_D1CFGR_D1PPRE_DIV16
432#else
433#define RCC_APB3_DIV1 RCC_CDCFGR1_CDPPRE_DIV1
434#define RCC_APB3_DIV2 RCC_CDCFGR1_CDPPRE_DIV2
435#define RCC_APB3_DIV4 RCC_CDCFGR1_CDPPRE_DIV4
436#define RCC_APB3_DIV8 RCC_CDCFGR1_CDPPRE_DIV8
437#define RCC_APB3_DIV16 RCC_CDCFGR1_CDPPRE_DIV16
438#endif
447#if defined (RCC_D2CFGR_D2PPRE1_DIV1)
448#define RCC_APB1_DIV1 RCC_D2CFGR_D2PPRE1_DIV1
449#define RCC_APB1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2
450#define RCC_APB1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4
451#define RCC_APB1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8
452#define RCC_APB1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16
453#else
454#define RCC_APB1_DIV1 RCC_CDCFGR2_CDPPRE1_DIV1
455#define RCC_APB1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2
456#define RCC_APB1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4
457#define RCC_APB1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8
458#define RCC_APB1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16
459#endif
460
469#if defined (RCC_D2CFGR_D2PPRE2_DIV1)
470#define RCC_APB2_DIV1 RCC_D2CFGR_D2PPRE2_DIV1
471#define RCC_APB2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2
472#define RCC_APB2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4
473#define RCC_APB2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8
474#define RCC_APB2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16
475#else
476#define RCC_APB2_DIV1 RCC_CDCFGR2_CDPPRE2_DIV1
477#define RCC_APB2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2
478#define RCC_APB2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4
479#define RCC_APB2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8
480#define RCC_APB2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16
481#endif
490#if defined(RCC_D3CFGR_D3PPRE_DIV1)
491#define RCC_APB4_DIV1 RCC_D3CFGR_D3PPRE_DIV1
492#define RCC_APB4_DIV2 RCC_D3CFGR_D3PPRE_DIV2
493#define RCC_APB4_DIV4 RCC_D3CFGR_D3PPRE_DIV4
494#define RCC_APB4_DIV8 RCC_D3CFGR_D3PPRE_DIV8
495#define RCC_APB4_DIV16 RCC_D3CFGR_D3PPRE_DIV16
496#else
497#define RCC_APB4_DIV1 RCC_SRDCFGR_SRDPPRE_DIV1
498#define RCC_APB4_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2
499#define RCC_APB4_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4
500#define RCC_APB4_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8
501#define RCC_APB4_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16
502#endif
511#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U)
512#define RCC_RTCCLKSOURCE_LSE (0x00000100U)
513#define RCC_RTCCLKSOURCE_LSI (0x00000200U)
514#define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U)
515#define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U)
516#define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U)
517#define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U)
518#define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U)
519#define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U)
520#define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U)
521#define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U)
522#define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U)
523#define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U)
524#define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U)
525#define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U)
526#define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U)
527#define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U)
528#define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U)
529#define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U)
530#define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U)
531#define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U)
532#define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U)
533#define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U)
534#define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U)
535#define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U)
536#define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U)
537#define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U)
538#define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U)
539#define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U)
540#define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U)
541#define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U)
542#define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U)
543#define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U)
544#define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U)
545#define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U)
546#define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U)
547#define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U)
548#define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U)
549#define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U)
550#define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U)
551#define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U)
552#define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U)
553#define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U)
554#define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U)
555#define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U)
556#define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U)
557#define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U)
558#define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U)
559#define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U)
560#define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U)
561#define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U)
562#define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U)
563#define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U)
564#define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U)
565#define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U)
566#define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U)
567#define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U)
568#define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U)
569#define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U)
570#define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U)
571#define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U)
572#define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U)
573#define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U)
574#define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U)
575#define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U)
576
577
587#define RCC_MCO1 (0x00000000U)
588#define RCC_MCO2 (0x00000001U)
589
598#define RCC_MCO1SOURCE_HSI (0x00000000U)
599#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
600#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
601#define RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)
602#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2
603
612#define RCC_MCO2SOURCE_SYSCLK (0x00000000U)
613#define RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0
614#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
615#define RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)
616#define RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2
617#define RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)
618
627#define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0
628#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1
629#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
630#define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2
631#define RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
632#define RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
633#define RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
634#define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3
635#define RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
636#define RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
637#define RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
638#define RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
639#define RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
640#define RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
641#define RCC_MCODIV_15 RCC_CFGR_MCO1PRE
642
643
652#define RCC_IT_LSIRDY (0x00000001U)
653#define RCC_IT_LSERDY (0x00000002U)
654#define RCC_IT_HSIRDY (0x00000004U)
655#define RCC_IT_HSERDY (0x00000008U)
656#define RCC_IT_CSIRDY (0x00000010U)
657#define RCC_IT_HSI48RDY (0x00000020U)
658#define RCC_IT_PLLRDY (0x00000040U)
659#define RCC_IT_PLL2RDY (0x00000080U)
660#define RCC_IT_PLL3RDY (0x00000100U)
661#define RCC_IT_LSECSS (0x00000200U)
662#define RCC_IT_CSS (0x00000400U)
678/* Flags in the CR register */
679#define RCC_FLAG_HSIRDY ((uint8_t)0x22)
680#define RCC_FLAG_HSIDIV ((uint8_t)0x25)
681#define RCC_FLAG_CSIRDY ((uint8_t)0x28)
682#define RCC_FLAG_HSI48RDY ((uint8_t)0x2D)
683#if defined(RCC_CR_D1CKRDY)
684#define RCC_FLAG_D1CKRDY ((uint8_t)0x2E)
685#else
686#define RCC_FLAG_CPUCKRDY ((uint8_t)0x2E)
687#define RCC_FLAG_D1CKRDY RCC_FLAG_CPUCKRDY /* alias */
688#endif /* RCC_CR_D1CKRDY */
689#if defined(RCC_CR_D2CKRDY)
690#define RCC_FLAG_D2CKRDY ((uint8_t)0x2F)
691#else
692#define RCC_FLAG_CDCKRDY ((uint8_t)0x2F)
693#define RCC_FLAG_D2CKRDY RCC_FLAG_CDCKRDY /* alias */
694#endif /* RCC_CR_D2CKRDY */
695#define RCC_FLAG_HSERDY ((uint8_t)0x31)
696#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
697#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
698#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
699/* Flags in the BDCR register */
700#define RCC_FLAG_LSERDY ((uint8_t)0x41)
701
702/* Flags in the CSR register */
703#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
704
705/* Flags in the RSR register */
706#if defined(RCC_RSR_CPURSTF)
707#define RCC_FLAG_CPURST ((uint8_t)0x91)
708#endif /* RCC_RSR_CPURSTF */
709
710#if defined(RCC_RSR_D1RSTF)
711#define RCC_FLAG_D1RST ((uint8_t)0x93)
712#else
713#define RCC_FLAG_CDRST ((uint8_t)0x93)
714#endif /* RCC_RSR_D1RSTF */
715#if defined(RCC_RSR_D2RSTF)
716#define RCC_FLAG_D2RST ((uint8_t)0x94)
717#endif /* RCC_RSR_D2RSTF */
718#define RCC_FLAG_BORRST ((uint8_t)0x95)
719#define RCC_FLAG_PINRST ((uint8_t)0x96)
720#define RCC_FLAG_PORRST ((uint8_t)0x97)
721#define RCC_FLAG_SFTRST ((uint8_t)0x98)
722#define RCC_FLAG_IWDG1RST ((uint8_t)0x9A)
723#define RCC_FLAG_WWDG1RST ((uint8_t)0x9C)
724#define RCC_FLAG_LPWR1RST ((uint8_t)0x9E)
725#define RCC_FLAG_LPWR2RST ((uint8_t)0x9F)
726
727#if defined(DUAL_CORE)
728#define RCC_FLAG_C1RST (RCC_FLAG_CPURST)
729#define RCC_FLAG_C2RST ((uint8_t)0x92)
730#define RCC_FLAG_SFTR1ST (RCC_FLAG_SFTRST)
731#define RCC_FLAG_SFTR2ST ((uint8_t)0x99)
732#define RCC_FLAG_WWDG2RST ((uint8_t)0x9D)
733#define RCC_FLAG_IWDG2RST ((uint8_t)0x9B)
734#endif /*DUAL_CORE*/
735
736
745#define RCC_LSEDRIVE_LOW (0x00000000U)
746#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
747#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
748#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
757#define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U)
758#define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK
759
768#define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U)
769#define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK
770
771
776#if defined(RCC_VER_X)
777#define HAL_RCC_REV_Y_HSITRIM_Pos (12U)
778#define HAL_RCC_REV_Y_HSITRIM_Msk (0x3F000U)
779#define HAL_RCC_REV_Y_CSITRIM_Pos (26U)
780#define HAL_RCC_REV_Y_CSITRIM_Msk (0x7C000000U)
781#endif /* RCC_VER_X */
782
787/* Exported macros -----------------------------------------------------------*/
788
799#define __HAL_RCC_MDMA_CLK_ENABLE() do { \
800 __IO uint32_t tmpreg; \
801 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
802 /* Delay after an RCC peripheral clock enabling */ \
803 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
804 UNUSED(tmpreg); \
805 } while(0)
806
807#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
808 __IO uint32_t tmpreg; \
809 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
810 /* Delay after an RCC peripheral clock enabling */ \
811 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
812 UNUSED(tmpreg); \
813 } while(0)
814
815#if defined(JPEG)
816#define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \
817 __IO uint32_t tmpreg; \
818 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
819 /* Delay after an RCC peripheral clock enabling */ \
820 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
821 UNUSED(tmpreg); \
822 } while(0)
823#endif /* JPEG */
824
825#define __HAL_RCC_FMC_CLK_ENABLE() do { \
826 __IO uint32_t tmpreg; \
827 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
828 /* Delay after an RCC peripheral clock enabling */ \
829 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
830 UNUSED(tmpreg); \
831 } while(0)
832
833#if defined(QUADSPI)
834#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
835 __IO uint32_t tmpreg; \
836 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
837 /* Delay after an RCC peripheral clock enabling */ \
838 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
839 UNUSED(tmpreg); \
840 } while(0)
841#endif /* QUADSPI */
842#if defined(OCTOSPI1)
843#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \
844 __IO uint32_t tmpreg; \
845 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
846 /* Delay after an RCC peripheral clock enabling */ \
847 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\
848 UNUSED(tmpreg); \
849 } while(0)
850#endif /* OCTOSPI1 */
851#if defined(OCTOSPI2)
852#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \
853 __IO uint32_t tmpreg; \
854 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
855 /* Delay after an RCC peripheral clock enabling */ \
856 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\
857 UNUSED(tmpreg); \
858 } while(0)
859#endif /* OCTOSPI2 */
860#if defined(OCTOSPIM)
861#define __HAL_RCC_OCTOSPIM_CLK_ENABLE() do { \
862 __IO uint32_t tmpreg; \
863 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
864 /* Delay after an RCC peripheral clock enabling */ \
865 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\
866 UNUSED(tmpreg); \
867 } while(0)
868#endif /* OCTOSPIM */
869#if defined(OTFDEC1)
870#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \
871 __IO uint32_t tmpreg; \
872 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
873 /* Delay after an RCC peripheral clock enabling */ \
874 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\
875 UNUSED(tmpreg); \
876 } while(0)
877#endif /* OTFDEC1 */
878#if defined(OTFDEC2)
879#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \
880 __IO uint32_t tmpreg; \
881 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
882 /* Delay after an RCC peripheral clock enabling */ \
883 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\
884 UNUSED(tmpreg); \
885 } while(0)
886#endif /* OTFDEC2 */
887#if defined(GFXMMU)
888#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \
889 __IO uint32_t tmpreg; \
890 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
891 /* Delay after an RCC peripheral clock enabling */ \
892 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\
893 UNUSED(tmpreg); \
894 } while(0)
895#endif /* GFXMMU */
896#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
897 __IO uint32_t tmpreg; \
898 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
899 /* Delay after an RCC peripheral clock enabling */ \
900 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
901 UNUSED(tmpreg); \
902 } while(0)
903
904
905#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
906#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
907#if defined(JPEG)
908#define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
909#endif /* JPEG */
910#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
911
912#if defined(QUADSPI)
913#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
914#endif /* QUADSPI */
915#if defined(OCTOSPI1)
916#define __HAL_RCC_OSPI1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))
917#endif /* OCTOSPII */
918#if defined(OCTOSPI2)
919#define __HAL_RCC_OSPI2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))
920#endif /* OCTOSPI2 */
921#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
922#if defined(OCTOSPIM)
923#define __HAL_RCC_OCTOSPIM_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))
924#endif /* OCTOSPIM */
925#if defined(OTFDEC1)
926#define __HAL_RCC_OTFDEC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))
927#endif /* OTOFDEC1 */
928#if defined(OTFDEC2)
929#define __HAL_RCC_OTFDEC2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))
930#endif /* OTOFDEC2 */
931#if defined(GFXMMU)
932#define __HAL_RCC_GFXMMU_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))
933#endif /* GFXMMU */
934
941#define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U)
942#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U)
943#if defined(JPEG)
944#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)
945#endif /* JPEG */
946#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U)
947#if defined (QUADSPI)
948#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U)
949#endif /* QUADSPI */
950#if defined(OCTOSPI1)
951#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U)
952#endif /* OCTOSPII */
953#if defined(OCTOSPI2)
954#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U)
955#endif /* OCTOSPI2 */
956#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)
957#if defined(OCTOSPIM)
958#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)
959#endif /* OCTOSPIM */
960#if defined(OTFDEC1)
961#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)
962#endif /* OTOFDEC1 */
963#if defined(OTFDEC2)
964#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)
965#endif /* OTOFDEC2 */
966#if defined(GFXMMU)
967#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)
968#endif /* GFXMMU */
969
970#define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U)
971#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U)
972#if defined(JPEG)
973#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)
974#endif /* JPEG */
975#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U)
976#if defined (QUADSPI)
977#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U)
978#endif /* QUADSPI */
979#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)
980#if defined(OCTOSPI1)
981#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)
982#endif
983#if defined(OCTOSPI2)
984#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)
985#endif
986#if defined(OCTOSPIM)
987#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)
988#endif
989#if defined(OTFDEC1)
990#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)
991#endif
992#if defined(OTFDEC2)
993#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)
994#endif
995#if defined(GFXMMU)
996#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)
997#endif
1004#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
1005 __IO uint32_t tmpreg; \
1006 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
1007 /* Delay after an RCC peripheral clock enabling */ \
1008 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
1009 UNUSED(tmpreg); \
1010 } while(0)
1011
1012#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
1013 __IO uint32_t tmpreg; \
1014 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
1015 /* Delay after an RCC peripheral clock enabling */ \
1016 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
1017 UNUSED(tmpreg); \
1018 } while(0)
1019
1020#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
1021 __IO uint32_t tmpreg; \
1022 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
1023 /* Delay after an RCC peripheral clock enabling */ \
1024 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
1025 UNUSED(tmpreg); \
1026 } while(0)
1027
1028#if defined(DUAL_CORE)
1029#define __HAL_RCC_ART_CLK_ENABLE() do { \
1030 __IO uint32_t tmpreg; \
1031 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
1032 /* Delay after an RCC peripheral clock enabling */ \
1033 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\
1034 UNUSED(tmpreg); \
1035 } while(0)
1036#endif /*DUAL_CORE*/
1037
1038#if defined(RCC_AHB1ENR_CRCEN)
1039#define __HAL_RCC_CRC_CLK_ENABLE() do { \
1040 __IO uint32_t tmpreg; \
1041 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
1042 /* Delay after an RCC peripheral clock enabling */ \
1043 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
1044 UNUSED(tmpreg); \
1045 } while(0)
1046#endif
1047
1048#if defined(ETH)
1049#define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \
1050 __IO uint32_t tmpreg; \
1051 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
1052 /* Delay after an RCC peripheral clock enabling */ \
1053 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
1054 UNUSED(tmpreg); \
1055 } while(0)
1056
1057#define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \
1058 __IO uint32_t tmpreg; \
1059 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
1060 /* Delay after an RCC peripheral clock enabling */ \
1061 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
1062 UNUSED(tmpreg); \
1063 } while(0)
1064
1065#define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \
1066 __IO uint32_t tmpreg; \
1067 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
1068 /* Delay after an RCC peripheral clock enabling */ \
1069 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
1070 UNUSED(tmpreg); \
1071 } while(0)
1072#endif
1073
1074#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \
1075 __IO uint32_t tmpreg; \
1076 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
1077 /* Delay after an RCC peripheral clock enabling */ \
1078 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
1079 UNUSED(tmpreg); \
1080 } while(0)
1081
1082#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \
1083 __IO uint32_t tmpreg; \
1084 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
1085 /* Delay after an RCC peripheral clock enabling */ \
1086 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
1087 UNUSED(tmpreg); \
1088 } while(0)
1089
1090#if defined(USB2_OTG_FS)
1091#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \
1092 __IO uint32_t tmpreg; \
1093 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
1094 /* Delay after an RCC peripheral clock enabling */ \
1095 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
1096 UNUSED(tmpreg); \
1097 } while(0)
1098
1099#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \
1100 __IO uint32_t tmpreg; \
1101 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
1102 /* Delay after an RCC peripheral clock enabling */ \
1103 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
1104 UNUSED(tmpreg); \
1105 } while(0)
1106#endif
1107
1108#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
1109#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
1110#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
1111#if defined(DUAL_CORE)
1112#define __HAL_RCC_ART_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
1113#endif /*DUAL_CORE*/
1114#if defined(RCC_AHB1ENR_CRCEN)
1115#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))
1116#endif
1117#if defined(ETH)
1118#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
1119#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
1120#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
1121#endif
1122#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
1123#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
1124#if defined(USB2_OTG_FS)
1125#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
1126#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
1127#endif /* USB2_OTG_FS */
1128
1135#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U)
1136#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U)
1137#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U)
1138#if defined(DUAL_CORE)
1139#define __HAL_RCC_ART_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) != 0U)
1140#endif /*DUAL_CORE*/
1141#if defined(RCC_AHB1ENR_CRCEN)
1142#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) != 0U)
1143#endif
1144#if defined(ETH)
1145#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U)
1146#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U)
1147#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U)
1148#endif
1149#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U)
1150#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)
1151#if defined(USB2_OTG_FS)
1152#define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U)
1153#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U)
1154#endif /* USB2_OTG_FS */
1155
1156#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U)
1157#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U)
1158#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U)
1159#if defined(DUAL_CORE)
1160#define __HAL_RCC_ART_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) == 0U)
1161#endif /*DUAL_CORE*/
1162#if defined(RCC_AHB1ENR_CRCEN)
1163#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) == 0U)
1164#endif
1165#if defined(ETH)
1166#define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U)
1167#define __HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U)
1168#define __HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U)
1169#endif
1170#define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U)
1171#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)
1172#if defined(USB2_OTG_FS)
1173#define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U)
1174#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U)
1175#endif /* USB2_OTG_FS */
1176
1183#if defined(DCMI) && defined(PSSI)
1184#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \
1185 __IO uint32_t tmpreg; \
1186 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
1187 /* Delay after an RCC peripheral clock enabling */ \
1188 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\
1189 UNUSED(tmpreg); \
1190 } while(0)
1191
1192#define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility*/
1193#else
1194#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
1195 __IO uint32_t tmpreg; \
1196 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1197 /* Delay after an RCC peripheral clock enabling */ \
1198 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
1199 UNUSED(tmpreg); \
1200 } while(0)
1201#endif /* DCMI && PSSI */
1202
1203#if defined(CRYP)
1204#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
1205 __IO uint32_t tmpreg; \
1206 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1207 /* Delay after an RCC peripheral clock enabling */ \
1208 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
1209 UNUSED(tmpreg); \
1210 } while(0)
1211#endif /* CRYP */
1212
1213#if defined(HASH)
1214#define __HAL_RCC_HASH_CLK_ENABLE() do { \
1215 __IO uint32_t tmpreg; \
1216 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1217 /* Delay after an RCC peripheral clock enabling */ \
1218 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
1219 UNUSED(tmpreg); \
1220 } while(0)
1221#endif /* HASH */
1222
1223#define __HAL_RCC_RNG_CLK_ENABLE() do { \
1224 __IO uint32_t tmpreg; \
1225 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
1226 /* Delay after an RCC peripheral clock enabling */ \
1227 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
1228 UNUSED(tmpreg); \
1229 } while(0)
1230
1231#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
1232 __IO uint32_t tmpreg; \
1233 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
1234 /* Delay after an RCC peripheral clock enabling */ \
1235 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
1236 UNUSED(tmpreg); \
1237 } while(0)
1238
1239#if defined(FMAC)
1240#define __HAL_RCC_FMAC_CLK_ENABLE() do { \
1241 __IO uint32_t tmpreg; \
1242 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\
1243 /* Delay after an RCC peripheral clock enabling */ \
1244 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\
1245 UNUSED(tmpreg); \
1246 } while(0)
1247#endif /* FMAC */
1248
1249#if defined(CORDIC)
1250#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \
1251 __IO uint32_t tmpreg; \
1252 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\
1253 /* Delay after an RCC peripheral clock enabling */ \
1254 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\
1255 UNUSED(tmpreg); \
1256 } while(0)
1257#endif /* CORDIC */
1258
1259#if defined(RCC_AHB2ENR_D2SRAM1EN)
1260#define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \
1261 __IO uint32_t tmpreg; \
1262 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
1263 /* Delay after an RCC peripheral clock enabling */ \
1264 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
1265 UNUSED(tmpreg); \
1266 } while(0)
1267#else
1268#define __HAL_RCC_AHBSRAM1_CLK_ENABLE() do { \
1269 __IO uint32_t tmpreg; \
1270 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
1271 /* Delay after an RCC peripheral clock enabling */ \
1272 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
1273 UNUSED(tmpreg); \
1274 } while(0)
1275#endif /* RCC_AHB2ENR_D2SRAM1EN */
1276
1277#if defined(RCC_AHB2ENR_D2SRAM2EN)
1278#define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \
1279 __IO uint32_t tmpreg; \
1280 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
1281 /* Delay after an RCC peripheral clock enabling */ \
1282 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
1283 UNUSED(tmpreg); \
1284 } while(0)
1285#else
1286#define __HAL_RCC_AHBSRAM2_CLK_ENABLE() do { \
1287 __IO uint32_t tmpreg; \
1288 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
1289 /* Delay after an RCC peripheral clock enabling */ \
1290 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
1291 UNUSED(tmpreg); \
1292 } while(0)
1293#endif /* RCC_AHB2ENR_D2SRAM2EN */
1294
1295#if defined(RCC_AHB2ENR_D2SRAM3EN)
1296#define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \
1297 __IO uint32_t tmpreg; \
1298 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
1299 /* Delay after an RCC peripheral clock enabling */ \
1300 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
1301 UNUSED(tmpreg); \
1302 } while(0)
1303#endif
1304
1305#if defined(RCC_AHB2ENR_HSEMEN)
1306#define __HAL_RCC_HSEM_CLK_ENABLE() do { \
1307 __IO uint32_t tmpreg; \
1308 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
1309 /* Delay after an RCC peripheral clock enabling */ \
1310 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\
1311 UNUSED(tmpreg); \
1312 } while(0)
1313#endif /* RCC_AHB2ENR_HSEMEN */
1314
1315#if defined(BDMA1)
1316#define __HAL_RCC_BDMA1_CLK_ENABLE() do { \
1317 __IO uint32_t tmpreg; \
1318 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
1319 /* Delay after an RCC peripheral clock enabling */ \
1320 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\
1321 UNUSED(tmpreg); \
1322 } while(0)
1323#endif /* BDMA1 */
1324
1325#if defined(DCMI) && defined(PSSI)
1326#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))
1327#define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/
1328#else
1329#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
1330#endif /* DCMI && PSSI */
1331#if defined(CRYP)
1332#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
1333#endif /* CRYP */
1334#if defined(HASH)
1335#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
1336#endif /* HASH */
1337#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
1338#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
1339#if defined(FMAC)
1340#define __HAL_RCC_FMAC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_FMACEN))
1341#endif /* FMAC */
1342#if defined(CORDIC)
1343#define __HAL_RCC_CORDIC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CORDICEN))
1344#endif /* CORDIC */
1345#if defined(RCC_AHB2ENR_D2SRAM1EN)
1346#define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
1347#else
1348#define __HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))
1349#endif /* RCC_AHB2ENR_D2SRAM1EN */
1350#if defined(RCC_AHB2ENR_D2SRAM2EN)
1351#define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
1352#else
1353#define __HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))
1354#endif /* RCC_AHB2ENR_D2SRAM2EN */
1355#if defined(RCC_AHB2ENR_D2SRAM3EN)
1356#define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
1357#endif
1358#if defined(RCC_AHB2ENR_HSEMEN)
1359#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))
1360#endif
1361#if defined(BDMA1)
1362#define __HAL_RCC_BDMA1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))
1363#endif
1364
1371#if defined(DCMI) && defined(PSSI)
1372#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) != 0U)
1373#define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility*/
1374#else
1375#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U)
1376#endif /* DCMI && PSSI */
1377#if defined(CRYP)
1378#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U)
1379#endif /* CRYP */
1380#if defined(HASH)
1381#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U)
1382#endif /* HASH */
1383#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)
1384#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)
1385#if defined(FMAC)
1386#define __HAL_RCC_FMAC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) != 0U)
1387#endif /* FMAC */
1388#if defined(CORDIC)
1389#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) != 0U)
1390#endif /* CORDIC */
1391#if defined(RCC_AHB2ENR_D2SRAM1EN)
1392#define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)
1393#else
1394#define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)
1395#endif /* RCC_AHB2ENR_D2SRAM1EN */
1396#if defined(RCC_AHB2ENR_D2SRAM2EN)
1397#define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U)
1398#else
1399#define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)
1400#endif /* RCC_AHB2ENR_D2SRAM2EN */
1401#if defined(RCC_AHB2ENR_D2SRAM3EN)
1402#define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U)
1403#endif
1404#if defined(RCC_AHB2ENR_HSEMEN)
1405#define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) != 0U)
1406#endif
1407#if defined(BDMA1)
1408#define __HAL_RCC_BDMA1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) != 0U)
1409#endif
1410
1411#if defined(DCMI) && defined(PSSI)
1412#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) == 0U)
1413#define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility*/
1414#else
1415#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U)
1416#endif /* DCMI && PSSI */
1417#if defined(CRYP)
1418#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U)
1419#endif /* CRYP */
1420#if defined(HASH)
1421#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U)
1422#endif /* HASH */
1423#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)
1424#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)
1425#if defined(FMAC)
1426#define __HAL_RCC_FMAC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) == 0U)
1427#endif /* FMAC */
1428#if defined(CORDIC)
1429#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) == 0U)
1430#endif /* CORDIC */
1431#if defined(RCC_AHB2ENR_D2SRAM1EN)
1432#define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)
1433#else
1434#define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)
1435#endif /* RCC_AHB2ENR_D2SRAM1EN */
1436#if defined(RCC_AHB2ENR_D2SRAM2EN)
1437#define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U)
1438#else
1439#define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)
1440#endif /* RCC_AHB2ENR_D2SRAM2EN */
1441#if defined(RCC_AHB2ENR_D2SRAM3EN)
1442#define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U)
1443#endif
1444#if defined(RCC_AHB2ENR_HSEMEN)
1445#define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) == 0U)
1446#endif
1447#if defined(BDMA1)
1448#define __HAL_RCC_BDMA1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) == 0U)
1449#endif
1450
1457#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
1458 __IO uint32_t tmpreg; \
1459 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
1460 /* Delay after an RCC peripheral clock enabling */ \
1461 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
1462 UNUSED(tmpreg); \
1463 } while(0)
1464
1465#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
1466 __IO uint32_t tmpreg; \
1467 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
1468 /* Delay after an RCC peripheral clock enabling */ \
1469 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
1470 UNUSED(tmpreg); \
1471 } while(0)
1472
1473#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
1474 __IO uint32_t tmpreg; \
1475 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
1476 /* Delay after an RCC peripheral clock enabling */ \
1477 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
1478 UNUSED(tmpreg); \
1479 } while(0)
1480
1481#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
1482 __IO uint32_t tmpreg; \
1483 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
1484 /* Delay after an RCC peripheral clock enabling */ \
1485 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
1486 UNUSED(tmpreg); \
1487 } while(0)
1488
1489#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
1490 __IO uint32_t tmpreg; \
1491 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
1492 /* Delay after an RCC peripheral clock enabling */ \
1493 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
1494 UNUSED(tmpreg); \
1495 } while(0)
1496
1497#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
1498 __IO uint32_t tmpreg; \
1499 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
1500 /* Delay after an RCC peripheral clock enabling */ \
1501 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
1502 UNUSED(tmpreg); \
1503 } while(0)
1504
1505#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1506 __IO uint32_t tmpreg; \
1507 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
1508 /* Delay after an RCC peripheral clock enabling */ \
1509 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
1510 UNUSED(tmpreg); \
1511 } while(0)
1512
1513#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
1514 __IO uint32_t tmpreg; \
1515 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
1516 /* Delay after an RCC peripheral clock enabling */ \
1517 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
1518 UNUSED(tmpreg); \
1519 } while(0)
1520
1521#if defined(GPIOI)
1522#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
1523 __IO uint32_t tmpreg; \
1524 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
1525 /* Delay after an RCC peripheral clock enabling */ \
1526 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
1527 UNUSED(tmpreg); \
1528 } while(0)
1529#endif /* GPIOI */
1530
1531#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
1532 __IO uint32_t tmpreg; \
1533 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
1534 /* Delay after an RCC peripheral clock enabling */ \
1535 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
1536 UNUSED(tmpreg); \
1537 } while(0)
1538
1539#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
1540 __IO uint32_t tmpreg; \
1541 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
1542 /* Delay after an RCC peripheral clock enabling */ \
1543 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
1544 UNUSED(tmpreg); \
1545 } while(0)
1546
1547#if defined(RCC_AHB4ENR_CRCEN)
1548#define __HAL_RCC_CRC_CLK_ENABLE() do { \
1549 __IO uint32_t tmpreg; \
1550 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
1551 /* Delay after an RCC peripheral clock enabling */ \
1552 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
1553 UNUSED(tmpreg); \
1554 } while(0)
1555#endif
1556
1557#if defined(BDMA2)
1558#define __HAL_RCC_BDMA2_CLK_ENABLE() do { \
1559 __IO uint32_t tmpreg; \
1560 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
1561 /* Delay after an RCC peripheral clock enabling */ \
1562 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\
1563 UNUSED(tmpreg); \
1564 } while(0)
1565
1566#define __HAL_RCC_BDMA_CLK_ENABLE() __HAL_RCC_BDMA2_CLK_ENABLE() /* for API backward compatibility*/
1567#else
1568#define __HAL_RCC_BDMA_CLK_ENABLE() do { \
1569 __IO uint32_t tmpreg; \
1570 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
1571 /* Delay after an RCC peripheral clock enabling */ \
1572 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
1573 UNUSED(tmpreg); \
1574 } while(0)
1575#endif
1576
1577#if defined(ADC3)
1578#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
1579 __IO uint32_t tmpreg; \
1580 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
1581 /* Delay after an RCC peripheral clock enabling */ \
1582 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
1583 UNUSED(tmpreg); \
1584 } while(0)
1585#endif
1586
1587#if defined(RCC_AHB4ENR_HSEMEN)
1588#define __HAL_RCC_HSEM_CLK_ENABLE() do { \
1589 __IO uint32_t tmpreg; \
1590 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
1591 /* Delay after an RCC peripheral clock enabling */ \
1592 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
1593 UNUSED(tmpreg); \
1594 } while(0)
1595#endif
1596
1597#if defined(RCC_AHB4ENR_SRDSRAMEN)
1598#define __HAL_RCC_SRDSRAM_CLK_ENABLE() do { \
1599 __IO uint32_t tmpreg; \
1600 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
1601 /* Delay after an RCC peripheral clock enabling */ \
1602 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\
1603 UNUSED(tmpreg); \
1604 } while(0)
1605#endif
1606
1607#define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \
1608 __IO uint32_t tmpreg; \
1609 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
1610 /* Delay after an RCC peripheral clock enabling */ \
1611 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
1612 UNUSED(tmpreg); \
1613 } while(0)
1614
1615
1616#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
1617#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
1618#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
1619#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
1620#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
1621#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
1622#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
1623#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
1624#if defined(GPIOI)
1625#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
1626#endif /* GPIOI */
1627#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
1628#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
1629#if defined(RCC_AHB4ENR_CRCEN)
1630#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
1631#endif
1632#if defined(BDMA2)
1633#define __HAL_RCC_BDMA2_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)
1634#define __HAL_RCC_BDMA_CLK_DISABLE() __HAL_RCC_BDMA2_CLK_DISABLE() /* for API backward compatibility*/
1635#else
1636#define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
1637#endif
1638#if defined(ADC3)
1639#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
1640#endif
1641#if defined(RCC_AHB4ENR_HSEMEN)
1642#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
1643#endif
1644#if defined(RCC_AHB4ENR_SRDSRAMEN)
1645#define __HAL_RCC_SRDSRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)
1646#endif
1647#define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
1648
1649
1656#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U)
1657#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U)
1658#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U)
1659#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U)
1660#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U)
1661#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U)
1662#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U)
1663#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U)
1664#if defined(GPIOI)
1665#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U)
1666#endif /* GPIOI */
1667#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U)
1668#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U)
1669#if defined(RCC_AHB4ENR_CRCEN)
1670#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U)
1671#endif
1672#if defined(BDMA2)
1673#define __HAL_RCC_BDMA2_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) != 0U)
1674#define __HAL_RCC_BDMA_IS_CLK_ENABLED() __HAL_RCC_BDMA2_IS_CLK_ENABLED() /* for API backward compatibility*/
1675#else
1676#define __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U)
1677#endif
1678#if defined(ADC3)
1679#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U)
1680#endif
1681#if defined(RCC_AHB4ENR_HSEMEN)
1682#define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U)
1683#endif
1684#if defined(RCC_AHB4ENR_SRDSRAMEN)
1685#define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)
1686#endif
1687#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)
1688
1689#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U)
1690#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U)
1691#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U)
1692#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U)
1693#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U)
1694#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U)
1695#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U)
1696#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U)
1697#if defined(GPIOI)
1698#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U)
1699#endif /* GPIOI */
1700#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U)
1701#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U)
1702
1703#if defined(RCC_AHB4ENR_CRCEN)
1704#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U)
1705#endif
1706#if defined(BDMA2)
1707#define __HAL_RCC_BDMA2_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) == 0U)
1708#define __HAL_RCC_BDMA_IS_CLK_DISABLED() __HAL_RCC_BDMA2_IS_CLK_DISABLED() /* for API backward compatibility*/
1709#else
1710#define __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U)
1711#endif
1712#if defined(ADC3)
1713#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U)
1714#endif
1715#if defined(RCC_AHB4ENR_HSEMEN)
1716#define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U)
1717#endif
1718#if defined(RCC_AHB4ENR_SRDSRAMEN)
1719#define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) == 0U)
1720#endif
1721#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)
1722
1723
1730#if defined(LTDC)
1731#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
1732 __IO uint32_t tmpreg; \
1733 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
1734 /* Delay after an RCC peripheral clock enabling */ \
1735 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\
1736 UNUSED(tmpreg); \
1737 } while(0)
1738#endif /* LTDC */
1739
1740#if defined(DSI)
1741#define __HAL_RCC_DSI_CLK_ENABLE() do { \
1742 __IO uint32_t tmpreg; \
1743 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
1744 /* Delay after an RCC peripheral clock enabling */ \
1745 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\
1746 UNUSED(tmpreg); \
1747 } while(0)
1748#endif /*DSI*/
1749
1750#define __HAL_RCC_WWDG1_CLK_ENABLE() do { \
1751 __IO uint32_t tmpreg; \
1752 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
1753 /* Delay after an RCC peripheral clock enabling */ \
1754 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
1755 UNUSED(tmpreg); \
1756 } while(0)
1757
1758#if defined(LTDC)
1759#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
1760#endif /* LTDC */
1761#if defined(DSI)
1762#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
1763#endif /*DSI*/
1764#define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
1765
1772#if defined(LTDC)
1773#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U)
1774#endif /* LTDC */
1775#if defined(DSI)
1776#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) != 0U)
1777#endif /*DSI*/
1778#define __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
1779#if defined(LTDC)
1780#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U)
1781#endif /* LTDC */
1782#if defined(DSI)
1783#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) == 0U)
1784#endif /*DSI*/
1785#define __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)
1786
1787
1794#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
1795 __IO uint32_t tmpreg; \
1796 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
1797 /* Delay after an RCC peripheral clock enabling */ \
1798 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
1799 UNUSED(tmpreg); \
1800 } while(0)
1801
1802#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
1803 __IO uint32_t tmpreg; \
1804 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
1805 /* Delay after an RCC peripheral clock enabling */ \
1806 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
1807 UNUSED(tmpreg); \
1808 } while(0)
1809
1810#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
1811 __IO uint32_t tmpreg; \
1812 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
1813 /* Delay after an RCC peripheral clock enabling */ \
1814 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
1815 UNUSED(tmpreg); \
1816 } while(0)
1817
1818#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
1819 __IO uint32_t tmpreg; \
1820 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
1821 /* Delay after an RCC peripheral clock enabling */ \
1822 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
1823 UNUSED(tmpreg); \
1824 } while(0)
1825
1826#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
1827 __IO uint32_t tmpreg; \
1828 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
1829 /* Delay after an RCC peripheral clock enabling */ \
1830 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
1831 UNUSED(tmpreg); \
1832 } while(0)
1833
1834#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
1835 __IO uint32_t tmpreg; \
1836 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
1837 /* Delay after an RCC peripheral clock enabling */ \
1838 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
1839 UNUSED(tmpreg); \
1840 } while(0)
1841
1842#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
1843 __IO uint32_t tmpreg; \
1844 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
1845 /* Delay after an RCC peripheral clock enabling */ \
1846 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
1847 UNUSED(tmpreg); \
1848 } while(0)
1849
1850#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
1851 __IO uint32_t tmpreg; \
1852 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
1853 /* Delay after an RCC peripheral clock enabling */ \
1854 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
1855 UNUSED(tmpreg); \
1856 } while(0)
1857
1858#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1859 __IO uint32_t tmpreg; \
1860 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
1861 /* Delay after an RCC peripheral clock enabling */ \
1862 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
1863 UNUSED(tmpreg); \
1864 } while(0)
1865
1866#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
1867 __IO uint32_t tmpreg; \
1868 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
1869 /* Delay after an RCC peripheral clock enabling */ \
1870 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
1871 UNUSED(tmpreg); \
1872 } while(0)
1873
1874#if defined(DUAL_CORE)
1875#define __HAL_RCC_WWDG2_CLK_ENABLE() do { \
1876 __IO uint32_t tmpreg; \
1877 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
1878 /* Delay after an RCC peripheral clock enabling */ \
1879 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\
1880 UNUSED(tmpreg); \
1881 } while(0)
1882#endif /*DUAL_CORE*/
1883
1884#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
1885 __IO uint32_t tmpreg; \
1886 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
1887 /* Delay after an RCC peripheral clock enabling */ \
1888 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
1889 UNUSED(tmpreg); \
1890 } while(0)
1891
1892#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
1893 __IO uint32_t tmpreg; \
1894 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
1895 /* Delay after an RCC peripheral clock enabling */ \
1896 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
1897 UNUSED(tmpreg); \
1898 } while(0)
1899
1900#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
1901 __IO uint32_t tmpreg; \
1902 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
1903 /* Delay after an RCC peripheral clock enabling */ \
1904 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
1905 UNUSED(tmpreg); \
1906 } while(0)
1907
1908#define __HAL_RCC_USART2_CLK_ENABLE() do { \
1909 __IO uint32_t tmpreg; \
1910 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
1911 /* Delay after an RCC peripheral clock enabling */ \
1912 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
1913 UNUSED(tmpreg); \
1914 } while(0)
1915
1916#define __HAL_RCC_USART3_CLK_ENABLE() do { \
1917 __IO uint32_t tmpreg; \
1918 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
1919 /* Delay after an RCC peripheral clock enabling */ \
1920 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
1921 UNUSED(tmpreg); \
1922 } while(0)
1923
1924#define __HAL_RCC_UART4_CLK_ENABLE() do { \
1925 __IO uint32_t tmpreg; \
1926 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
1927 /* Delay after an RCC peripheral clock enabling */ \
1928 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
1929 UNUSED(tmpreg); \
1930 } while(0)
1931
1932#define __HAL_RCC_UART5_CLK_ENABLE() do { \
1933 __IO uint32_t tmpreg; \
1934 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
1935 /* Delay after an RCC peripheral clock enabling */ \
1936 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
1937 UNUSED(tmpreg); \
1938 } while(0)
1939
1940#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
1941 __IO uint32_t tmpreg; \
1942 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
1943 /* Delay after an RCC peripheral clock enabling */ \
1944 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
1945 UNUSED(tmpreg); \
1946 } while(0)
1947
1948#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
1949 __IO uint32_t tmpreg; \
1950 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
1951 /* Delay after an RCC peripheral clock enabling */ \
1952 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
1953 UNUSED(tmpreg); \
1954 } while(0)
1955
1956#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
1957 __IO uint32_t tmpreg; \
1958 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
1959 /* Delay after an RCC peripheral clock enabling */ \
1960 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
1961 UNUSED(tmpreg); \
1962 } while(0)
1963
1964#if defined(I2C5)
1965#define __HAL_RCC_I2C5_CLK_ENABLE() do { \
1966 __IO uint32_t tmpreg; \
1967 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\
1968 /* Delay after an RCC peripheral clock enabling */ \
1969 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\
1970 UNUSED(tmpreg); \
1971 } while(0)
1972#endif /* I2C5 */
1973
1974#define __HAL_RCC_CEC_CLK_ENABLE() do { \
1975 __IO uint32_t tmpreg; \
1976 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
1977 /* Delay after an RCC peripheral clock enabling */ \
1978 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
1979 UNUSED(tmpreg); \
1980 } while(0)
1981
1982#define __HAL_RCC_DAC12_CLK_ENABLE() do { \
1983 __IO uint32_t tmpreg; \
1984 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
1985 /* Delay after an RCC peripheral clock enabling */ \
1986 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
1987 UNUSED(tmpreg); \
1988 } while(0)
1989
1990#define __HAL_RCC_UART7_CLK_ENABLE() do { \
1991 __IO uint32_t tmpreg; \
1992 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
1993 /* Delay after an RCC peripheral clock enabling */ \
1994 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
1995 UNUSED(tmpreg); \
1996 } while(0)
1997
1998#define __HAL_RCC_UART8_CLK_ENABLE() do { \
1999 __IO uint32_t tmpreg; \
2000 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
2001 /* Delay after an RCC peripheral clock enabling */ \
2002 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
2003 UNUSED(tmpreg); \
2004 } while(0)
2005
2006#define __HAL_RCC_CRS_CLK_ENABLE() do { \
2007 __IO uint32_t tmpreg; \
2008 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
2009 /* Delay after an RCC peripheral clock enabling */ \
2010 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
2011 UNUSED(tmpreg); \
2012 } while(0)
2013
2014#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
2015 __IO uint32_t tmpreg; \
2016 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
2017 /* Delay after an RCC peripheral clock enabling */ \
2018 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
2019 UNUSED(tmpreg); \
2020 } while(0)
2021
2022#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
2023 __IO uint32_t tmpreg; \
2024 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
2025 /* Delay after an RCC peripheral clock enabling */ \
2026 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
2027 UNUSED(tmpreg); \
2028 } while(0)
2029
2030#define __HAL_RCC_MDIOS_CLK_ENABLE() do { \
2031 __IO uint32_t tmpreg; \
2032 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
2033 /* Delay after an RCC peripheral clock enabling */ \
2034 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
2035 UNUSED(tmpreg); \
2036 } while(0)
2037
2038#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \
2039 __IO uint32_t tmpreg; \
2040 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
2041 /* Delay after an RCC peripheral clock enabling */ \
2042 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
2043 UNUSED(tmpreg); \
2044 } while(0)
2045
2046#if defined(TIM23)
2047#define __HAL_RCC_TIM23_CLK_ENABLE() do { \
2048 __IO uint32_t tmpreg; \
2049 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\
2050 /* Delay after an RCC peripheral clock enabling */ \
2051 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\
2052 UNUSED(tmpreg); \
2053 } while(0)
2054#endif /* TIM23 */
2055
2056#if defined(TIM24)
2057#define __HAL_RCC_TIM24_CLK_ENABLE() do { \
2058 __IO uint32_t tmpreg; \
2059 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\
2060 /* Delay after an RCC peripheral clock enabling */ \
2061 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\
2062 UNUSED(tmpreg); \
2063 } while(0)
2064#endif /* TIM24 */
2065
2066#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
2067#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
2068#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
2069#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
2070#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
2071#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
2072#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
2073#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
2074#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
2075#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
2076
2077#if defined(DUAL_CORE)
2078#define __HAL_RCC_WWDG2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
2079#endif /*DUAL_CORE*/
2080
2081#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
2082#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
2083#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
2084#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
2085#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
2086#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
2087#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
2088#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
2089#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
2090#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
2091#if defined(I2C5)
2092#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C5EN)
2093#endif /* I2C5 */
2094#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
2095#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
2096#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
2097#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
2098#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
2099#define __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
2100#define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
2101#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
2102#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
2103#if defined(TIM23)
2104#define __HAL_RCC_TIM23_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM23EN)
2105#endif /* TIM23 */
2106#if defined(TIM24)
2107#define __HAL_RCC_TIM24_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM24EN)
2108#endif /* TIM24 */
2109
2110
2117#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U)
2118#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U)
2119#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U)
2120#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U)
2121#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U)
2122#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U)
2123#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U)
2124#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U)
2125#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U)
2126#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U)
2127#if defined(DUAL_CORE)
2128#define __HAL_RCC_WWDG2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) != 0U)
2129#endif /*DUAL_CORE*/
2130#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U)
2131#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U)
2132#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)
2133#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U)
2134#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U)
2135#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U)
2136#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U)
2137#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U)
2138#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U)
2139#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U)
2140#if defined(I2C5)
2141#define __HAL_RCC_I2C5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) != 0U)
2142#endif /* I2C5 */
2143#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U)
2144#define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U)
2145#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U)
2146#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U)
2147#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U)
2148#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U)
2149#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U)
2150#define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U)
2151#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U)
2152#if defined(TIM23)
2153#define __HAL_RCC_TIM23_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) != 0U)
2154#endif /* TIM23 */
2155#if defined(TIM24)
2156#define __HAL_RCC_TIM24_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) != 0U)
2157#endif /* TIM24 */
2158
2159#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U)
2160#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U)
2161#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U)
2162#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U)
2163#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U)
2164#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U)
2165#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U)
2166#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U)
2167#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U)
2168#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U)
2169#if defined(DUAL_CORE)
2170#define __HAL_RCC_WWDG2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) == 0U)
2171#endif /*DUAL_CORE*/
2172#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U)
2173#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U)
2174#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)
2175#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U)
2176#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U)
2177#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U)
2178#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U)
2179#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U)
2180#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U)
2181#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U)
2182#if defined(I2C5)
2183#define __HAL_RCC_I2C5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) == 0U)
2184#endif /* I2C5 */
2185#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U)
2186#define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U)
2187#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U)
2188#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U)
2189#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U)
2190#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U)
2191#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U)
2192#define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U)
2193#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U)
2194#if defined(TIM23)
2195#define __HAL_RCC_TIM23_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) == 0U)
2196#endif /* TIM23 */
2197#if defined(TIM24)
2198#define __HAL_RCC_TIM24_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) == 0U)
2199#endif /* TIM24 */
2200
2201
2208#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
2209 __IO uint32_t tmpreg; \
2210 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
2211 /* Delay after an RCC peripheral clock enabling */ \
2212 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
2213 UNUSED(tmpreg); \
2214 } while(0)
2215
2216#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
2217 __IO uint32_t tmpreg; \
2218 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2219 /* Delay after an RCC peripheral clock enabling */ \
2220 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
2221 UNUSED(tmpreg); \
2222 } while(0)
2223
2224#define __HAL_RCC_USART1_CLK_ENABLE() do { \
2225 __IO uint32_t tmpreg; \
2226 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
2227 /* Delay after an RCC peripheral clock enabling */ \
2228 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
2229 UNUSED(tmpreg); \
2230 } while(0)
2231
2232#define __HAL_RCC_USART6_CLK_ENABLE() do { \
2233 __IO uint32_t tmpreg; \
2234 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
2235 /* Delay after an RCC peripheral clock enabling */ \
2236 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
2237 UNUSED(tmpreg); \
2238 } while(0)
2239
2240#if defined(UART9)
2241#define __HAL_RCC_UART9_CLK_ENABLE() do { \
2242 __IO uint32_t tmpreg; \
2243 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
2244 /* Delay after an RCC peripheral clock enabling */ \
2245 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
2246 UNUSED(tmpreg); \
2247 } while(0)
2248#endif /*UART9*/
2249
2250#if defined(USART10)
2251#define __HAL_RCC_USART10_CLK_ENABLE() do { \
2252 __IO uint32_t tmpreg; \
2253 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
2254 /* Delay after an RCC peripheral clock enabling */ \
2255 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\
2256 UNUSED(tmpreg); \
2257 } while(0)
2258#endif /*USART10*/
2259
2260#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
2261 __IO uint32_t tmpreg; \
2262 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2263 /* Delay after an RCC peripheral clock enabling */ \
2264 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
2265 UNUSED(tmpreg); \
2266 } while(0)
2267
2268#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
2269 __IO uint32_t tmpreg; \
2270 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2271 /* Delay after an RCC peripheral clock enabling */ \
2272 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
2273 UNUSED(tmpreg); \
2274 } while(0)
2275
2276#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
2277 __IO uint32_t tmpreg; \
2278 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
2279 /* Delay after an RCC peripheral clock enabling */ \
2280 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
2281 UNUSED(tmpreg); \
2282 } while(0)
2283
2284#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
2285 __IO uint32_t tmpreg; \
2286 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
2287 /* Delay after an RCC peripheral clock enabling */ \
2288 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
2289 UNUSED(tmpreg); \
2290 } while(0)
2291
2292#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
2293 __IO uint32_t tmpreg; \
2294 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
2295 /* Delay after an RCC peripheral clock enabling */ \
2296 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
2297 UNUSED(tmpreg); \
2298 } while(0)
2299
2300#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
2301 __IO uint32_t tmpreg; \
2302 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
2303 /* Delay after an RCC peripheral clock enabling */ \
2304 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
2305 UNUSED(tmpreg); \
2306 } while(0)
2307
2308#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
2309 __IO uint32_t tmpreg; \
2310 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
2311 /* Delay after an RCC peripheral clock enabling */ \
2312 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
2313 UNUSED(tmpreg); \
2314 } while(0)
2315
2316#if defined(SAI2)
2317#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
2318 __IO uint32_t tmpreg; \
2319 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
2320 /* Delay after an RCC peripheral clock enabling */ \
2321 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
2322 UNUSED(tmpreg); \
2323 } while(0)
2324#endif /*SAI2*/
2325
2326#if defined(SAI3)
2327#define __HAL_RCC_SAI3_CLK_ENABLE() do { \
2328 __IO uint32_t tmpreg; \
2329 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
2330 /* Delay after an RCC peripheral clock enabling */ \
2331 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\
2332 UNUSED(tmpreg); \
2333 } while(0)
2334#endif /*SAI3*/
2335
2336#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
2337 __IO uint32_t tmpreg; \
2338 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
2339 /* Delay after an RCC peripheral clock enabling */ \
2340 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
2341 UNUSED(tmpreg); \
2342 } while(0)
2343
2344#if defined(HRTIM1)
2345#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
2346 __IO uint32_t tmpreg; \
2347 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
2348 /* Delay after an RCC peripheral clock enabling */ \
2349 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\
2350 UNUSED(tmpreg); \
2351 } while(0)
2352#endif /*HRTIM1*/
2353
2354#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
2355#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
2356#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
2357#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
2358#if defined(UART9)
2359#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)
2360#endif /*UART9*/
2361#if defined(USART10)
2362#define __HAL_RCC_USART10_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)
2363#endif /*USART10*/
2364#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
2365#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
2366#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
2367#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
2368#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
2369#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
2370#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
2371#if defined(SAI2)
2372#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
2373#endif /*SAI2*/
2374#if defined(SAI3)
2375#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
2376#endif /*SAI3*/
2377#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
2378#if defined(HRTIM1)
2379#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
2380#endif /*HRTIM*/
2381
2388#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U)
2389#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U)
2390#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)
2391#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)
2392#if defined(UART9)
2393#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)
2394#endif /*UART9*/
2395#if defined(USART10)
2396#define __HAL_RCC_USART10_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)
2397#endif /*USART10*/
2398#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U)
2399#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U)
2400#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U)
2401#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U)
2402#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U)
2403#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)
2404#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U)
2405#if defined(SAI2)
2406#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U)
2407#endif /*SAI2*/
2408#if defined(SAI3)
2409#define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U)
2410#endif /* SAI3 */
2411#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)
2412#if defined(HRTIM1)
2413#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U)
2414#endif /*HRTIM1*/
2415
2416#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U)
2417#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U)
2418#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)
2419#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)
2420#if defined(UART9)
2421#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)
2422#endif /*UART9*/
2423#if defined(USART10)
2424#define __HAL_RCC_USART10_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)
2425#endif /*USART10*/
2426#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U)
2427#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U)
2428#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U)
2429#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U)
2430#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U)
2431#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)
2432#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U)
2433#if defined(SAI2)
2434#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U)
2435#endif /*SAI2*/
2436#if defined(SAI3)
2437#define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U)
2438#endif /*SAI3*/
2439#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)
2440#if defined(HRTIM1)
2441#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U)
2442#endif /*HRTIM1*/
2443
2450#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
2451 __IO uint32_t tmpreg; \
2452 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
2453 /* Delay after an RCC peripheral clock enabling */ \
2454 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
2455 UNUSED(tmpreg); \
2456 } while(0)
2457
2458#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
2459 __IO uint32_t tmpreg; \
2460 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
2461 /* Delay after an RCC peripheral clock enabling */ \
2462 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
2463 UNUSED(tmpreg); \
2464 } while(0)
2465
2466#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
2467 __IO uint32_t tmpreg; \
2468 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
2469 /* Delay after an RCC peripheral clock enabling */ \
2470 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
2471 UNUSED(tmpreg); \
2472 } while(0)
2473
2474#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
2475 __IO uint32_t tmpreg; \
2476 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
2477 /* Delay after an RCC peripheral clock enabling */ \
2478 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
2479 UNUSED(tmpreg); \
2480 } while(0)
2481
2482#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
2483 __IO uint32_t tmpreg; \
2484 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
2485 /* Delay after an RCC peripheral clock enabling */ \
2486 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
2487 UNUSED(tmpreg); \
2488 } while(0)
2489
2490#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \
2491 __IO uint32_t tmpreg; \
2492 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
2493 /* Delay after an RCC peripheral clock enabling */ \
2494 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
2495 UNUSED(tmpreg); \
2496 } while(0)
2497
2498#if defined(LPTIM4)
2499#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \
2500 __IO uint32_t tmpreg; \
2501 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
2502 /* Delay after an RCC peripheral clock enabling */ \
2503 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
2504 UNUSED(tmpreg); \
2505 } while(0)
2506#endif /* LPTIM4 */
2507
2508#if defined(LPTIM5)
2509#define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \
2510 __IO uint32_t tmpreg; \
2511 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
2512 /* Delay after an RCC peripheral clock enabling */ \
2513 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
2514 UNUSED(tmpreg); \
2515 } while(0)
2516#endif /* LPTIM5 */
2517
2518#if defined(DAC2)
2519#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
2520 __IO uint32_t tmpreg; \
2521 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
2522 /* Delay after an RCC peripheral clock enabling */ \
2523 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\
2524 UNUSED(tmpreg); \
2525 } while(0)
2526#endif /* DAC2 */
2527
2528#define __HAL_RCC_COMP12_CLK_ENABLE() do { \
2529 __IO uint32_t tmpreg; \
2530 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
2531 /* Delay after an RCC peripheral clock enabling */ \
2532 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
2533 UNUSED(tmpreg); \
2534 } while(0)
2535
2536#define __HAL_RCC_VREF_CLK_ENABLE() do { \
2537 __IO uint32_t tmpreg; \
2538 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
2539 /* Delay after an RCC peripheral clock enabling */ \
2540 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
2541 UNUSED(tmpreg); \
2542 } while(0)
2543
2544#if defined(SAI4)
2545#define __HAL_RCC_SAI4_CLK_ENABLE() do { \
2546 __IO uint32_t tmpreg; \
2547 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
2548 /* Delay after an RCC peripheral clock enabling */ \
2549 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\
2550 UNUSED(tmpreg); \
2551 } while(0)
2552#endif /* SAI4 */
2553
2554#define __HAL_RCC_RTC_CLK_ENABLE() do { \
2555 __IO uint32_t tmpreg; \
2556 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
2557 /* Delay after an RCC peripheral clock enabling */ \
2558 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
2559 UNUSED(tmpreg); \
2560 } while(0)
2561
2562#if defined(DTS)
2563#define __HAL_RCC_DTS_CLK_ENABLE() do { \
2564 __IO uint32_t tmpreg; \
2565 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
2566 /* Delay after an RCC peripheral clock enabling */ \
2567 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
2568 UNUSED(tmpreg); \
2569 } while(0)
2570#endif /*DTS*/
2571
2572#if defined(DFSDM2_BASE)
2573#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
2574 __IO uint32_t tmpreg; \
2575 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
2576 /* Delay after an RCC peripheral clock enabling */ \
2577 tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\
2578 UNUSED(tmpreg); \
2579 } while(0)
2580#endif /*DFSDM2*/
2581
2582#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
2583#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
2584#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
2585#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
2586#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
2587#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
2588#if defined(LPTIM4)
2589#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
2590#endif /*LPTIM4*/
2591#if defined(LPTIM5)
2592#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
2593#endif /*LPTIM5*/
2594#if defined(DAC2)
2595#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)
2596#endif /*DAC2*/
2597#define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
2598#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
2599#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
2600#if defined(SAI4)
2601#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
2602#endif /*SAI4*/
2603#if defined(DTS)
2604#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)
2605#endif /*DTS*/
2606#if defined(DFSDM2_BASE)
2607#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)
2608#endif /*DFSDM2*/
2609
2616#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U)
2617#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)
2618#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U)
2619#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U)
2620#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U)
2621#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U)
2622#if defined(LPTIM4)
2623#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U)
2624#endif /*LPTIM4*/
2625#if defined(LPTIM5)
2626#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U)
2627#endif /*LPTIM5*/
2628#if defined(DAC2)
2629#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) != 0U)
2630#endif /*DAC2*/
2631#define __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U)
2632#define __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U)
2633#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U)
2634#if defined(SAI4)
2635#define __HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U)
2636#endif /*SAI4*/
2637#if defined(DTS)
2638#define __HAL_RCC_DTS_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) != 0U)
2639#endif /*DTS*/
2640#if defined(DFSDM2_BASE)
2641#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) != 0U)
2642#endif /*DFSDM2*/
2643
2644#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U)
2645#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)
2646#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U)
2647#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U)
2648#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U)
2649#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U)
2650#if defined(LPTIM4)
2651#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U)
2652#endif /*LPTIM4*/
2653#if defined(LPTIM5)
2654#define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U)
2655#endif /*LPTIM5*/
2656#if defined(DAC2)
2657#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) == 0U)
2658#endif /*DAC2*/
2659#define __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U)
2660#define __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U)
2661#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U)
2662#if defined(SAI4)
2663#define __HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U)
2664#endif /*SAI4*/
2665#if defined(DTS)
2666#define __HAL_RCC_DTS_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) == 0U)
2667#endif /*DTS*/
2668#if defined(DFSDM2_BASE)
2669#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) == 0U)
2670#endif /*DFSDM2*/
2671
2672#if defined(DUAL_CORE)
2673
2674/* Exported macros for RCC_C1 -------------------------------------------------*/
2675
2682#define __HAL_RCC_C1_MDMA_CLK_ENABLE() do { \
2683 __IO uint32_t tmpreg; \
2684 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
2685 /* Delay after an RCC peripheral clock enabling */ \
2686 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
2687 UNUSED(tmpreg); \
2688 } while(0)
2689
2690#define __HAL_RCC_C1_DMA2D_CLK_ENABLE() do { \
2691 __IO uint32_t tmpreg; \
2692 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
2693 /* Delay after an RCC peripheral clock enabling */ \
2694 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
2695 UNUSED(tmpreg); \
2696 } while(0)
2697
2698#define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE() do { \
2699 __IO uint32_t tmpreg; \
2700 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
2701 /* Delay after an RCC peripheral clock enabling */ \
2702 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
2703 UNUSED(tmpreg); \
2704 } while(0)
2705
2706
2707#define __HAL_RCC_C1_FMC_CLK_ENABLE() do { \
2708 __IO uint32_t tmpreg; \
2709 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
2710 /* Delay after an RCC peripheral clock enabling */ \
2711 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
2712 UNUSED(tmpreg); \
2713 } while(0)
2714
2715#define __HAL_RCC_C1_QSPI_CLK_ENABLE() do { \
2716 __IO uint32_t tmpreg; \
2717 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
2718 /* Delay after an RCC peripheral clock enabling */ \
2719 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
2720 UNUSED(tmpreg); \
2721 } while(0)
2722
2723#define __HAL_RCC_C1_SDMMC1_CLK_ENABLE() do { \
2724 __IO uint32_t tmpreg; \
2725 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
2726 /* Delay after an RCC peripheral clock enabling */ \
2727 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
2728 UNUSED(tmpreg); \
2729 } while(0)
2730
2731
2732
2733
2734#define __HAL_RCC_C1_MDMA_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
2735#define __HAL_RCC_C1_DMA2D_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
2736#define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
2737#define __HAL_RCC_C1_FMC_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
2738#define __HAL_RCC_C1_QSPI_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
2739#define __HAL_RCC_C1_SDMMC1_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
2740
2741
2742
2743
2750#define __HAL_RCC_C1_DMA1_CLK_ENABLE() do { \
2751 __IO uint32_t tmpreg; \
2752 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
2753 /* Delay after an RCC peripheral clock enabling */ \
2754 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
2755 UNUSED(tmpreg); \
2756 } while(0)
2757
2758#define __HAL_RCC_C1_DMA2_CLK_ENABLE() do { \
2759 __IO uint32_t tmpreg; \
2760 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
2761 /* Delay after an RCC peripheral clock enabling */ \
2762 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
2763 UNUSED(tmpreg); \
2764 } while(0)
2765
2766#define __HAL_RCC_C1_ADC12_CLK_ENABLE() do { \
2767 __IO uint32_t tmpreg; \
2768 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
2769 /* Delay after an RCC peripheral clock enabling */ \
2770 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
2771 UNUSED(tmpreg); \
2772 } while(0)
2773
2774#define __HAL_RCC_C1_ART_CLK_ENABLE() do { \
2775 __IO uint32_t tmpreg; \
2776 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
2777 /* Delay after an RCC peripheral clock enabling */ \
2778 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\
2779 UNUSED(tmpreg); \
2780 } while(0)
2781
2782#define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE() do { \
2783 __IO uint32_t tmpreg; \
2784 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
2785 /* Delay after an RCC peripheral clock enabling */ \
2786 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
2787 UNUSED(tmpreg); \
2788 } while(0)
2789
2790#define __HAL_RCC_C1_ETH1TX_CLK_ENABLE() do { \
2791 __IO uint32_t tmpreg; \
2792 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
2793 /* Delay after an RCC peripheral clock enabling */ \
2794 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
2795 UNUSED(tmpreg); \
2796 } while(0)
2797
2798#define __HAL_RCC_C1_ETH1RX_CLK_ENABLE() do { \
2799 __IO uint32_t tmpreg; \
2800 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
2801 /* Delay after an RCC peripheral clock enabling */ \
2802 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
2803 UNUSED(tmpreg); \
2804 } while(0)
2805
2806
2807#define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE() do { \
2808 __IO uint32_t tmpreg; \
2809 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
2810 /* Delay after an RCC peripheral clock enabling */ \
2811 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
2812 UNUSED(tmpreg); \
2813 } while(0)
2814
2815#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \
2816 __IO uint32_t tmpreg; \
2817 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
2818 /* Delay after an RCC peripheral clock enabling */ \
2819 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
2820 UNUSED(tmpreg); \
2821 } while(0)
2822
2823#define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE() do { \
2824 __IO uint32_t tmpreg; \
2825 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
2826 /* Delay after an RCC peripheral clock enabling */ \
2827 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
2828 UNUSED(tmpreg); \
2829 } while(0)
2830
2831#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \
2832 __IO uint32_t tmpreg; \
2833 SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
2834 /* Delay after an RCC peripheral clock enabling */ \
2835 tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
2836 UNUSED(tmpreg); \
2837 } while(0)
2838
2839#define __HAL_RCC_C1_DMA1_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
2840#define __HAL_RCC_C1_DMA2_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
2841#define __HAL_RCC_C1_ADC12_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
2842#define __HAL_RCC_C1_ART_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
2843#define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
2844#define __HAL_RCC_C1_ETH1TX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
2845#define __HAL_RCC_C1_ETH1RX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
2846#define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
2847#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
2848#define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
2849#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
2850
2857#define __HAL_RCC_C1_DCMI_CLK_ENABLE() do { \
2858 __IO uint32_t tmpreg; \
2859 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
2860 /* Delay after an RCC peripheral clock enabling */ \
2861 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
2862 UNUSED(tmpreg); \
2863 } while(0)
2864#if defined(CRYP)
2865#define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \
2866 __IO uint32_t tmpreg; \
2867 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
2868 /* Delay after an RCC peripheral clock enabling */ \
2869 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
2870 UNUSED(tmpreg); \
2871 } while(0)
2872#endif /* CRYP */
2873
2874#if defined(HASH)
2875#define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \
2876 __IO uint32_t tmpreg; \
2877 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
2878 /* Delay after an RCC peripheral clock enabling */ \
2879 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\
2880 UNUSED(tmpreg); \
2881 } while(0)
2882#endif /* HASH */
2883
2884#define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \
2885 __IO uint32_t tmpreg; \
2886 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
2887 /* Delay after an RCC peripheral clock enabling */ \
2888 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\
2889 UNUSED(tmpreg); \
2890 } while(0)
2891
2892#define __HAL_RCC_C1_SDMMC2_CLK_ENABLE() do { \
2893 __IO uint32_t tmpreg; \
2894 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
2895 /* Delay after an RCC peripheral clock enabling */ \
2896 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
2897 UNUSED(tmpreg); \
2898 } while(0)
2899
2900#define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE() do { \
2901 __IO uint32_t tmpreg; \
2902 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
2903 /* Delay after an RCC peripheral clock enabling */ \
2904 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
2905 UNUSED(tmpreg); \
2906 } while(0)
2907
2908#define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE() do { \
2909 __IO uint32_t tmpreg; \
2910 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
2911 /* Delay after an RCC peripheral clock enabling */ \
2912 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
2913 UNUSED(tmpreg); \
2914 } while(0)
2915
2916#define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE() do { \
2917 __IO uint32_t tmpreg; \
2918 SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
2919 /* Delay after an RCC peripheral clock enabling */ \
2920 tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
2921 UNUSED(tmpreg); \
2922 } while(0)
2923
2924#define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
2925#if defined(CRYP)
2926#define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
2927#endif /* CRYP */
2928#if defined(HASH)
2929#define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
2930#endif /* HASH */
2931#define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
2932#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
2933#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
2934#define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
2935#define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
2936
2943#define __HAL_RCC_C1_GPIOA_CLK_ENABLE() do { \
2944 __IO uint32_t tmpreg; \
2945 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
2946 /* Delay after an RCC peripheral clock enabling */ \
2947 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
2948 UNUSED(tmpreg); \
2949 } while(0)
2950
2951#define __HAL_RCC_C1_GPIOB_CLK_ENABLE() do { \
2952 __IO uint32_t tmpreg; \
2953 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
2954 /* Delay after an RCC peripheral clock enabling */ \
2955 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
2956 UNUSED(tmpreg); \
2957 } while(0)
2958
2959#define __HAL_RCC_C1_GPIOC_CLK_ENABLE() do { \
2960 __IO uint32_t tmpreg; \
2961 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
2962 /* Delay after an RCC peripheral clock enabling */ \
2963 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
2964 UNUSED(tmpreg); \
2965 } while(0)
2966
2967#define __HAL_RCC_C1_GPIOD_CLK_ENABLE() do { \
2968 __IO uint32_t tmpreg; \
2969 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
2970 /* Delay after an RCC peripheral clock enabling */ \
2971 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
2972 UNUSED(tmpreg); \
2973 } while(0)
2974
2975#define __HAL_RCC_C1_GPIOE_CLK_ENABLE() do { \
2976 __IO uint32_t tmpreg; \
2977 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
2978 /* Delay after an RCC peripheral clock enabling */ \
2979 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
2980 UNUSED(tmpreg); \
2981 } while(0)
2982
2983#define __HAL_RCC_C1_GPIOF_CLK_ENABLE() do { \
2984 __IO uint32_t tmpreg; \
2985 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
2986 /* Delay after an RCC peripheral clock enabling */ \
2987 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
2988 UNUSED(tmpreg); \
2989 } while(0)
2990
2991#define __HAL_RCC_C1_GPIOG_CLK_ENABLE() do { \
2992 __IO uint32_t tmpreg; \
2993 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
2994 /* Delay after an RCC peripheral clock enabling */ \
2995 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
2996 UNUSED(tmpreg); \
2997 } while(0)
2998
2999#define __HAL_RCC_C1_GPIOH_CLK_ENABLE() do { \
3000 __IO uint32_t tmpreg; \
3001 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
3002 /* Delay after an RCC peripheral clock enabling */ \
3003 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
3004 UNUSED(tmpreg); \
3005 } while(0)
3006
3007#define __HAL_RCC_C1_GPIOI_CLK_ENABLE() do { \
3008 __IO uint32_t tmpreg; \
3009 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
3010 /* Delay after an RCC peripheral clock enabling */ \
3011 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
3012 UNUSED(tmpreg); \
3013 } while(0)
3014
3015#define __HAL_RCC_C1_GPIOJ_CLK_ENABLE() do { \
3016 __IO uint32_t tmpreg; \
3017 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
3018 /* Delay after an RCC peripheral clock enabling */ \
3019 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
3020 UNUSED(tmpreg); \
3021 } while(0)
3022
3023#define __HAL_RCC_C1_GPIOK_CLK_ENABLE() do { \
3024 __IO uint32_t tmpreg; \
3025 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
3026 /* Delay after an RCC peripheral clock enabling */ \
3027 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
3028 UNUSED(tmpreg); \
3029 } while(0)
3030
3031#define __HAL_RCC_C1_CRC_CLK_ENABLE() do { \
3032 __IO uint32_t tmpreg; \
3033 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
3034 /* Delay after an RCC peripheral clock enabling */ \
3035 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\
3036 UNUSED(tmpreg); \
3037 } while(0)
3038
3039#define __HAL_RCC_C1_BDMA_CLK_ENABLE() do { \
3040 __IO uint32_t tmpreg; \
3041 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
3042 /* Delay after an RCC peripheral clock enabling */ \
3043 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
3044 UNUSED(tmpreg); \
3045 } while(0)
3046
3047#define __HAL_RCC_C1_ADC3_CLK_ENABLE() do { \
3048 __IO uint32_t tmpreg; \
3049 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
3050 /* Delay after an RCC peripheral clock enabling */ \
3051 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
3052 UNUSED(tmpreg); \
3053 } while(0)
3054
3055#define __HAL_RCC_C1_HSEM_CLK_ENABLE() do { \
3056 __IO uint32_t tmpreg; \
3057 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
3058 /* Delay after an RCC peripheral clock enabling */ \
3059 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
3060 UNUSED(tmpreg); \
3061 } while(0)
3062
3063#define __HAL_RCC_C1_BKPRAM_CLK_ENABLE() do { \
3064 __IO uint32_t tmpreg; \
3065 SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
3066 /* Delay after an RCC peripheral clock enabling */ \
3067 tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
3068 UNUSED(tmpreg); \
3069 } while(0)
3070
3071
3072#define __HAL_RCC_C1_GPIOA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
3073#define __HAL_RCC_C1_GPIOB_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
3074#define __HAL_RCC_C1_GPIOC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
3075#define __HAL_RCC_C1_GPIOD_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
3076#define __HAL_RCC_C1_GPIOE_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
3077#define __HAL_RCC_C1_GPIOF_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
3078#define __HAL_RCC_C1_GPIOG_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
3079#define __HAL_RCC_C1_GPIOH_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
3080#define __HAL_RCC_C1_GPIOI_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
3081#define __HAL_RCC_C1_GPIOJ_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
3082#define __HAL_RCC_C1_GPIOK_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
3083#define __HAL_RCC_C1_CRC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
3084#define __HAL_RCC_C1_BDMA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
3085#define __HAL_RCC_C1_ADC3_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
3086#define __HAL_RCC_C1_HSEM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
3087#define __HAL_RCC_C1_BKPRAM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
3088
3089
3096#define __HAL_RCC_C1_LTDC_CLK_ENABLE() do { \
3097 __IO uint32_t tmpreg; \
3098 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
3099 /* Delay after an RCC peripheral clock enabling */ \
3100 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\
3101 UNUSED(tmpreg); \
3102 } while(0)
3103
3104#define __HAL_RCC_C1_DSI_CLK_ENABLE() do { \
3105 __IO uint32_t tmpreg; \
3106 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
3107 /* Delay after an RCC peripheral clock enabling */ \
3108 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\
3109 UNUSED(tmpreg); \
3110 } while(0)
3111
3112#define __HAL_RCC_C1_WWDG1_CLK_ENABLE() do { \
3113 __IO uint32_t tmpreg; \
3114 SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
3115 /* Delay after an RCC peripheral clock enabling */ \
3116 tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\
3117 UNUSED(tmpreg); \
3118 } while(0)
3119
3120#define __HAL_RCC_C1_LTDC_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
3121#define __HAL_RCC_C1_DSI_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
3122#define __HAL_RCC_C1_WWDG1_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
3123
3130#define __HAL_RCC_C1_TIM2_CLK_ENABLE() do { \
3131 __IO uint32_t tmpreg; \
3132 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
3133 /* Delay after an RCC peripheral clock enabling */ \
3134 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\
3135 UNUSED(tmpreg); \
3136 } while(0)
3137
3138#define __HAL_RCC_C1_TIM3_CLK_ENABLE() do { \
3139 __IO uint32_t tmpreg; \
3140 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
3141 /* Delay after an RCC peripheral clock enabling */ \
3142 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\
3143 UNUSED(tmpreg); \
3144 } while(0)
3145
3146#define __HAL_RCC_C1_TIM4_CLK_ENABLE() do { \
3147 __IO uint32_t tmpreg; \
3148 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
3149 /* Delay after an RCC peripheral clock enabling */ \
3150 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\
3151 UNUSED(tmpreg); \
3152 } while(0)
3153
3154#define __HAL_RCC_C1_TIM5_CLK_ENABLE() do { \
3155 __IO uint32_t tmpreg; \
3156 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
3157 /* Delay after an RCC peripheral clock enabling */ \
3158 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\
3159 UNUSED(tmpreg); \
3160 } while(0)
3161
3162#define __HAL_RCC_C1_TIM6_CLK_ENABLE() do { \
3163 __IO uint32_t tmpreg; \
3164 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
3165 /* Delay after an RCC peripheral clock enabling */ \
3166 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\
3167 UNUSED(tmpreg); \
3168 } while(0)
3169
3170#define __HAL_RCC_C1_TIM7_CLK_ENABLE() do { \
3171 __IO uint32_t tmpreg; \
3172 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
3173 /* Delay after an RCC peripheral clock enabling */ \
3174 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\
3175 UNUSED(tmpreg); \
3176 } while(0)
3177
3178#define __HAL_RCC_C1_TIM12_CLK_ENABLE() do { \
3179 __IO uint32_t tmpreg; \
3180 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
3181 /* Delay after an RCC peripheral clock enabling */ \
3182 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\
3183 UNUSED(tmpreg); \
3184 } while(0)
3185
3186#define __HAL_RCC_C1_TIM13_CLK_ENABLE() do { \
3187 __IO uint32_t tmpreg; \
3188 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
3189 /* Delay after an RCC peripheral clock enabling */ \
3190 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\
3191 UNUSED(tmpreg); \
3192 } while(0)
3193
3194#define __HAL_RCC_C1_TIM14_CLK_ENABLE() do { \
3195 __IO uint32_t tmpreg; \
3196 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
3197 /* Delay after an RCC peripheral clock enabling */ \
3198 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\
3199 UNUSED(tmpreg); \
3200 } while(0)
3201
3202#define __HAL_RCC_C1_LPTIM1_CLK_ENABLE() do { \
3203 __IO uint32_t tmpreg; \
3204 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
3205 /* Delay after an RCC peripheral clock enabling */ \
3206 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
3207 UNUSED(tmpreg); \
3208 } while(0)
3209
3210#define __HAL_RCC_C1_WWDG2_CLK_ENABLE() do { \
3211 __IO uint32_t tmpreg; \
3212 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
3213 /* Delay after an RCC peripheral clock enabling */ \
3214 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\
3215 UNUSED(tmpreg); \
3216 } while(0)
3217
3218#define __HAL_RCC_C1_SPI2_CLK_ENABLE() do { \
3219 __IO uint32_t tmpreg; \
3220 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
3221 /* Delay after an RCC peripheral clock enabling */ \
3222 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\
3223 UNUSED(tmpreg); \
3224 } while(0)
3225
3226#define __HAL_RCC_C1_SPI3_CLK_ENABLE() do { \
3227 __IO uint32_t tmpreg; \
3228 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
3229 /* Delay after an RCC peripheral clock enabling */ \
3230 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\
3231 UNUSED(tmpreg); \
3232 } while(0)
3233
3234#define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE() do { \
3235 __IO uint32_t tmpreg; \
3236 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
3237 /* Delay after an RCC peripheral clock enabling */ \
3238 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
3239 UNUSED(tmpreg); \
3240 } while(0)
3241
3242#define __HAL_RCC_C1_USART2_CLK_ENABLE() do { \
3243 __IO uint32_t tmpreg; \
3244 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
3245 /* Delay after an RCC peripheral clock enabling */ \
3246 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\
3247 UNUSED(tmpreg); \
3248 } while(0)
3249
3250#define __HAL_RCC_C1_USART3_CLK_ENABLE() do { \
3251 __IO uint32_t tmpreg; \
3252 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
3253 /* Delay after an RCC peripheral clock enabling */ \
3254 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\
3255 UNUSED(tmpreg); \
3256 } while(0)
3257
3258#define __HAL_RCC_C1_UART4_CLK_ENABLE() do { \
3259 __IO uint32_t tmpreg; \
3260 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
3261 /* Delay after an RCC peripheral clock enabling */ \
3262 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\
3263 UNUSED(tmpreg); \
3264 } while(0)
3265
3266#define __HAL_RCC_C1_UART5_CLK_ENABLE() do { \
3267 __IO uint32_t tmpreg; \
3268 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
3269 /* Delay after an RCC peripheral clock enabling */ \
3270 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\
3271 UNUSED(tmpreg); \
3272 } while(0)
3273
3274#define __HAL_RCC_C1_I2C1_CLK_ENABLE() do { \
3275 __IO uint32_t tmpreg; \
3276 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
3277 /* Delay after an RCC peripheral clock enabling */ \
3278 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\
3279 UNUSED(tmpreg); \
3280 } while(0)
3281
3282#define __HAL_RCC_C1_I2C2_CLK_ENABLE() do { \
3283 __IO uint32_t tmpreg; \
3284 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
3285 /* Delay after an RCC peripheral clock enabling */ \
3286 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\
3287 UNUSED(tmpreg); \
3288 } while(0)
3289
3290#define __HAL_RCC_C1_I2C3_CLK_ENABLE() do { \
3291 __IO uint32_t tmpreg; \
3292 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
3293 /* Delay after an RCC peripheral clock enabling */ \
3294 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\
3295 UNUSED(tmpreg); \
3296 } while(0)
3297
3298#define __HAL_RCC_C1_CEC_CLK_ENABLE() do { \
3299 __IO uint32_t tmpreg; \
3300 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
3301 /* Delay after an RCC peripheral clock enabling */ \
3302 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\
3303 UNUSED(tmpreg); \
3304 } while(0)
3305
3306#define __HAL_RCC_C1_DAC12_CLK_ENABLE() do { \
3307 __IO uint32_t tmpreg; \
3308 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
3309 /* Delay after an RCC peripheral clock enabling */ \
3310 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\
3311 UNUSED(tmpreg); \
3312 } while(0)
3313
3314#define __HAL_RCC_C1_UART7_CLK_ENABLE() do { \
3315 __IO uint32_t tmpreg; \
3316 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
3317 /* Delay after an RCC peripheral clock enabling */ \
3318 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\
3319 UNUSED(tmpreg); \
3320 } while(0)
3321
3322#define __HAL_RCC_C1_UART8_CLK_ENABLE() do { \
3323 __IO uint32_t tmpreg; \
3324 SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
3325 /* Delay after an RCC peripheral clock enabling */ \
3326 tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\
3327 UNUSED(tmpreg); \
3328 } while(0)
3329
3330#define __HAL_RCC_C1_CRS_CLK_ENABLE() do { \
3331 __IO uint32_t tmpreg; \
3332 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
3333 /* Delay after an RCC peripheral clock enabling */ \
3334 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\
3335 UNUSED(tmpreg); \
3336 } while(0)
3337
3338#define __HAL_RCC_C1_SWPMI_CLK_ENABLE() do { \
3339 __IO uint32_t tmpreg; \
3340 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
3341 /* Delay after an RCC peripheral clock enabling */ \
3342 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\
3343 UNUSED(tmpreg); \
3344 } while(0)
3345
3346#define __HAL_RCC_C1_OPAMP_CLK_ENABLE() do { \
3347 __IO uint32_t tmpreg; \
3348 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
3349 /* Delay after an RCC peripheral clock enabling */ \
3350 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\
3351 UNUSED(tmpreg); \
3352 } while(0)
3353
3354#define __HAL_RCC_C1_MDIOS_CLK_ENABLE() do { \
3355 __IO uint32_t tmpreg; \
3356 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
3357 /* Delay after an RCC peripheral clock enabling */ \
3358 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\
3359 UNUSED(tmpreg); \
3360 } while(0)
3361
3362#define __HAL_RCC_C1_FDCAN_CLK_ENABLE() do { \
3363 __IO uint32_t tmpreg; \
3364 SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
3365 /* Delay after an RCC peripheral clock enabling */ \
3366 tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\
3367 UNUSED(tmpreg); \
3368 } while(0)
3369
3370
3371#define __HAL_RCC_C1_TIM2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
3372#define __HAL_RCC_C1_TIM3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
3373#define __HAL_RCC_C1_TIM4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
3374#define __HAL_RCC_C1_TIM5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
3375#define __HAL_RCC_C1_TIM6_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
3376#define __HAL_RCC_C1_TIM7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
3377#define __HAL_RCC_C1_TIM12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
3378#define __HAL_RCC_C1_TIM13_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
3379#define __HAL_RCC_C1_TIM14_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
3380#define __HAL_RCC_C1_LPTIM1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
3381#define __HAL_RCC_C1_WWDG2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
3382#define __HAL_RCC_C1_SPI2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
3383#define __HAL_RCC_C1_SPI3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
3384#define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
3385#define __HAL_RCC_C1_USART2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
3386#define __HAL_RCC_C1_USART3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
3387#define __HAL_RCC_C1_UART4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
3388#define __HAL_RCC_C1_UART5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
3389#define __HAL_RCC_C1_I2C1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
3390#define __HAL_RCC_C1_I2C2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
3391#define __HAL_RCC_C1_I2C3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
3392#define __HAL_RCC_C1_CEC_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
3393#define __HAL_RCC_C1_DAC12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
3394#define __HAL_RCC_C1_UART7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
3395#define __HAL_RCC_C1_UART8_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
3396#define __HAL_RCC_C1_CRS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
3397#define __HAL_RCC_C1_SWPMI_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
3398#define __HAL_RCC_C1_OPAMP_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
3399#define __HAL_RCC_C1_MDIOS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
3400#define __HAL_RCC_C1_FDCAN_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
3401
3408#define __HAL_RCC_C1_TIM1_CLK_ENABLE() do { \
3409 __IO uint32_t tmpreg; \
3410 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
3411 /* Delay after an RCC peripheral clock enabling */ \
3412 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\
3413 UNUSED(tmpreg); \
3414 } while(0)
3415
3416#define __HAL_RCC_C1_TIM8_CLK_ENABLE() do { \
3417 __IO uint32_t tmpreg; \
3418 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
3419 /* Delay after an RCC peripheral clock enabling */ \
3420 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\
3421 UNUSED(tmpreg); \
3422 } while(0)
3423
3424#define __HAL_RCC_C1_USART1_CLK_ENABLE() do { \
3425 __IO uint32_t tmpreg; \
3426 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
3427 /* Delay after an RCC peripheral clock enabling */ \
3428 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\
3429 UNUSED(tmpreg); \
3430 } while(0)
3431
3432#define __HAL_RCC_C1_USART6_CLK_ENABLE() do { \
3433 __IO uint32_t tmpreg; \
3434 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
3435 /* Delay after an RCC peripheral clock enabling */ \
3436 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\
3437 UNUSED(tmpreg); \
3438 } while(0)
3439
3440#define __HAL_RCC_C1_SPI1_CLK_ENABLE() do { \
3441 __IO uint32_t tmpreg; \
3442 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
3443 /* Delay after an RCC peripheral clock enabling */ \
3444 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\
3445 UNUSED(tmpreg); \
3446 } while(0)
3447
3448#define __HAL_RCC_C1_SPI4_CLK_ENABLE() do { \
3449 __IO uint32_t tmpreg; \
3450 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
3451 /* Delay after an RCC peripheral clock enabling */ \
3452 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\
3453 UNUSED(tmpreg); \
3454 } while(0)
3455
3456#define __HAL_RCC_C1_TIM15_CLK_ENABLE() do { \
3457 __IO uint32_t tmpreg; \
3458 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
3459 /* Delay after an RCC peripheral clock enabling */ \
3460 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\
3461 UNUSED(tmpreg); \
3462 } while(0)
3463
3464#define __HAL_RCC_C1_TIM16_CLK_ENABLE() do { \
3465 __IO uint32_t tmpreg; \
3466 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
3467 /* Delay after an RCC peripheral clock enabling */ \
3468 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\
3469 UNUSED(tmpreg); \
3470 } while(0)
3471
3472#define __HAL_RCC_C1_TIM17_CLK_ENABLE() do { \
3473 __IO uint32_t tmpreg; \
3474 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
3475 /* Delay after an RCC peripheral clock enabling */ \
3476 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\
3477 UNUSED(tmpreg); \
3478 } while(0)
3479
3480#define __HAL_RCC_C1_SPI5_CLK_ENABLE() do { \
3481 __IO uint32_t tmpreg; \
3482 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
3483 /* Delay after an RCC peripheral clock enabling */ \
3484 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
3485 UNUSED(tmpreg); \
3486 } while(0)
3487
3488#define __HAL_RCC_C1_SAI1_CLK_ENABLE() do { \
3489 __IO uint32_t tmpreg; \
3490 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
3491 /* Delay after an RCC peripheral clock enabling */ \
3492 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\
3493 UNUSED(tmpreg); \
3494 } while(0)
3495
3496#define __HAL_RCC_C1_SAI2_CLK_ENABLE() do { \
3497 __IO uint32_t tmpreg; \
3498 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
3499 /* Delay after an RCC peripheral clock enabling */ \
3500 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\
3501 UNUSED(tmpreg); \
3502 } while(0)
3503
3504#define __HAL_RCC_C1_SAI3_CLK_ENABLE() do { \
3505 __IO uint32_t tmpreg; \
3506 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
3507 /* Delay after an RCC peripheral clock enabling */ \
3508 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\
3509 UNUSED(tmpreg); \
3510 } while(0)
3511
3512#define __HAL_RCC_C1_DFSDM1_CLK_ENABLE() do { \
3513 __IO uint32_t tmpreg; \
3514 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
3515 /* Delay after an RCC peripheral clock enabling */ \
3516 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
3517 UNUSED(tmpreg); \
3518 } while(0)
3519
3520#define __HAL_RCC_C1_HRTIM1_CLK_ENABLE() do { \
3521 __IO uint32_t tmpreg; \
3522 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
3523 /* Delay after an RCC peripheral clock enabling */ \
3524 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\
3525 UNUSED(tmpreg); \
3526 } while(0)
3527
3528#define __HAL_RCC_C1_TIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
3529#define __HAL_RCC_C1_TIM8_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
3530#define __HAL_RCC_C1_USART1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
3531#define __HAL_RCC_C1_USART6_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
3532#define __HAL_RCC_C1_SPI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
3533#define __HAL_RCC_C1_SPI4_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
3534#define __HAL_RCC_C1_TIM15_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
3535#define __HAL_RCC_C1_TIM16_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
3536#define __HAL_RCC_C1_TIM17_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
3537#define __HAL_RCC_C1_SPI5_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
3538#define __HAL_RCC_C1_SAI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
3539#define __HAL_RCC_C1_SAI2_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
3540#define __HAL_RCC_C1_SAI3_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
3541#define __HAL_RCC_C1_DFSDM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
3542#define __HAL_RCC_C1_HRTIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
3543
3550#define __HAL_RCC_C1_SYSCFG_CLK_ENABLE() do { \
3551 __IO uint32_t tmpreg; \
3552 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
3553 /* Delay after an RCC peripheral clock enabling */ \
3554 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
3555 UNUSED(tmpreg); \
3556 } while(0)
3557
3558#define __HAL_RCC_C1_LPUART1_CLK_ENABLE() do { \
3559 __IO uint32_t tmpreg; \
3560 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
3561 /* Delay after an RCC peripheral clock enabling */ \
3562 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\
3563 UNUSED(tmpreg); \
3564 } while(0)
3565
3566#define __HAL_RCC_C1_SPI6_CLK_ENABLE() do { \
3567 __IO uint32_t tmpreg; \
3568 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
3569 /* Delay after an RCC peripheral clock enabling */ \
3570 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\
3571 UNUSED(tmpreg); \
3572 } while(0)
3573
3574#define __HAL_RCC_C1_I2C4_CLK_ENABLE() do { \
3575 __IO uint32_t tmpreg; \
3576 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
3577 /* Delay after an RCC peripheral clock enabling */ \
3578 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\
3579 UNUSED(tmpreg); \
3580 } while(0)
3581
3582#define __HAL_RCC_C1_LPTIM2_CLK_ENABLE() do { \
3583 __IO uint32_t tmpreg; \
3584 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
3585 /* Delay after an RCC peripheral clock enabling */ \
3586 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
3587 UNUSED(tmpreg); \
3588 } while(0)
3589
3590#define __HAL_RCC_C1_LPTIM3_CLK_ENABLE() do { \
3591 __IO uint32_t tmpreg; \
3592 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
3593 /* Delay after an RCC peripheral clock enabling */ \
3594 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
3595 UNUSED(tmpreg); \
3596 } while(0)
3597
3598#define __HAL_RCC_C1_LPTIM4_CLK_ENABLE() do { \
3599 __IO uint32_t tmpreg; \
3600 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
3601 /* Delay after an RCC peripheral clock enabling */ \
3602 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
3603 UNUSED(tmpreg); \
3604 } while(0)
3605
3606#define __HAL_RCC_C1_LPTIM5_CLK_ENABLE() do { \
3607 __IO uint32_t tmpreg; \
3608 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
3609 /* Delay after an RCC peripheral clock enabling */ \
3610 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
3611 UNUSED(tmpreg); \
3612 } while(0)
3613
3614#define __HAL_RCC_C1_COMP12_CLK_ENABLE() do { \
3615 __IO uint32_t tmpreg; \
3616 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
3617 /* Delay after an RCC peripheral clock enabling */ \
3618 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\
3619 UNUSED(tmpreg); \
3620 } while(0)
3621
3622
3623#define __HAL_RCC_C1_VREF_CLK_ENABLE() do { \
3624 __IO uint32_t tmpreg; \
3625 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
3626 /* Delay after an RCC peripheral clock enabling */ \
3627 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\
3628 UNUSED(tmpreg); \
3629 } while(0)
3630
3631#define __HAL_RCC_C1_RTC_CLK_ENABLE() do { \
3632 __IO uint32_t tmpreg; \
3633 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
3634 /* Delay after an RCC peripheral clock enabling */ \
3635 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
3636 UNUSED(tmpreg); \
3637 } while(0)
3638
3639#define __HAL_RCC_C1_SAI4_CLK_ENABLE() do { \
3640 __IO uint32_t tmpreg; \
3641 SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
3642 /* Delay after an RCC peripheral clock enabling */ \
3643 tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\
3644 UNUSED(tmpreg); \
3645 } while(0)
3646
3647
3648#define __HAL_RCC_C1_SYSCFG_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
3649#define __HAL_RCC_C1_LPUART1_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
3650#define __HAL_RCC_C1_SPI6_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
3651#define __HAL_RCC_C1_I2C4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
3652#define __HAL_RCC_C1_LPTIM2_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
3653#define __HAL_RCC_C1_LPTIM3_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
3654#define __HAL_RCC_C1_LPTIM4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
3655#define __HAL_RCC_C1_LPTIM5_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
3656#define __HAL_RCC_C1_COMP12_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
3657#define __HAL_RCC_C1_VREF_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
3658#define __HAL_RCC_C1_RTC_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
3659#define __HAL_RCC_C1_SAI4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
3660
3661/* Exported macros for RCC_C2 -------------------------------------------------*/
3662
3670#define __HAL_RCC_C2_MDMA_CLK_ENABLE() do { \
3671 __IO uint32_t tmpreg; \
3672 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
3673 /* Delay after an RCC peripheral clock enabling */ \
3674 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
3675 UNUSED(tmpreg); \
3676 } while(0)
3677
3678#define __HAL_RCC_C2_DMA2D_CLK_ENABLE() do { \
3679 __IO uint32_t tmpreg; \
3680 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
3681 /* Delay after an RCC peripheral clock enabling */ \
3682 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
3683 UNUSED(tmpreg); \
3684 } while(0)
3685
3686#define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE() do { \
3687 __IO uint32_t tmpreg; \
3688 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
3689 /* Delay after an RCC peripheral clock enabling */ \
3690 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\
3691 UNUSED(tmpreg); \
3692 } while(0)
3693
3694#define __HAL_RCC_FLASH_C2_ALLOCATE() do { \
3695 __IO uint32_t tmpreg; \
3696 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
3697 /* Delay after an RCC peripheral clock enabling */ \
3698 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\
3699 UNUSED(tmpreg); \
3700 } while(0)
3701
3702#define __HAL_RCC_DTCM1_C2_ALLOCATE() do { \
3703 __IO uint32_t tmpreg; \
3704 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
3705 /* Delay after an RCC peripheral clock enabling */ \
3706 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\
3707 UNUSED(tmpreg); \
3708 } while(0)
3709
3710#define __HAL_RCC_DTCM2_C2_ALLOCATE() do { \
3711 __IO uint32_t tmpreg; \
3712 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
3713 /* Delay after an RCC peripheral clock enabling */ \
3714 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\
3715 UNUSED(tmpreg); \
3716 } while(0)
3717
3718#define __HAL_RCC_ITCM_C2_ALLOCATE() do { \
3719 __IO uint32_t tmpreg; \
3720 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
3721 /* Delay after an RCC peripheral clock enabling */ \
3722 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\
3723 UNUSED(tmpreg); \
3724 } while(0)
3725
3726#define __HAL_RCC_D1SRAM1_C2_ALLOCATE() do { \
3727 __IO uint32_t tmpreg; \
3728 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
3729 /* Delay after an RCC peripheral clock enabling */ \
3730 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\
3731 UNUSED(tmpreg); \
3732 } while(0)
3733
3734#define __HAL_RCC_C2_FMC_CLK_ENABLE() do { \
3735 __IO uint32_t tmpreg; \
3736 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
3737 /* Delay after an RCC peripheral clock enabling */ \
3738 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
3739 UNUSED(tmpreg); \
3740 } while(0)
3741
3742#define __HAL_RCC_C2_QSPI_CLK_ENABLE() do { \
3743 __IO uint32_t tmpreg; \
3744 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
3745 /* Delay after an RCC peripheral clock enabling */ \
3746 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
3747 UNUSED(tmpreg); \
3748 } while(0)
3749
3750#define __HAL_RCC_C2_SDMMC1_CLK_ENABLE() do { \
3751 __IO uint32_t tmpreg; \
3752 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
3753 /* Delay after an RCC peripheral clock enabling */ \
3754 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
3755 UNUSED(tmpreg); \
3756 } while(0)
3757
3758
3759
3760
3761#define __HAL_RCC_C2_MDMA_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))
3762#define __HAL_RCC_C2_DMA2D_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))
3763#define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))
3764#define __HAL_RCC_C2_FMC_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
3765#define __HAL_RCC_C2_QSPI_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))
3766#define __HAL_RCC_C2_SDMMC1_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))
3767#define __HAL_RCC_FLASH_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))
3768#define __HAL_RCC_DTCM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN))
3769#define __HAL_RCC_DTCM2_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN))
3770#define __HAL_RCC_ITCM_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN))
3771#define __HAL_RCC_D1SRAM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN))
3772
3779#define __HAL_RCC_C2_DMA1_CLK_ENABLE() do { \
3780 __IO uint32_t tmpreg; \
3781 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
3782 /* Delay after an RCC peripheral clock enabling */ \
3783 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
3784 UNUSED(tmpreg); \
3785 } while(0)
3786
3787#define __HAL_RCC_C2_DMA2_CLK_ENABLE() do { \
3788 __IO uint32_t tmpreg; \
3789 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
3790 /* Delay after an RCC peripheral clock enabling */ \
3791 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
3792 UNUSED(tmpreg); \
3793 } while(0)
3794
3795#define __HAL_RCC_C2_ADC12_CLK_ENABLE() do { \
3796 __IO uint32_t tmpreg; \
3797 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
3798 /* Delay after an RCC peripheral clock enabling */ \
3799 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
3800 UNUSED(tmpreg); \
3801 } while(0)
3802
3803#define __HAL_RCC_C2_ART_CLK_ENABLE() do { \
3804 __IO uint32_t tmpreg; \
3805 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
3806 /* Delay after an RCC peripheral clock enabling */ \
3807 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\
3808 UNUSED(tmpreg); \
3809 } while(0)
3810
3811#define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE() do { \
3812 __IO uint32_t tmpreg; \
3813 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
3814 /* Delay after an RCC peripheral clock enabling */ \
3815 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\
3816 UNUSED(tmpreg); \
3817 } while(0)
3818
3819#define __HAL_RCC_C2_ETH1TX_CLK_ENABLE() do { \
3820 __IO uint32_t tmpreg; \
3821 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
3822 /* Delay after an RCC peripheral clock enabling */ \
3823 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\
3824 UNUSED(tmpreg); \
3825 } while(0)
3826
3827#define __HAL_RCC_C2_ETH1RX_CLK_ENABLE() do { \
3828 __IO uint32_t tmpreg; \
3829 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
3830 /* Delay after an RCC peripheral clock enabling */ \
3831 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\
3832 UNUSED(tmpreg); \
3833 } while(0)
3834
3835#define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE() do { \
3836 __IO uint32_t tmpreg; \
3837 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
3838 /* Delay after an RCC peripheral clock enabling */ \
3839 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
3840 UNUSED(tmpreg); \
3841 } while(0)
3842
3843#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \
3844 __IO uint32_t tmpreg; \
3845 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
3846 /* Delay after an RCC peripheral clock enabling */ \
3847 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
3848 UNUSED(tmpreg); \
3849 } while(0)
3850
3851#define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE() do { \
3852 __IO uint32_t tmpreg; \
3853 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
3854 /* Delay after an RCC peripheral clock enabling */ \
3855 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\
3856 UNUSED(tmpreg); \
3857 } while(0)
3858
3859#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \
3860 __IO uint32_t tmpreg; \
3861 SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
3862 /* Delay after an RCC peripheral clock enabling */ \
3863 tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\
3864 UNUSED(tmpreg); \
3865 } while(0)
3866
3867
3868#define __HAL_RCC_C2_DMA1_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))
3869#define __HAL_RCC_C2_DMA2_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))
3870#define __HAL_RCC_C2_ADC12_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))
3871#define __HAL_RCC_C2_ART_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))
3872#define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))
3873#define __HAL_RCC_C2_ETH1TX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))
3874#define __HAL_RCC_C2_ETH1RX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))
3875#define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))
3876#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))
3877#define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))
3878#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))
3879
3886#define __HAL_RCC_C2_DCMI_CLK_ENABLE() do { \
3887 __IO uint32_t tmpreg; \
3888 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
3889 /* Delay after an RCC peripheral clock enabling */ \
3890 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
3891 UNUSED(tmpreg); \
3892 } while(0)
3893
3894#if defined(CRYP)
3895#define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \
3896 __IO uint32_t tmpreg; \
3897 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
3898 /* Delay after an RCC peripheral clock enabling */ \
3899 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
3900 UNUSED(tmpreg); \
3901 } while(0)
3902#endif /* CRYP */
3903
3904#if defined(HASH)
3905#define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \
3906 __IO uint32_t tmpreg; \
3907 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
3908 /* Delay after an RCC peripheral clock enabling */ \
3909 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\
3910 UNUSED(tmpreg); \
3911 } while(0)
3912#endif /* HASH */
3913
3914#define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \
3915 __IO uint32_t tmpreg; \
3916 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
3917 /* Delay after an RCC peripheral clock enabling */ \
3918 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\
3919 UNUSED(tmpreg); \
3920 } while(0)
3921
3922#define __HAL_RCC_C2_SDMMC2_CLK_ENABLE() do { \
3923 __IO uint32_t tmpreg; \
3924 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
3925 /* Delay after an RCC peripheral clock enabling */ \
3926 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
3927 UNUSED(tmpreg); \
3928 } while(0)
3929
3930#define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE() do { \
3931 __IO uint32_t tmpreg; \
3932 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
3933 /* Delay after an RCC peripheral clock enabling */ \
3934 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\
3935 UNUSED(tmpreg); \
3936 } while(0)
3937
3938#define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE() do { \
3939 __IO uint32_t tmpreg; \
3940 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
3941 /* Delay after an RCC peripheral clock enabling */ \
3942 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\
3943 UNUSED(tmpreg); \
3944 } while(0)
3945
3946#define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE() do { \
3947 __IO uint32_t tmpreg; \
3948 SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
3949 /* Delay after an RCC peripheral clock enabling */ \
3950 tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\
3951 UNUSED(tmpreg); \
3952 } while(0)
3953
3954#define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))
3955#if defined(CRYP)
3956#define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))
3957#endif /* CRYP */
3958#if defined(HASH)
3959#define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))
3960#endif /* HASH */
3961#define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))
3962#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))
3963#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))
3964#define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))
3965#define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))
3966
3973#define __HAL_RCC_C2_GPIOA_CLK_ENABLE() do { \
3974 __IO uint32_t tmpreg; \
3975 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
3976 /* Delay after an RCC peripheral clock enabling */ \
3977 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
3978 UNUSED(tmpreg); \
3979 } while(0)
3980
3981#define __HAL_RCC_C2_GPIOB_CLK_ENABLE() do { \
3982 __IO uint32_t tmpreg; \
3983 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
3984 /* Delay after an RCC peripheral clock enabling */ \
3985 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
3986 UNUSED(tmpreg); \
3987 } while(0)
3988
3989#define __HAL_RCC_C2_GPIOC_CLK_ENABLE() do { \
3990 __IO uint32_t tmpreg; \
3991 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
3992 /* Delay after an RCC peripheral clock enabling */ \
3993 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
3994 UNUSED(tmpreg); \
3995 } while(0)
3996
3997#define __HAL_RCC_C2_GPIOD_CLK_ENABLE() do { \
3998 __IO uint32_t tmpreg; \
3999 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
4000 /* Delay after an RCC peripheral clock enabling */ \
4001 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
4002 UNUSED(tmpreg); \
4003 } while(0)
4004
4005#define __HAL_RCC_C2_GPIOE_CLK_ENABLE() do { \
4006 __IO uint32_t tmpreg; \
4007 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
4008 /* Delay after an RCC peripheral clock enabling */ \
4009 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
4010 UNUSED(tmpreg); \
4011 } while(0)
4012
4013#define __HAL_RCC_C2_GPIOF_CLK_ENABLE() do { \
4014 __IO uint32_t tmpreg; \
4015 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
4016 /* Delay after an RCC peripheral clock enabling */ \
4017 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
4018 UNUSED(tmpreg); \
4019 } while(0)
4020
4021#define __HAL_RCC_C2_GPIOG_CLK_ENABLE() do { \
4022 __IO uint32_t tmpreg; \
4023 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
4024 /* Delay after an RCC peripheral clock enabling */ \
4025 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
4026 UNUSED(tmpreg); \
4027 } while(0)
4028
4029#define __HAL_RCC_C2_GPIOH_CLK_ENABLE() do { \
4030 __IO uint32_t tmpreg; \
4031 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
4032 /* Delay after an RCC peripheral clock enabling */ \
4033 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
4034 UNUSED(tmpreg); \
4035 } while(0)
4036
4037#define __HAL_RCC_C2_GPIOI_CLK_ENABLE() do { \
4038 __IO uint32_t tmpreg; \
4039 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
4040 /* Delay after an RCC peripheral clock enabling */ \
4041 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\
4042 UNUSED(tmpreg); \
4043 } while(0)
4044
4045#define __HAL_RCC_C2_GPIOJ_CLK_ENABLE() do { \
4046 __IO uint32_t tmpreg; \
4047 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
4048 /* Delay after an RCC peripheral clock enabling */ \
4049 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
4050 UNUSED(tmpreg); \
4051 } while(0)
4052
4053#define __HAL_RCC_C2_GPIOK_CLK_ENABLE() do { \
4054 __IO uint32_t tmpreg; \
4055 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
4056 /* Delay after an RCC peripheral clock enabling */ \
4057 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
4058 UNUSED(tmpreg); \
4059 } while(0)
4060
4061#define __HAL_RCC_C2_CRC_CLK_ENABLE() do { \
4062 __IO uint32_t tmpreg; \
4063 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
4064 /* Delay after an RCC peripheral clock enabling */ \
4065 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\
4066 UNUSED(tmpreg); \
4067 } while(0)
4068
4069#define __HAL_RCC_C2_BDMA_CLK_ENABLE() do { \
4070 __IO uint32_t tmpreg; \
4071 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
4072 /* Delay after an RCC peripheral clock enabling */ \
4073 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
4074 UNUSED(tmpreg); \
4075 } while(0)
4076
4077#define __HAL_RCC_C2_ADC3_CLK_ENABLE() do { \
4078 __IO uint32_t tmpreg; \
4079 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
4080 /* Delay after an RCC peripheral clock enabling */ \
4081 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\
4082 UNUSED(tmpreg); \
4083 } while(0)
4084
4085#define __HAL_RCC_C2_HSEM_CLK_ENABLE() do { \
4086 __IO uint32_t tmpreg; \
4087 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
4088 /* Delay after an RCC peripheral clock enabling */ \
4089 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\
4090 UNUSED(tmpreg); \
4091 } while(0)
4092
4093#define __HAL_RCC_C2_BKPRAM_CLK_ENABLE() do { \
4094 __IO uint32_t tmpreg; \
4095 SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
4096 /* Delay after an RCC peripheral clock enabling */ \
4097 tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
4098 UNUSED(tmpreg); \
4099 } while(0)
4100
4101
4102#define __HAL_RCC_C2_GPIOA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)
4103#define __HAL_RCC_C2_GPIOB_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)
4104#define __HAL_RCC_C2_GPIOC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)
4105#define __HAL_RCC_C2_GPIOD_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)
4106#define __HAL_RCC_C2_GPIOE_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)
4107#define __HAL_RCC_C2_GPIOF_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)
4108#define __HAL_RCC_C2_GPIOG_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)
4109#define __HAL_RCC_C2_GPIOH_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)
4110#define __HAL_RCC_C2_GPIOI_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)
4111#define __HAL_RCC_C2_GPIOJ_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)
4112#define __HAL_RCC_C2_GPIOK_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)
4113#define __HAL_RCC_C2_CRC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)
4114#define __HAL_RCC_C2_BDMA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)
4115#define __HAL_RCC_C2_ADC3_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)
4116#define __HAL_RCC_C2_HSEM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)
4117#define __HAL_RCC_C2_BKPRAM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)
4118
4119
4126#define __HAL_RCC_C2_LTDC_CLK_ENABLE() do { \
4127 __IO uint32_t tmpreg; \
4128 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
4129 /* Delay after an RCC peripheral clock enabling */ \
4130 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\
4131 UNUSED(tmpreg); \
4132 } while(0)
4133
4134#define __HAL_RCC_C2_DSI_CLK_ENABLE() do { \
4135 __IO uint32_t tmpreg; \
4136 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
4137 /* Delay after an RCC peripheral clock enabling */ \
4138 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\
4139 UNUSED(tmpreg); \
4140 } while(0)
4141
4142#define __HAL_RCC_C2_WWDG1_CLK_ENABLE() do { \
4143 __IO uint32_t tmpreg; \
4144 SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
4145 /* Delay after an RCC peripheral clock enabling */ \
4146 tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\
4147 UNUSED(tmpreg); \
4148 } while(0)
4149
4150#define __HAL_RCC_C2_LTDC_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)
4151#define __HAL_RCC_C2_DSI_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)
4152#define __HAL_RCC_C2_WWDG1_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)
4153
4160#define __HAL_RCC_C2_TIM2_CLK_ENABLE() do { \
4161 __IO uint32_t tmpreg; \
4162 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
4163 /* Delay after an RCC peripheral clock enabling */ \
4164 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\
4165 UNUSED(tmpreg); \
4166 } while(0)
4167
4168#define __HAL_RCC_C2_TIM3_CLK_ENABLE() do { \
4169 __IO uint32_t tmpreg; \
4170 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
4171 /* Delay after an RCC peripheral clock enabling */ \
4172 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\
4173 UNUSED(tmpreg); \
4174 } while(0)
4175
4176#define __HAL_RCC_C2_TIM4_CLK_ENABLE() do { \
4177 __IO uint32_t tmpreg; \
4178 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
4179 /* Delay after an RCC peripheral clock enabling */ \
4180 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\
4181 UNUSED(tmpreg); \
4182 } while(0)
4183
4184#define __HAL_RCC_C2_TIM5_CLK_ENABLE() do { \
4185 __IO uint32_t tmpreg; \
4186 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
4187 /* Delay after an RCC peripheral clock enabling */ \
4188 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\
4189 UNUSED(tmpreg); \
4190 } while(0)
4191
4192#define __HAL_RCC_C2_TIM6_CLK_ENABLE() do { \
4193 __IO uint32_t tmpreg; \
4194 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
4195 /* Delay after an RCC peripheral clock enabling */ \
4196 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\
4197 UNUSED(tmpreg); \
4198 } while(0)
4199
4200#define __HAL_RCC_C2_TIM7_CLK_ENABLE() do { \
4201 __IO uint32_t tmpreg; \
4202 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
4203 /* Delay after an RCC peripheral clock enabling */ \
4204 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\
4205 UNUSED(tmpreg); \
4206 } while(0)
4207
4208#define __HAL_RCC_C2_TIM12_CLK_ENABLE() do { \
4209 __IO uint32_t tmpreg; \
4210 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
4211 /* Delay after an RCC peripheral clock enabling */ \
4212 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\
4213 UNUSED(tmpreg); \
4214 } while(0)
4215
4216#define __HAL_RCC_C2_TIM13_CLK_ENABLE() do { \
4217 __IO uint32_t tmpreg; \
4218 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
4219 /* Delay after an RCC peripheral clock enabling */ \
4220 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\
4221 UNUSED(tmpreg); \
4222 } while(0)
4223
4224#define __HAL_RCC_C2_TIM14_CLK_ENABLE() do { \
4225 __IO uint32_t tmpreg; \
4226 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
4227 /* Delay after an RCC peripheral clock enabling */ \
4228 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\
4229 UNUSED(tmpreg); \
4230 } while(0)
4231
4232#define __HAL_RCC_C2_LPTIM1_CLK_ENABLE() do { \
4233 __IO uint32_t tmpreg; \
4234 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
4235 /* Delay after an RCC peripheral clock enabling */ \
4236 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
4237 UNUSED(tmpreg); \
4238 } while(0)
4239
4240#define __HAL_RCC_C2_WWDG2_CLK_ENABLE() do { \
4241 __IO uint32_t tmpreg; \
4242 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
4243 /* Delay after an RCC peripheral clock enabling */ \
4244 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\
4245 UNUSED(tmpreg); \
4246 } while(0)
4247
4248#define __HAL_RCC_C2_SPI2_CLK_ENABLE() do { \
4249 __IO uint32_t tmpreg; \
4250 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
4251 /* Delay after an RCC peripheral clock enabling */ \
4252 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\
4253 UNUSED(tmpreg); \
4254 } while(0)
4255
4256#define __HAL_RCC_C2_SPI3_CLK_ENABLE() do { \
4257 __IO uint32_t tmpreg; \
4258 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
4259 /* Delay after an RCC peripheral clock enabling */ \
4260 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\
4261 UNUSED(tmpreg); \
4262 } while(0)
4263
4264#define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE() do { \
4265 __IO uint32_t tmpreg; \
4266 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
4267 /* Delay after an RCC peripheral clock enabling */ \
4268 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
4269 UNUSED(tmpreg); \
4270 } while(0)
4271
4272#define __HAL_RCC_C2_USART2_CLK_ENABLE() do { \
4273 __IO uint32_t tmpreg; \
4274 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
4275 /* Delay after an RCC peripheral clock enabling */ \
4276 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\
4277 UNUSED(tmpreg); \
4278 } while(0)
4279
4280#define __HAL_RCC_C2_USART3_CLK_ENABLE() do { \
4281 __IO uint32_t tmpreg; \
4282 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
4283 /* Delay after an RCC peripheral clock enabling */ \
4284 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\
4285 UNUSED(tmpreg); \
4286 } while(0)
4287
4288#define __HAL_RCC_C2_UART4_CLK_ENABLE() do { \
4289 __IO uint32_t tmpreg; \
4290 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
4291 /* Delay after an RCC peripheral clock enabling */ \
4292 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\
4293 UNUSED(tmpreg); \
4294 } while(0)
4295
4296#define __HAL_RCC_C2_UART5_CLK_ENABLE() do { \
4297 __IO uint32_t tmpreg; \
4298 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
4299 /* Delay after an RCC peripheral clock enabling */ \
4300 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\
4301 UNUSED(tmpreg); \
4302 } while(0)
4303
4304#define __HAL_RCC_C2_I2C1_CLK_ENABLE() do { \
4305 __IO uint32_t tmpreg; \
4306 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
4307 /* Delay after an RCC peripheral clock enabling */ \
4308 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\
4309 UNUSED(tmpreg); \
4310 } while(0)
4311
4312#define __HAL_RCC_C2_I2C2_CLK_ENABLE() do { \
4313 __IO uint32_t tmpreg; \
4314 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
4315 /* Delay after an RCC peripheral clock enabling */ \
4316 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\
4317 UNUSED(tmpreg); \
4318 } while(0)
4319
4320#define __HAL_RCC_C2_I2C3_CLK_ENABLE() do { \
4321 __IO uint32_t tmpreg; \
4322 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
4323 /* Delay after an RCC peripheral clock enabling */ \
4324 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\
4325 UNUSED(tmpreg); \
4326 } while(0)
4327
4328#define __HAL_RCC_C2_CEC_CLK_ENABLE() do { \
4329 __IO uint32_t tmpreg; \
4330 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
4331 /* Delay after an RCC peripheral clock enabling */ \
4332 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\
4333 UNUSED(tmpreg); \
4334 } while(0)
4335
4336#define __HAL_RCC_C2_DAC12_CLK_ENABLE() do { \
4337 __IO uint32_t tmpreg; \
4338 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
4339 /* Delay after an RCC peripheral clock enabling */ \
4340 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\
4341 UNUSED(tmpreg); \
4342 } while(0)
4343
4344#define __HAL_RCC_C2_UART7_CLK_ENABLE() do { \
4345 __IO uint32_t tmpreg; \
4346 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
4347 /* Delay after an RCC peripheral clock enabling */ \
4348 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\
4349 UNUSED(tmpreg); \
4350 } while(0)
4351
4352#define __HAL_RCC_C2_UART8_CLK_ENABLE() do { \
4353 __IO uint32_t tmpreg; \
4354 SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
4355 /* Delay after an RCC peripheral clock enabling */ \
4356 tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\
4357 UNUSED(tmpreg); \
4358 } while(0)
4359
4360#define __HAL_RCC_C2_CRS_CLK_ENABLE() do { \
4361 __IO uint32_t tmpreg; \
4362 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
4363 /* Delay after an RCC peripheral clock enabling */ \
4364 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\
4365 UNUSED(tmpreg); \
4366 } while(0)
4367
4368#define __HAL_RCC_C2_SWPMI_CLK_ENABLE() do { \
4369 __IO uint32_t tmpreg; \
4370 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
4371 /* Delay after an RCC peripheral clock enabling */ \
4372 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\
4373 UNUSED(tmpreg); \
4374 } while(0)
4375
4376#define __HAL_RCC_C2_OPAMP_CLK_ENABLE() do { \
4377 __IO uint32_t tmpreg; \
4378 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
4379 /* Delay after an RCC peripheral clock enabling */ \
4380 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\
4381 UNUSED(tmpreg); \
4382 } while(0)
4383
4384#define __HAL_RCC_C2_MDIOS_CLK_ENABLE() do { \
4385 __IO uint32_t tmpreg; \
4386 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
4387 /* Delay after an RCC peripheral clock enabling */ \
4388 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\
4389 UNUSED(tmpreg); \
4390 } while(0)
4391
4392#define __HAL_RCC_C2_FDCAN_CLK_ENABLE() do { \
4393 __IO uint32_t tmpreg; \
4394 SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
4395 /* Delay after an RCC peripheral clock enabling */ \
4396 tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\
4397 UNUSED(tmpreg); \
4398 } while(0)
4399
4400
4401#define __HAL_RCC_C2_TIM2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)
4402#define __HAL_RCC_C2_TIM3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)
4403#define __HAL_RCC_C2_TIM4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)
4404#define __HAL_RCC_C2_TIM5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)
4405#define __HAL_RCC_C2_TIM6_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)
4406#define __HAL_RCC_C2_TIM7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)
4407#define __HAL_RCC_C2_TIM12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)
4408#define __HAL_RCC_C2_TIM13_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)
4409#define __HAL_RCC_C2_TIM14_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)
4410#define __HAL_RCC_C2_LPTIM1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)
4411#define __HAL_RCC_C2_WWDG2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)
4412#define __HAL_RCC_C2_SPI2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)
4413#define __HAL_RCC_C2_SPI3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)
4414#define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)
4415#define __HAL_RCC_C2_USART2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)
4416#define __HAL_RCC_C2_USART3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)
4417#define __HAL_RCC_C2_UART4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)
4418#define __HAL_RCC_C2_UART5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)
4419#define __HAL_RCC_C2_I2C1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)
4420#define __HAL_RCC_C2_I2C2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)
4421#define __HAL_RCC_C2_I2C3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)
4422#define __HAL_RCC_C2_CEC_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)
4423#define __HAL_RCC_C2_DAC12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)
4424#define __HAL_RCC_C2_UART7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)
4425#define __HAL_RCC_C2_UART8_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)
4426#define __HAL_RCC_C2_CRS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)
4427#define __HAL_RCC_C2_SWPMI_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)
4428#define __HAL_RCC_C2_OPAMP_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)
4429#define __HAL_RCC_C2_MDIOS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)
4430#define __HAL_RCC_C2_FDCAN_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)
4431
4438#define __HAL_RCC_C2_TIM1_CLK_ENABLE() do { \
4439 __IO uint32_t tmpreg; \
4440 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
4441 /* Delay after an RCC peripheral clock enabling */ \
4442 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\
4443 UNUSED(tmpreg); \
4444 } while(0)
4445
4446#define __HAL_RCC_C2_TIM8_CLK_ENABLE() do { \
4447 __IO uint32_t tmpreg; \
4448 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
4449 /* Delay after an RCC peripheral clock enabling */ \
4450 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\
4451 UNUSED(tmpreg); \
4452 } while(0)
4453
4454#define __HAL_RCC_C2_USART1_CLK_ENABLE() do { \
4455 __IO uint32_t tmpreg; \
4456 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
4457 /* Delay after an RCC peripheral clock enabling */ \
4458 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\
4459 UNUSED(tmpreg); \
4460 } while(0)
4461
4462#define __HAL_RCC_C2_USART6_CLK_ENABLE() do { \
4463 __IO uint32_t tmpreg; \
4464 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
4465 /* Delay after an RCC peripheral clock enabling */ \
4466 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\
4467 UNUSED(tmpreg); \
4468 } while(0)
4469
4470#define __HAL_RCC_C2_SPI1_CLK_ENABLE() do { \
4471 __IO uint32_t tmpreg; \
4472 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
4473 /* Delay after an RCC peripheral clock enabling */ \
4474 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\
4475 UNUSED(tmpreg); \
4476 } while(0)
4477
4478#define __HAL_RCC_C2_SPI4_CLK_ENABLE() do { \
4479 __IO uint32_t tmpreg; \
4480 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
4481 /* Delay after an RCC peripheral clock enabling */ \
4482 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\
4483 UNUSED(tmpreg); \
4484 } while(0)
4485
4486#define __HAL_RCC_C2_TIM15_CLK_ENABLE() do { \
4487 __IO uint32_t tmpreg; \
4488 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
4489 /* Delay after an RCC peripheral clock enabling */ \
4490 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\
4491 UNUSED(tmpreg); \
4492 } while(0)
4493
4494#define __HAL_RCC_C2_TIM16_CLK_ENABLE() do { \
4495 __IO uint32_t tmpreg; \
4496 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
4497 /* Delay after an RCC peripheral clock enabling */ \
4498 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\
4499 UNUSED(tmpreg); \
4500 } while(0)
4501
4502#define __HAL_RCC_C2_TIM17_CLK_ENABLE() do { \
4503 __IO uint32_t tmpreg; \
4504 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
4505 /* Delay after an RCC peripheral clock enabling */ \
4506 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\
4507 UNUSED(tmpreg); \
4508 } while(0)
4509
4510#define __HAL_RCC_C2_SPI5_CLK_ENABLE() do { \
4511 __IO uint32_t tmpreg; \
4512 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
4513 /* Delay after an RCC peripheral clock enabling */ \
4514 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
4515 UNUSED(tmpreg); \
4516 } while(0)
4517
4518#define __HAL_RCC_C2_SAI1_CLK_ENABLE() do { \
4519 __IO uint32_t tmpreg; \
4520 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
4521 /* Delay after an RCC peripheral clock enabling */ \
4522 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\
4523 UNUSED(tmpreg); \
4524 } while(0)
4525
4526#define __HAL_RCC_C2_SAI2_CLK_ENABLE() do { \
4527 __IO uint32_t tmpreg; \
4528 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
4529 /* Delay after an RCC peripheral clock enabling */ \
4530 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\
4531 UNUSED(tmpreg); \
4532 } while(0)
4533
4534#define __HAL_RCC_C2_SAI3_CLK_ENABLE() do { \
4535 __IO uint32_t tmpreg; \
4536 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
4537 /* Delay after an RCC peripheral clock enabling */ \
4538 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\
4539 UNUSED(tmpreg); \
4540 } while(0)
4541
4542#define __HAL_RCC_C2_DFSDM1_CLK_ENABLE() do { \
4543 __IO uint32_t tmpreg; \
4544 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
4545 /* Delay after an RCC peripheral clock enabling */ \
4546 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
4547 UNUSED(tmpreg); \
4548 } while(0)
4549
4550#define __HAL_RCC_C2_HRTIM1_CLK_ENABLE() do { \
4551 __IO uint32_t tmpreg; \
4552 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
4553 /* Delay after an RCC peripheral clock enabling */ \
4554 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\
4555 UNUSED(tmpreg); \
4556 } while(0)
4557
4558#define __HAL_RCC_C2_TIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)
4559#define __HAL_RCC_C2_TIM8_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)
4560#define __HAL_RCC_C2_USART1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)
4561#define __HAL_RCC_C2_USART6_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)
4562#define __HAL_RCC_C2_SPI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)
4563#define __HAL_RCC_C2_SPI4_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)
4564#define __HAL_RCC_C2_TIM15_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)
4565#define __HAL_RCC_C2_TIM16_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)
4566#define __HAL_RCC_C2_TIM17_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)
4567#define __HAL_RCC_C2_SPI5_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
4568#define __HAL_RCC_C2_SAI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)
4569#define __HAL_RCC_C2_SAI2_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)
4570#define __HAL_RCC_C2_SAI3_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)
4571#define __HAL_RCC_C2_DFSDM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)
4572#define __HAL_RCC_C2_HRTIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)
4573
4580#define __HAL_RCC_C2_SYSCFG_CLK_ENABLE() do { \
4581 __IO uint32_t tmpreg; \
4582 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
4583 /* Delay after an RCC peripheral clock enabling */ \
4584 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
4585 UNUSED(tmpreg); \
4586 } while(0)
4587
4588#define __HAL_RCC_C2_LPUART1_CLK_ENABLE() do { \
4589 __IO uint32_t tmpreg; \
4590 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
4591 /* Delay after an RCC peripheral clock enabling */ \
4592 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\
4593 UNUSED(tmpreg); \
4594 } while(0)
4595
4596#define __HAL_RCC_C2_SPI6_CLK_ENABLE() do { \
4597 __IO uint32_t tmpreg; \
4598 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
4599 /* Delay after an RCC peripheral clock enabling */ \
4600 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\
4601 UNUSED(tmpreg); \
4602 } while(0)
4603
4604#define __HAL_RCC_C2_I2C4_CLK_ENABLE() do { \
4605 __IO uint32_t tmpreg; \
4606 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
4607 /* Delay after an RCC peripheral clock enabling */ \
4608 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\
4609 UNUSED(tmpreg); \
4610 } while(0)
4611
4612#define __HAL_RCC_C2_LPTIM2_CLK_ENABLE() do { \
4613 __IO uint32_t tmpreg; \
4614 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
4615 /* Delay after an RCC peripheral clock enabling */ \
4616 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
4617 UNUSED(tmpreg); \
4618 } while(0)
4619
4620#define __HAL_RCC_C2_LPTIM3_CLK_ENABLE() do { \
4621 __IO uint32_t tmpreg; \
4622 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
4623 /* Delay after an RCC peripheral clock enabling */ \
4624 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
4625 UNUSED(tmpreg); \
4626 } while(0)
4627
4628#define __HAL_RCC_C2_LPTIM4_CLK_ENABLE() do { \
4629 __IO uint32_t tmpreg; \
4630 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
4631 /* Delay after an RCC peripheral clock enabling */ \
4632 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
4633 UNUSED(tmpreg); \
4634 } while(0)
4635
4636#define __HAL_RCC_C2_LPTIM5_CLK_ENABLE() do { \
4637 __IO uint32_t tmpreg; \
4638 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
4639 /* Delay after an RCC peripheral clock enabling */ \
4640 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
4641 UNUSED(tmpreg); \
4642 } while(0)
4643
4644#define __HAL_RCC_C2_COMP12_CLK_ENABLE() do { \
4645 __IO uint32_t tmpreg; \
4646 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
4647 /* Delay after an RCC peripheral clock enabling */ \
4648 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\
4649 UNUSED(tmpreg); \
4650 } while(0)
4651
4652#define __HAL_RCC_C2_VREF_CLK_ENABLE() do { \
4653 __IO uint32_t tmpreg; \
4654 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
4655 /* Delay after an RCC peripheral clock enabling */ \
4656 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\
4657 UNUSED(tmpreg); \
4658 } while(0)
4659
4660#define __HAL_RCC_C2_RTC_CLK_ENABLE() do { \
4661 __IO uint32_t tmpreg; \
4662 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
4663 /* Delay after an RCC peripheral clock enabling */ \
4664 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
4665 UNUSED(tmpreg); \
4666 } while(0)
4667
4668#define __HAL_RCC_C2_SAI4_CLK_ENABLE() do { \
4669 __IO uint32_t tmpreg; \
4670 SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
4671 /* Delay after an RCC peripheral clock enabling */ \
4672 tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\
4673 UNUSED(tmpreg); \
4674 } while(0)
4675
4676
4677
4678#define __HAL_RCC_C2_SYSCFG_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)
4679#define __HAL_RCC_C2_LPUART1_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)
4680#define __HAL_RCC_C2_SPI6_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)
4681#define __HAL_RCC_C2_I2C4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)
4682#define __HAL_RCC_C2_LPTIM2_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)
4683#define __HAL_RCC_C2_LPTIM3_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)
4684#define __HAL_RCC_C2_LPTIM4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)
4685#define __HAL_RCC_C2_LPTIM5_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)
4686#define __HAL_RCC_C2_COMP12_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)
4687#define __HAL_RCC_C2_VREF_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)
4688#define __HAL_RCC_C2_RTC_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)
4689#define __HAL_RCC_C2_SAI4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)
4690
4691#endif /*DUAL_CORE*/
4692
4696#if (STM32H7_DEV_ID == 0x450UL)
4697#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00015031U) /* Resets MDMA, DMA2D, JPEG, FMC, QSPI and SDMMC1 */
4698#elif (STM32H7_DEV_ID == 0x480UL)
4699#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x01E95031U) /* Resets MDMA, DMA2D, JPEG, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 and GFXMMU */
4700#else
4701#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00E95011U) /* Resets MDMA, DMA2D, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 */
4702#endif /* STM32H7_DEV_ID == 0x450UL */
4703#define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))
4704#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))
4705#if defined(JPEG)
4706#define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))
4707#endif /* JPEG */
4708#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
4709#if defined(QUADSPI)
4710#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
4711#endif /*QUADSPI*/
4712#if defined(OCTOSPI1)
4713#define __HAL_RCC_OSPI1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))
4714#endif /*OCTOSPI1*/
4715#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))
4716#if defined(OCTOSPI2)
4717#define __HAL_RCC_OSPI2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))
4718#endif /*OCTOSPI2*/
4719#if defined(OCTOSPIM)
4720#define __HAL_RCC_IOMNGR_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))
4721#endif /*OCTOSPIM*/
4722#if defined(OTFDEC1)
4723#define __HAL_RCC_OTFDEC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))
4724#endif /*OTFDEC1*/
4725#if defined(OTFDEC2)
4726#define __HAL_RCC_OTFDEC2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))
4727#endif /*OTFDEC2*/
4728#if defined(GFXMMU)
4729#define __HAL_RCC_GFXMMU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))
4730#endif /*GFXMMU*/
4731
4732#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
4733#define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))
4734#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))
4735#if defined(JPEG)
4736#define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))
4737#endif /* JPEG */
4738#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))
4739#if defined(QUADSPI)
4740#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))
4741#endif /*QUADSPI*/
4742#if defined(OCTOSPI1)
4743#define __HAL_RCC_OSPI1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))
4744#endif /*OCTOSPI1*/
4745#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))
4746#if defined(OCTOSPI2)
4747#define __HAL_RCC_OSPI2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))
4748#endif /*OCTOSPI2*/
4749#if defined(OCTOSPIM)
4750#define __HAL_RCC_IOMNGR_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))
4751#endif /*OCTOSPIM*/
4752#if defined(OTFDEC1)
4753#define __HAL_RCC_OTFDEC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))
4754#endif /*OTFDEC1*/
4755#if defined(OTFDEC2)
4756#define __HAL_RCC_OTFDEC2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))
4757#endif /*OTFDEC2*/
4758#if defined(GFXMMU)
4759#define __HAL_RCC_GFXMMU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))
4760#endif /*GFXMMU*/
4761
4762
4763
4766#if (STM32H7_DEV_ID == 0x450UL)
4767#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0A00C023U) /* Resets DMA1, DMA2, ADC12, ART, ETHMAC, USB1OTG and USB2OTG */
4768#elif (STM32H7_DEV_ID == 0x480UL)
4769#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02000223U) /* Resets DMA1, DMA2, ADC12, CRC and USB1OTG */
4770#else
4771#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02008023U) /* Resets DMA1, DMA2, ADC12, ETHMAC and USB1OTG */
4772#endif /* STM32H7_DEV_ID == 0x450UL */
4773#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
4774#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
4775#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))
4776#if defined(DUAL_CORE)
4777#define __HAL_RCC_ART_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST))
4778#endif /*DUAL_CORE*/
4779#if defined(RCC_AHB1RSTR_CRCRST)
4780#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
4781#endif
4782#if defined(ETH)
4783#define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))
4784#endif /*ETH*/
4785#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))
4786#if defined(USB2_OTG_FS)
4787#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))
4788#endif /*USB2_OTG_FS*/
4789
4790#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
4791#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))
4792#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))
4793#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))
4794#if defined(DUAL_CORE)
4795#define __HAL_RCC_ART_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST))
4796#endif /*DUAL_CORE*/
4797#if defined(RCC_AHB1RSTR_CRCRST)
4798#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))
4799#endif
4800#if defined(ETH)
4801#define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))
4802#endif /*ETH*/
4803#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))
4804#if defined(USB2_OTG_FS)
4805#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))
4806#endif /*USB2_OTG_FS*/
4807
4810#if (STM32H7_DEV_ID == 0x450UL)
4811#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000271U) /* Resets DCMI, CRYPT, HASH, RNG and SDMMC2 */
4812#elif (STM32H7_DEV_ID == 0x480UL)
4813#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000A75U) /* Resets DCMI_PSSI, HSEM, CRYPT, HASH, RNG, SDMMC2 and BDMA1 */
4814#else
4815#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00030271U) /* Resets DCMI_PSSI, CRYPT, HASH, RNG, SDMMC2, FMAC and CORDIC */
4816#endif /* STM32H7_DEV_ID == 0x450UL */
4817#if defined(DCMI) && defined(PSSI)
4818#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))
4819#define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/
4820#else
4821#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
4822#endif /* DCMI && PSSI */
4823#if defined(CRYP)
4824#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
4825#endif /* CRYP */
4826#if defined(HASH)
4827#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
4828#endif /* HASH */
4829#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
4830#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))
4831#if defined(FMAC)
4832#define __HAL_RCC_FMAC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_FMACRST))
4833#endif /*FMAC*/
4834#if defined(CORDIC)
4835#define __HAL_RCC_CORDIC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CORDICRST))
4836#endif /*CORDIC*/
4837#if defined(RCC_AHB2RSTR_HSEMRST)
4838#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))
4839#endif
4840#if defined(BDMA1)
4841#define __HAL_RCC_BDMA1_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))
4842#endif /*BDMA1*/
4843
4844#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
4845#if defined(DCMI) && defined(PSSI)
4846#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))
4847#define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility*/
4848#else
4849#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))
4850#endif /* DCMI && PSSI */
4851#if defined(CRYP)
4852#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))
4853#endif /* CRYP */
4854#if defined(HASH)
4855#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))
4856#endif /* HASH */
4857#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))
4858#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))
4859#if defined(FMAC)
4860#define __HAL_RCC_FMAC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_FMACRST))
4861#endif /*FMAC*/
4862#if defined(CORDIC)
4863#define __HAL_RCC_CORDIC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CORDICRST))
4864#endif /*CORDIC*/
4865#if defined(RCC_AHB2RSTR_HSEMRST)
4866#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))
4867#endif
4868#if defined(BDMA1)
4869#define __HAL_RCC_BDMA1_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))
4870#endif /*BDMA1*/
4871
4872
4876#if (STM32H7_DEV_ID == 0x450UL)
4877#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032807FFU) /* Resets GPIOA..GPIOK, CRC, BDMA, ADC3 and HSEM */
4878#elif (STM32H7_DEV_ID == 0x480UL)
4879#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x002007FFU) /* Resets GPIOA..GPIOK and BDMA2 */
4880#else
4881#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032806FFU) /* Resets GPIOA..GPIOH, GPIOJ, GPIOK, CRC, BDMA, ADC3 and HSEM */
4882#endif /* STM32H7_DEV_ID == 0x450UL */
4883#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)
4884#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)
4885#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)
4886#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)
4887#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)
4888#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)
4889#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)
4890#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)
4891#if defined(GPIOI)
4892#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)
4893#endif /* GPIOI */
4894#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)
4895#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)
4896#if defined(RCC_AHB4RSTR_CRCRST)
4897#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)
4898#endif
4899#if defined(BDMA2)
4900#define __HAL_RCC_BDMA2_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)
4901#define __HAL_RCC_BDMA_FORCE_RESET() __HAL_RCC_BDMA2_FORCE_RESET() /* for API backward compatibility*/
4902#else
4903#define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)
4904#endif /*BDMA2*/
4905#if defined(ADC3)
4906#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)
4907#endif /*ADC3*/
4908#if defined(RCC_AHB4RSTR_HSEMRST)
4909#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)
4910#endif
4911
4912#define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U)
4913#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)
4914#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)
4915#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)
4916#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)
4917#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)
4918#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)
4919#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)
4920#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)
4921#if defined(GPIOI)
4922#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)
4923#endif /* GPIOI */
4924#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)
4925#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)
4926#if defined(RCC_AHB4RSTR_CRCRST)
4927#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)
4928#endif
4929#if defined(BDMA2)
4930#define __HAL_RCC_BDMA2_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)
4931#define __HAL_RCC_BDMA_RELEASE_RESET() __HAL_RCC_BDMA2_RELEASE_RESET() /* for API backward compatibility*/
4932#else
4933#define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)
4934#endif /*BDMA2*/
4935#if defined(ADC3)
4936#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)
4937#endif /*ADC3*/
4938#if defined(RCC_AHB4RSTR_HSEMRST)
4939#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)
4940#endif
4941
4944#if (STM32H7_DEV_ID == 0x450UL)
4945#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000018U) /* Rests LTDC and DSI */
4946#else
4947#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000008U) /* Rests LTDC */
4948#endif /* STM32H7_DEV_ID == 0x450UL */
4949#if defined(LTDC)
4950#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)
4951#endif /* LTDC */
4952#if defined(DSI)
4953#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST)
4954#endif /*DSI*/
4955
4956#define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U)
4957#if defined(LTDC)
4958#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)
4959#endif /* LTDC */
4960#if defined(DSI)
4961#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST)
4962#endif /*DSI*/
4963
4966#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL)
4967#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xE8FFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, CEC, DAC1(2), UART7 and UART8 */
4968#else
4969#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xEAFFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, I2C5, CEC, DAC12, UART7 and UART8 */
4970#endif /* STM32H7_DEV_ID == 0x450UL */
4971#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL)
4972#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x00000136U) /* Resets CRS, SWP, OPAMP, MDIOS and FDCAN */
4973#else
4974#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x03000136U) /* Resets CRS, SWP, OPAMP, MDIOS, FDCAN, TIM23 and TIM24 */
4975#endif /* STM32H7_DEV_ID == 0x450UL */
4976#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)
4977#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)
4978#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)
4979#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)
4980#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)
4981#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)
4982#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)
4983#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)
4984#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)
4985#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)
4986#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)
4987#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)
4988#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)
4989#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)
4990#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)
4991#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)
4992#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)
4993#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)
4994#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)
4995#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)
4996#if defined(I2C5)
4997#define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C5RST)
4998#endif /* I2C5 */
4999#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)
5000#define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)
5001#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)
5002#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)
5003#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)
5004#define __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)
5005#define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)
5006#define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)
5007#define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)
5008#if defined(TIM23)
5009#define __HAL_RCC_TIM23_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM23RST)
5010#endif /* TIM23 */
5011#if defined(TIM24)
5012#define __HAL_RCC_TIM24_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM24RST)
5013#endif /* TIM24 */
5014
5015#define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U)
5016#define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U)
5017#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)
5018#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)
5019#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)
5020#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)
5021#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)
5022#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)
5023#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)
5024#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)
5025#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)
5026#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)
5027#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)
5028#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)
5029#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)
5030#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)
5031#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)
5032#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)
5033#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)
5034#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)
5035#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)
5036#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)
5037#if defined(I2C5)
5038#define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C5RST)
5039#endif /* I2C5 */
5040#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)
5041#define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)
5042#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)
5043#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)
5044#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)
5045#define __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)
5046#define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)
5047#define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)
5048#define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)
5049#if defined(TIM23)
5050#define __HAL_RCC_TIM23_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM23RST)
5051#endif /* TIM23 */
5052#if defined(TIM24)
5053#define __HAL_RCC_TIM24_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM24RST)
5054#endif /* TIM24 */
5055
5058#if (STM32H7_DEV_ID == 0x450UL)
5059#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x31D73033U) /* Resets TIM1, TIM8, USART1, USART6, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1..SAI3, DFSDM1 and HRTIM */
5060#elif (STM32H7_DEV_ID == 0x480UL)
5061#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x40D730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1, SAI2 and DFSDM1 */
5062#else
5063#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x405730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1 and DFSDM1 */
5064#endif /* STM32H7_DEV_ID == 0x450UL */
5065#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)
5066#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)
5067#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)
5068#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)
5069#if defined(UART9)
5070#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)
5071#endif /*UART9*/
5072#if defined(USART10)
5073#define __HAL_RCC_USART10_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)
5074#endif /*USART10*/
5075#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)
5076#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)
5077#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)
5078#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)
5079#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)
5080#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)
5081#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)
5082#if defined(SAI2)
5083#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)
5084#endif /* SAI2 */
5085#if defined(SAI3)
5086#define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)
5087#endif /*SAI3*/
5088#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)
5089#if defined(HRTIM1)
5090#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)
5091#endif /*HRTIM1*/
5092
5093#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
5094#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)
5095#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)
5096#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)
5097#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)
5098#if defined(UART9)
5099#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)
5100#endif /*UART9*/
5101#if defined(USART10)
5102#define __HAL_RCC_USART10_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)
5103#endif /*USART10*/
5104#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)
5105#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)
5106#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)
5107#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)
5108#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)
5109#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)
5110#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)
5111#if defined(SAI2)
5112#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)
5113#endif /* SAI2 */
5114#if defined(SAI3)
5115#define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)
5116#endif /*SAI3*/
5117#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)
5118#if defined(HRTIM1)
5119#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)
5120#endif /*HRTIM1*/
5121
5125#if (STM32H7_DEV_ID == 0x450UL)
5126#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0020DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF and SAI4 */
5127#elif (STM32H7_DEV_ID == 0x480UL)
5128#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0C00E6AAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2, LPTIM3, DAC2, COMP12, VREF, DTS and DFSDM2 */
5129#else
5130#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0420DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF, SAI4 and DTS */
5131#endif /* STM32H7_DEV_ID == 0x450UL */
5132#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)
5133#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)
5134#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)
5135#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)
5136#define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)
5137#define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)
5138#if defined(LPTIM4)
5139#define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)
5140#endif /*LPTIM4*/
5141#if defined(LPTIM5)
5142#define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)
5143#endif /*LPTIM5*/
5144#if defined(DAC2)
5145#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)
5146#endif /*DAC2*/
5147#define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)
5148#define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)
5149#if defined(SAI4)
5150#define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)
5151#endif /*SAI4*/
5152#if defined(DTS)
5153#define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)
5154#endif /*DTS*/
5155#if defined(DFSDM2_BASE)
5156#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)
5157#endif /*DFSDM2*/
5158
5159#define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U)
5160#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)
5161#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)
5162#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)
5163#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)
5164#define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)
5165#define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)
5166#if defined(LPTIM4)
5167#define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)
5168#endif /*LPTIM4*/
5169#if defined(LPTIM5)
5170#define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)
5171#endif /*LPTIM5*/
5172#if defined(RCC_APB4RSTR_DAC2RST)
5173#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)
5174#endif
5175#define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)
5176#define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)
5177#if defined(SAI4)
5178#define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)
5179#endif /*SAI4*/
5180#if defined(DTS)
5181#define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)
5182#endif /*DTS*/
5183#if defined(DFSDM2_BASE)
5184#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)
5185#endif /*DFSDM2*/
5186
5195#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
5196#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
5197#if defined(JPEG)
5198#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
5199#endif /* JPEG */
5200#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
5201#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
5202#if defined(QUADSPI)
5203#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
5204#endif /*QUADSPI*/
5205#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
5206#if defined(OCTOSPI1)
5207#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))
5208#endif /*OCTOSPI1*/
5209#if defined(OCTOSPI2)
5210#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))
5211#endif /*OCTOSPI2*/
5212#if defined(OCTOSPIM)
5213#define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))
5214#endif /*OCTOSPIM*/
5215#if defined(OTFDEC1)
5216#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))
5217#endif /*OTFDEC1*/
5218#if defined(OTFDEC2)
5219#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))
5220#endif /*OTFDEC2*/
5221#if defined(GFXMMU)
5222#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))
5223#endif /*GFXMMU*/
5224#if defined(CD_AXISRAM2_BASE)
5225#define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))
5226#endif
5227#if defined(CD_AXISRAM3_BASE)
5228#define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))
5229#endif
5230#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
5231#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
5232#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
5233#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
5234#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
5235#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE
5236#else
5237#define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN))
5238#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE /* For backward compatibility */
5239#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
5240
5241#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
5242#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
5243#if defined(JPEG)
5244#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
5245#endif /* JPEG */
5246#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
5247#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
5248#if defined(QUADSPI)
5249#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
5250#endif /*QUADSPI*/
5251#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
5252#if defined(OCTOSPI1)
5253#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))
5254#endif /*OCTOSPI1*/
5255#if defined(OCTOSPI2)
5256#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))
5257#endif /*OCTOSPI2*/
5258#if defined(OCTOSPIM)
5259#define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))
5260#endif /*OCTOSPIM*/
5261#if defined(OTFDEC1)
5262#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))
5263#endif /*OTFDEC1*/
5264#if defined(OTFDEC2)
5265#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))
5266#endif /*OTFDEC2*/
5267#if defined(GFXMMU)
5268#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))
5269#endif /*GFXMMU*/
5270#if defined(CD_AXISRAM2_BASE)
5271#define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))
5272#endif
5273#if defined(CD_AXISRAM3_BASE)
5274#define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))
5275#endif
5276#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
5277#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
5278#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
5279#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
5280#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
5281#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE
5282#else
5283#define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN))
5284#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE /* For backward compatibility */
5285#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
5286
5294#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U)
5295#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U)
5296#if defined(JPEG)
5297#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U)
5298#endif /* JPEG */
5299#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U)
5300#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U)
5301#if defined(QUADSPI)
5302#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U)
5303#endif /*QUADSPI*/
5304#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U)
5305#if defined(OCTOSPI1)
5306#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) != 0U)
5307#endif /*OCTOSPI1*/
5308#if defined(OCTOSPI2)
5309#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) != 0U)
5310#endif /*OCTOSPI2*/
5311#if defined(OCTOSPIM)
5312#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) != 0U)
5313#endif /*OCTOSPIM*/
5314#if defined(OTFDEC1)
5315#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)
5316#endif /*OTFDEC1*/
5317#if defined(OTFDEC2)
5318#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)
5319#endif /*OTFDEC2*/
5320#if defined(GFXMMU)
5321#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) != 0U)
5322#endif /*GFXMMU*/
5323#if defined(CD_AXISRAM2_BASE)
5324#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) != 0U)
5325#endif
5326#if defined(CD_AXISRAM3_BASE)
5327#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) != 0U)
5328#endif
5329#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U)
5330#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U)
5331#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U)
5332#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
5333#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)
5334#else
5335#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U)
5336#endif
5337
5338#define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U)
5339#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U)
5340#if defined(JPEG)
5341#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U)
5342#endif /* JPEG */
5343#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U)
5344#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U)
5345#if defined(QUADSPI)
5346#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U)
5347#endif /*QUADSPI*/
5348#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U)
5349#if defined(OCTOSPI1)
5350#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) == 0U)
5351#endif /*OCTOSPI1*/
5352#if defined(OCTOSPI2)
5353#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) == 0U)
5354#endif /*OCTOSPI2*/
5355#if defined(OCTOSPIM)
5356#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)
5357#endif /*OCTOSPIM*/
5358#if defined(OTFDEC1)
5359#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) == 0U)
5360#endif /*OTFDEC1*/
5361#if defined(OTFDEC2)
5362#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) == 0U)
5363#endif /*OTFDEC2*/
5364#if defined(GFXMMU)
5365#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) == 0U)
5366#endif /*GFXMMU*/
5367#if defined(CD_AXISRAM2_BASE)
5368#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) == 0U)
5369#endif
5370#if defined(CD_AXISRAM3_BASE)
5371#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) == 0U)
5372#endif
5373#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U)
5374#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U)
5375#define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U)
5376#if defined(RCC_AHB3LPENR_AXISRAMLPEN)
5377#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)
5378#else
5379#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U)
5380#endif /* RCC_AHB3LPENR_AXISRAMLPEN */
5381
5389#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
5390#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
5391#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
5392#if defined(RCC_AHB1LPENR_CRCLPEN)
5393#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
5394#endif
5395#if defined(ETH)
5396#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
5397#endif /*ETH*/
5398#if defined(DUAL_CORE)
5399#define __HAL_RCC_ART_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN))
5400#endif /*DUAL_CORE*/
5401#if defined(ETH)
5402#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
5403#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
5404#endif /*ETH*/
5405#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
5406#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
5407#if defined(USB2_OTG_FS)
5408#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
5409#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
5410#endif /* USB2_OTG_FS */
5411
5412#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
5413#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
5414#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
5415#if defined(RCC_AHB1LPENR_CRCLPEN)
5416#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))
5417#endif
5418#if defined(ETH)
5419#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
5420#endif /*ETH*/
5421#if defined(DUAL_CORE)
5422#define __HAL_RCC_ART_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN))
5423#endif /*DUAL_CORE*/
5424#if defined(ETH)
5425#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
5426#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
5427#endif /*ETH*/
5428#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
5429#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
5430#if defined(USB2_OTG_FS)
5431#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
5432#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
5433#endif /* USB2_OTG_FS */
5434
5442#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U)
5443#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U)
5444#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U)
5445#if defined(RCC_AHB1LPENR_CRCLPEN)
5446#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != 0U)
5447#endif
5448#if defined(ETH)
5449#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U)
5450#endif /*ETH*/
5451#if defined(DUAL_CORE)
5452#define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) != 0U)
5453#endif /*DUAL_CORE*/
5454#if defined(ETH)
5455#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U)
5456#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U)
5457#endif /*ETH*/
5458#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U)
5459#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)
5460#if defined(USB2_OTG_FS)
5461#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U)
5462#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U)
5463#endif /* USB2_OTG_FS */
5464
5465#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U)
5466#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U)
5467#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U)
5468#if defined(RCC_AHB1LPENR_CRCLPEN)
5469#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == 0U)
5470#endif
5471#if defined(ETH)
5472#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U)
5473#endif /* ETH */
5474#if defined(DUAL_CORE)
5475#define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) == 0U)
5476#endif /*DUAL_CORE*/
5477#if defined(ETH)
5478#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U)
5479#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U)
5480#endif /* ETH */
5481#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U)
5482#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)
5483#if defined(USB2_OTG_FS)
5484#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U)
5485#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U)
5486#endif /* USB2_OTG_FS */
5487
5488
5496#if defined(DCMI) && defined(PSSI)
5497#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))
5498#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility*/
5499#else
5500#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
5501#endif /* DCMI && PSSI */
5502#if defined(CRYP)
5503#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
5504#endif /* CRYP */
5505#if defined(HASH)
5506#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
5507#endif /* HASH */
5508#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
5509#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
5510#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
5511#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))
5512#endif
5513#if defined(FMAC)
5514#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_FMACLPEN))
5515#endif /* FMAC */
5516#if defined(CORDIC)
5517#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CORDICLPEN))
5518#endif /* CORDIC */
5519#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
5520#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
5521#else
5522#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))
5523#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
5524#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
5525#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
5526#else
5527#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))
5528#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
5529#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
5530#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
5531#endif
5532
5533#if defined(DCMI) && defined(PSSI)
5534#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))
5535#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility*/
5536#else
5537#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
5538#endif /* DCMI && PSSI */
5539#if defined(CRYP)
5540#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
5541#endif /* CRYP */
5542#if defined(HASH)
5543#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
5544#endif /* HASH */
5545#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
5546#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
5547#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
5548#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))
5549#endif
5550#if defined(FMAC)
5551#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_FMACLPEN))
5552#endif /* FMAC */
5553#if defined(CORDIC)
5554#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CORDICLPEN))
5555#endif /* CORDIC */
5556#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
5557#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
5558#else
5559#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))
5560#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
5561#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
5562#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
5563#else
5564#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))
5565#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
5566#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
5567#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
5568#endif
5569
5577#if defined(DCMI) && defined(PSSI)
5578#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) != 0U)
5579#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() /* for API backward compatibility*/
5580#else
5581#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U)
5582#endif /* DCMI && PSSI */
5583#if defined(CRYP)
5584#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U)
5585#endif /* CRYP */
5586#if defined(HASH)
5587#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U)
5588#endif /* HASH */
5589#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U)
5590#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U)
5591#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
5592#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)
5593#endif
5594#if defined(FMAC)
5595#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) != 0U)
5596#endif /* FMAC */
5597#if defined(CORDIC)
5598#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) != 0U)
5599#endif /* CORDIC */
5600#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
5601#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)
5602#else
5603#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)
5604#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
5605#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
5606#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U)
5607#else
5608#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)
5609#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
5610#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
5611#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U)
5612#endif /* RCC_AHB2LPENR_D2SRAM3LPEN */
5613
5614#if defined(DCMI) && defined(PSSI)
5615#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) == 0U)
5616#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() /* for API backward compatibility*/
5617#else
5618#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U)
5619#endif /* DCMI && PSSI */
5620#if defined(CRYP)
5621#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U)
5622#endif /* CRYP */
5623#if defined(HASH)
5624#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U)
5625#endif /* HASH */
5626#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U)
5627#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)
5628#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)
5629#endif
5630#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U)
5631#if defined(FMAC)
5632#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) == 0U)
5633#endif /* FMAC */
5634#if defined(CORDIC)
5635#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) == 0U)
5636#endif /* CORDIC */
5637#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)
5638#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)
5639#else
5640#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)
5641#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */
5642#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)
5643#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U)
5644#else
5645#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)
5646#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */
5647#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)
5648#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U)
5649#endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/
5650
5651
5659#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
5660#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
5661#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
5662#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
5663#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
5664#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
5665#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
5666#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
5667#if defined(GPIOI)
5668#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
5669#endif /* GPIOI */
5670#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
5671#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
5672#if defined(RCC_AHB4LPENR_CRCLPEN)
5673#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
5674#endif
5675#if defined(BDMA2)
5676#define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)
5677#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/
5678#else
5679#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
5680#endif /* BDMA2 */
5681#if defined(ADC3)
5682#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
5683#endif /* ADC3 */
5684#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
5685#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
5686#define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_SRDSRAMLPEN))
5687#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/
5688#else
5689#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
5690#endif /* RCC_AHB4LPENR_SRDSRAMLPEN */
5691
5692#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
5693#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
5694#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
5695#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
5696#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
5697#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
5698#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
5699#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
5700#if defined(GPIOI)
5701#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
5702#endif /* GPIOI */
5703#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
5704#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
5705#if defined(RCC_AHB4LPENR_CRCLPEN)
5706#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
5707#endif
5708#if defined(BDMA2)
5709#define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)
5710#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE /* For API backward compatibility*/
5711#else
5712#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
5713#endif /*BDMA2*/
5714#if defined(ADC3)
5715#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
5716#endif /*ADC3*/
5717#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
5718#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
5719#define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))
5720#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE
5721#else
5722#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
5723#endif
5724
5725
5733#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U)
5734#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U)
5735#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U)
5736#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U)
5737#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U)
5738#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U)
5739#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U)
5740#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U)
5741#if defined(GPIOI)
5742#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U)
5743#endif /* GPIOI */
5744#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U)
5745#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U)
5746#if defined(RCC_AHB4LPENR_CRCLPEN)
5747#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U)
5748#endif
5749#if defined(BDMA2)
5750#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) != 0U)
5751#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/
5752#else
5753#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U)
5754#endif /*BDMA2*/
5755#if defined(ADC3)
5756#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U)
5757#endif /*ADC3*/
5758#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U)
5759#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
5760#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)
5761#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/
5762#else
5763#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)
5764#endif
5765
5766#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U)
5767#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U)
5768#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U)
5769#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U)
5770#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U)
5771#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U)
5772#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U)
5773#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U)
5774#if defined(GPIOI)
5775#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U)
5776#endif /* GPIOI */
5777#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U)
5778#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U)
5779#if defined(RCC_AHB4LPENR_CRCLPEN)
5780#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U)
5781#endif
5782#if defined(BDMA2)
5783#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) == 0U)
5784#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/
5785#else
5786#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U)
5787#endif /*BDMA2*/
5788#if defined(ADC3)
5789#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U)
5790#endif /*ADC3*/
5791#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U)
5792#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)
5793#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)
5794#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/
5795#else
5796#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)
5797#endif
5798
5799
5807#if defined(LTDC)
5808#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
5809#endif /* LTDC */
5810#if defined(DSI)
5811#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
5812#endif /*DSI*/
5813#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
5814
5815#if defined(LTDC)
5816#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
5817#endif /* LTDC */
5818#if defined(DSI)
5819#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
5820#endif /*DSI*/
5821#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
5822
5823
5831#if defined(LTDC)
5832#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U)
5833#endif /* LTDC */
5834#if defined(DSI)
5835#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) != 0U)
5836#endif /*DSI*/
5837#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
5838
5839#if defined(LTDC)
5840#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U)
5841#endif /* LTDC */
5842#if defined(DSI)
5843#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) == 0U)
5844#endif /*DSI*/
5845#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)
5846
5847
5855#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
5856#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
5857#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
5858#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
5859#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
5860#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
5861#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
5862#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
5863#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
5864#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
5865
5866#if defined(DUAL_CORE)
5867#define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
5868#endif /*DUAL_CORE*/
5869
5870#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
5871#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
5872#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
5873#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
5874#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
5875#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
5876#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
5877#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
5878#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
5879#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
5880#if defined(I2C5)
5881#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C5LPEN)
5882#endif /* I2C5 */
5883#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
5884#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
5885#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
5886#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
5887#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
5888#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
5889#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
5890#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
5891#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
5892#if defined(TIM23)
5893#define __HAL_RCC_TIM23_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM23LPEN)
5894#endif /* TIM23 */
5895#if defined(TIM24)
5896#define __HAL_RCC_TIM24_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM24LPEN)
5897#endif /* TIM24 */
5898
5899
5900#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
5901#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
5902#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
5903#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
5904#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
5905#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
5906#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
5907#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
5908#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
5909#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
5910
5911#if defined(DUAL_CORE)
5912#define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
5913#endif /*DUAL_CORE*/
5914
5915#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
5916#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
5917#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
5918#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
5919#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
5920#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
5921#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
5922#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
5923#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
5924#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
5925#if defined(I2C5)
5926#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C5LPEN)
5927#endif /* I2C5 */
5928#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
5929#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
5930#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
5931#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
5932#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
5933#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
5934#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
5935#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
5936#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
5937#if defined(TIM23)
5938#define __HAL_RCC_TIM23_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM23LPEN)
5939#endif /* TIM23 */
5940#if defined(TIM24)
5941#define __HAL_RCC_TIM24_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM24LPEN)
5942#endif /* TIM24 */
5943
5944
5952#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U)
5953#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U)
5954#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U)
5955#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U)
5956#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U)
5957#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U)
5958#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U)
5959#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U)
5960#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U)
5961#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U)
5962#if defined(DUAL_CORE)
5963#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) != 0U)
5964#endif /*DUAL_CORE*/
5965#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U)
5966#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U)
5967#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)
5968#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U)
5969#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U)
5970#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U)
5971#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U)
5972#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U)
5973#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U)
5974#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U)
5975#if defined(I2C5)
5976#define __HAL_RCC_I2C5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) != 0U)
5977#endif /* I2C5 */
5978#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U)
5979#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U)
5980#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U)
5981#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U)
5982#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U)
5983#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U)
5984#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U)
5985#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U)
5986#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U)
5987#if defined(TIM23)
5988#define __HAL_RCC_TIM23_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) != 0U)
5989#endif /* TIM23 */
5990#if defined(TIM24)
5991#define __HAL_RCC_TIM24_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) != 0U)
5992#endif /* TIM24 */
5993
5994#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U)
5995#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U)
5996#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U)
5997#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U)
5998#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U)
5999#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U)
6000#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U)
6001#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U)
6002#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U)
6003#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U)
6004#if defined(DUAL_CORE)
6005#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) == 0U)
6006#endif /*DUAL_CORE*/
6007#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U)
6008#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U)
6009#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)
6010#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U)
6011#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U)
6012#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U)
6013#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U)
6014#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U)
6015#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U)
6016#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U)
6017#if defined(I2C5)
6018#define __HAL_RCC_I2C5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) == 0U)
6019#endif /* I2C5 */
6020#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U)
6021#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U)
6022#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U)
6023#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U)
6024#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U)
6025#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U)
6026#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U)
6027#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U)
6028#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U)
6029#if defined(TIM23)
6030#define __HAL_RCC_TIM23_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) == 0U)
6031#endif /* TIM23 */
6032#if defined(TIM24)
6033#define __HAL_RCC_TIM24_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) == 0U)
6034#endif /* TIM24 */
6035
6036
6044#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
6045#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
6046#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
6047#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
6048#if defined(UART9)
6049#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)
6050#endif /*UART9*/
6051#if defined(USART10)
6052#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)
6053#endif /*USART10*/
6054#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
6055#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
6056#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
6057#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
6058#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
6059#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
6060#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
6061#if defined(SAI2)
6062#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
6063#endif /* SAI2 */
6064#if defined(SAI3)
6065#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
6066#endif /*SAI3*/
6067#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
6068#if defined(HRTIM1)
6069#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
6070#endif /*HRTIM1*/
6071
6072#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
6073#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
6074#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
6075#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
6076#if defined(UART9)
6077#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)
6078#endif /*UART9*/
6079#if defined(USART10)
6080#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)
6081#endif /*USART10*/
6082#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
6083#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
6084#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
6085#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
6086#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
6087#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
6088#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
6089#if defined(SAI2)
6090#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
6091#endif /* SAI2 */
6092#if defined(SAI3)
6093#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
6094#endif /*SAI3*/
6095#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
6096#if defined(HRTIM1)
6097#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
6098#endif /*HRTIM1*/
6099
6100
6108#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U)
6109#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U)
6110#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)
6111#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)
6112#if defined(UART9)
6113#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)
6114#endif /*UART9*/
6115#if defined(USART10)
6116#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)
6117#endif /*USART10*/
6118#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)
6119#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U)
6120#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U)
6121#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U)
6122#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U)
6123#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U)
6124#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U)
6125#if defined(SAI2)
6126#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U)
6127#endif /* SAI2 */
6128#if defined(SAI3)
6129#define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U)
6130#endif /*SAI3*/
6131#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)
6132#if defined(HRTIM1)
6133#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U)
6134#endif /*HRTIM1*/
6135
6136#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U)
6137#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U)
6138#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)
6139#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)
6140#if defined(UART9)
6141#define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)
6142#endif /*UART9*/
6143#if defined(USART10)
6144#define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)
6145#endif /*USART10*/
6146#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)
6147#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U)
6148#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U)
6149#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U)
6150#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U)
6151#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U)
6152#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U)
6153#if defined(SAI2)
6154#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U)
6155#endif /* SAI2 */
6156#if defined(SAI3)
6157#define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U)
6158#endif /*SAI3*/
6159#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)
6160#if defined(HRTIM1)
6161#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U)
6162#endif /*HRTIM1*/
6163
6171#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
6172#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
6173#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
6174#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
6175#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
6176#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
6177#if defined(LPTIM4)
6178#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
6179#endif /*LPTIM4*/
6180#if defined(LPTIM5)
6181#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
6182#endif /*LPTIM5*/
6183#if defined(DAC2)
6184#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)
6185#endif /*DAC2*/
6186#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
6187#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
6188#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
6189#if defined(SAI4)
6190#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
6191#endif /*SAI4*/
6192#if defined(DTS)
6193#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)
6194#endif /*DTS*/
6195#if defined(DFSDM2_BASE)
6196#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)
6197#endif /*DFSDM2*/
6198
6199#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
6200#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
6201#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
6202#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
6203#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
6204#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
6205#if defined(LPTIM4)
6206#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
6207#endif /*LPTIM4*/
6208#if defined(LPTIM5)
6209#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
6210#endif /*LPTIM5*/
6211#if defined(DAC2)
6212#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)
6213#endif /*DAC2*/
6214#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
6215#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
6216#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
6217#if defined(SAI4)
6218#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
6219#endif /*SAI4*/
6220#if defined(DTS)
6221#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)
6222#endif /*DTS*/
6223#if defined(DFSDM2_BASE)
6224#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)
6225#endif /*DFSDM2*/
6226
6227
6235#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U)
6236#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)
6237#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U)
6238#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U)
6239#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U)
6240#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U)
6241#if defined(LPTIM4)
6242#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U)
6243#endif /*LPTIM4*/
6244#if defined(LPTIM5)
6245#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U)
6246#endif /*LPTIM5*/
6247#if defined(DAC2)
6248#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) != 0U)
6249#endif /*DAC2*/
6250#define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U)
6251#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U)
6252#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U)
6253#if defined(SAI4)
6254#define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U)
6255#endif /*SAI4*/
6256#if defined(DTS)
6257#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) != 0U)
6258#endif /*DTS*/
6259#if defined(DFSDM2_BASE)
6260#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)
6261#endif /*DFSDM2*/
6262
6263#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U)
6264#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)
6265#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U)
6266#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U)
6267#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U)
6268#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U)
6269#if defined(LPTIM4)
6270#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U)
6271#endif /*LPTIM4*/
6272#if defined(LPTIM5)
6273#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U)
6274#endif /*LPTIM5*/
6275#if defined(DAC2)
6276#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) == 0U)
6277#endif /*DAC2*/
6278#define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U)
6279#define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U)
6280#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U)
6281#if defined(SAI4)
6282#define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U)
6283#endif /*SAI4*/
6284#if defined(DTS)
6285#define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) == 0U)
6286#endif /*DTS*/
6287#if defined(DFSDM2_BASE)
6288#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)
6289#endif /*DFSDM2*/
6290
6291
6292#if defined(DUAL_CORE)
6293
6300#define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
6301#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
6302#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
6303#define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
6304#define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
6305#define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
6306#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
6307#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
6308#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
6309#define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
6310#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
6311
6312
6313#define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
6314#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
6315#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
6316#define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
6317#define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
6318#define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
6319#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
6320#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
6321#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
6322#define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
6323#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
6324
6325
6326
6334#define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
6335#define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
6336#define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
6337#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
6338#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
6339#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
6340#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
6341#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
6342#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
6343#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
6344
6345#define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
6346#define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
6347#define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
6348#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
6349#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
6350#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
6351#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
6352#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
6353#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
6354#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
6355
6363#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
6364#if defined(CRYP)
6365#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
6366#endif /* CRYP */
6367#if defined(HASH)
6368#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
6369#endif /* HASH */
6370#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
6371#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
6372#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
6373#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
6374#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
6375
6376#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
6377#if defined(CRYP)
6378#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
6379#endif /* CRYP */
6380#if defined(HASH)
6381#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
6382#endif /* HASH */
6383#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
6384#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
6385#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
6386#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
6387#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
6388
6396#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
6397#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
6398#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
6399#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
6400#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
6401#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
6402#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
6403#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
6404#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
6405#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
6406#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
6407#define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
6408#define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
6409#define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
6410#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
6411#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
6412
6413#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
6414#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
6415#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
6416#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
6417#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
6418#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
6419#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
6420#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
6421#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
6422#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
6423#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
6424#define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
6425#define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
6426#define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
6427#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
6428#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
6429
6437#define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
6438#define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
6439#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
6440
6441#define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
6442#define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
6443#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
6444
6452#define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
6453#define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
6454#define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
6455#define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
6456#define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
6457#define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
6458#define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
6459#define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
6460#define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
6461#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
6462#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
6463#define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
6464#define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
6465#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
6466#define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
6467#define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
6468#define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
6469#define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
6470#define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
6471#define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
6472#define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
6473#define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
6474#define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
6475#define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
6476#define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
6477#define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
6478#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
6479#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
6480#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
6481#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
6482
6483
6484#define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
6485#define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
6486#define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
6487#define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
6488#define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
6489#define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
6490#define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
6491#define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
6492#define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
6493#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
6494#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
6495#define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
6496#define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
6497#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
6498#define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
6499#define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
6500#define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
6501#define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
6502#define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
6503#define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
6504#define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
6505#define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
6506#define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
6507#define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
6508#define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
6509#define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
6510#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
6511#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
6512#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
6513#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
6514
6522#define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
6523#define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
6524#define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
6525#define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
6526#define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
6527#define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
6528#define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
6529#define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
6530#define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
6531#define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
6532#define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
6533#define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
6534#define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
6535#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
6536#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
6537
6538#define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
6539#define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
6540#define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
6541#define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
6542#define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
6543#define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
6544#define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
6545#define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
6546#define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
6547#define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
6548#define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
6549#define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
6550#define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
6551#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
6552#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
6553
6561#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
6562#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
6563#define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
6564#define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
6565#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
6566#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
6567#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
6568#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
6569#define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
6570#define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
6571#define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
6572#define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
6573
6574
6575#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
6576#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
6577#define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
6578#define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
6579#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
6580#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
6581#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
6582#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
6583#define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
6584#define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
6585#define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
6586#define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
6587
6596#define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))
6597#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))
6598#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))
6599#define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))
6600#define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
6601#define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
6602#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))
6603#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))
6604#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))
6605#define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))
6606#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))
6607
6608
6609#define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))
6610#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))
6611#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))
6612#define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))
6613#define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))
6614#define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))
6615#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))
6616#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))
6617#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))
6618#define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))
6619#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))
6620
6621
6622
6630#define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
6631#define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
6632#define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))
6633#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))
6634#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))
6635#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))
6636#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))
6637#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
6638#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))
6639#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
6640
6641#define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))
6642#define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))
6643#define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))
6644#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))
6645#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))
6646#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))
6647#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))
6648#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))
6649#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))
6650#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))
6651
6659#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
6660#if defined(CRYP)
6661#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
6662#endif /* CRYP */
6663#if defined(HASH)
6664#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
6665#endif /* HASH */
6666#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
6667#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))
6668#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))
6669#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))
6670#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))
6671
6672#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))
6673#if defined(CRYP)
6674#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))
6675#endif /* CRYP */
6676#if defined(HASH)
6677#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))
6678#endif /* HASH */
6679#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))
6680#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))
6681#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))
6682#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))
6683#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))
6684
6692#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)
6693#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)
6694#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)
6695#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)
6696#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)
6697#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)
6698#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)
6699#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)
6700#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)
6701#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)
6702#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)
6703#define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)
6704#define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)
6705#define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)
6706#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)
6707#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN))
6708
6709#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)
6710#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)
6711#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)
6712#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)
6713#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)
6714#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)
6715#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)
6716#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)
6717#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)
6718#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)
6719#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)
6720#define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)
6721#define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)
6722#define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)
6723#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)
6724#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))
6725
6733#define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)
6734#define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)
6735#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)
6736
6737#define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)
6738#define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)
6739#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)
6740
6748#define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)
6749#define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)
6750#define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)
6751#define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)
6752#define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)
6753#define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)
6754#define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)
6755#define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)
6756#define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)
6757#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)
6758#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)
6759#define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)
6760#define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)
6761#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)
6762#define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)
6763#define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)
6764#define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)
6765#define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)
6766#define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)
6767#define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)
6768#define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)
6769#define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)
6770#define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)
6771#define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)
6772#define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)
6773#define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)
6774#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)
6775#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)
6776#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)
6777#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)
6778
6779
6780#define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)
6781#define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)
6782#define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)
6783#define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)
6784#define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)
6785#define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)
6786#define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)
6787#define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)
6788#define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)
6789#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)
6790#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)
6791#define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)
6792#define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)
6793#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)
6794#define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)
6795#define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)
6796#define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)
6797#define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)
6798#define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)
6799#define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)
6800#define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)
6801#define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)
6802#define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)
6803#define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)
6804#define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)
6805#define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)
6806#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)
6807#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)
6808#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)
6809#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)
6810
6818#define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)
6819#define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)
6820#define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)
6821#define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)
6822#define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)
6823#define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)
6824#define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)
6825#define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)
6826#define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)
6827#define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)
6828#define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)
6829#define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)
6830#define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)
6831#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)
6832#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)
6833
6834#define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)
6835#define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)
6836#define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)
6837#define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)
6838#define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)
6839#define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)
6840#define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)
6841#define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)
6842#define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)
6843#define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)
6844#define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)
6845#define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)
6846#define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)
6847#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)
6848#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)
6849
6857#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)
6858#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)
6859#define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)
6860#define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)
6861#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)
6862#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)
6863#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)
6864#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)
6865#define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)
6866#define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)
6867#define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)
6868#define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)
6869
6870#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)
6871#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)
6872#define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)
6873#define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)
6874#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)
6875#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)
6876#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)
6877#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)
6878#define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)
6879#define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)
6880#define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)
6881#define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)
6882
6883#endif /*DUAL_CORE*/
6884
6885#if defined(DUAL_CORE)
6889#else
6893#endif /*DUAL_CORE*/
6894
6895#if defined(RCC_D3AMR_BDMAAMEN)
6896#define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)
6897#endif
6898#if defined(RCC_D3AMR_LPUART1AMEN)
6899#define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)
6900#endif
6901#if defined(RCC_D3AMR_SPI6AMEN)
6902#define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)
6903#endif
6904#if defined(RCC_D3AMR_I2C4AMEN)
6905#define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)
6906#endif
6907#if defined(RCC_D3AMR_LPTIM2AMEN)
6908#define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)
6909#endif
6910#if defined(RCC_D3AMR_LPTIM3AMEN)
6911#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)
6912#endif
6913#if defined(LPTIM4)
6914#define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)
6915#endif
6916#if defined(LPTIM5)
6917#define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)
6918#endif
6919#if defined(RCC_D3AMR_COMP12AMEN)
6920#define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)
6921#endif
6922#if defined(RCC_D3AMR_VREFAMEN)
6923#define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)
6924#endif
6925#if defined(RCC_D3AMR_RTCAMEN)
6926#define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)
6927#endif
6928#if defined(RCC_D3AMR_CRCAMEN)
6929#define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)
6930#endif
6931#if defined(SAI4)
6932#define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)
6933#endif
6934#if defined(ADC3)
6935#define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)
6936#endif
6937#if defined(RCC_D3AMR_DTSAMEN)
6938#define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_DTSAMEN)
6939#endif
6940#if defined(RCC_D3AMR_BKPRAMAMEN)
6941#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)
6942#endif
6943#if defined(RCC_D3AMR_SRAM4AMEN)
6944#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)
6945#endif
6946
6947#if defined(BDMA2)
6948#define __HAL_RCC_BDMA2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)
6949#endif
6950#if defined(RCC_SRDAMR_GPIOAMEN)
6951#define __HAL_RCC_GPIO_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)
6952#endif
6953#if defined(RCC_SRDAMR_LPUART1AMEN)
6954#define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)
6955#endif
6956#if defined(RCC_SRDAMR_SPI6AMEN)
6957#define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)
6958#endif
6959#if defined(RCC_SRDAMR_I2C4AMEN)
6960#define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)
6961#endif
6962#if defined(RCC_SRDAMR_LPTIM2AMEN)
6963#define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)
6964#endif
6965#if defined(RCC_SRDAMR_LPTIM3AMEN)
6966#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)
6967#endif
6968#if defined(DAC2)
6969#define __HAL_RCC_DAC2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)
6970#endif
6971#if defined(RCC_SRDAMR_COMP12AMEN)
6972#define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)
6973#endif
6974#if defined(RCC_SRDAMR_VREFAMEN)
6975#define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)
6976#endif
6977#if defined(RCC_SRDAMR_RTCAMEN)
6978#define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)
6979#endif
6980#if defined(RCC_SRDAMR_DTSAMEN)
6981#define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)
6982#endif
6983#if defined(DFSDM2_BASE)
6984#define __HAL_RCC_DFSDM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)
6985#endif
6986#if defined(RCC_SRDAMR_BKPRAMAMEN)
6987#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)
6988#endif
6989#if defined(RCC_SRDAMR_SRDSRAMAMEN)
6990#define __HAL_RCC_SRDSRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)
6991#endif
6992
6993#if defined(RCC_D3AMR_BDMAAMEN)
6994#define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)
6995#endif
6996#if defined(RCC_D3AMR_LPUART1AMEN)
6997#define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)
6998#endif
6999#if defined(RCC_D3AMR_SPI6AMEN)
7000#define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)
7001#endif
7002#if defined(RCC_D3AMR_I2C4AMEN)
7003#define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)
7004#endif
7005#if defined(RCC_D3AMR_LPTIM2AMEN)
7006#define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)
7007#endif
7008#if defined(RCC_D3AMR_LPTIM3AMEN)
7009#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)
7010#endif
7011#if defined(LPTIM4)
7012#define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)
7013#endif
7014#if defined(LPTIM5)
7015#define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)
7016#endif
7017#if defined(RCC_D3AMR_COMP12AMEN)
7018#define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)
7019#endif
7020#if defined(RCC_D3AMR_VREFAMEN)
7021#define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)
7022#endif
7023#if defined(RCC_D3AMR_RTCAMEN)
7024#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN)
7025#endif
7026#if defined(RCC_D3AMR_CRCAMEN)
7027#define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN)
7028#endif
7029#if defined(SAI4)
7030#define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN)
7031#endif
7032#if defined(ADC3)
7033#define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN)
7034#endif
7035#if defined(RCC_D3AMR_DTSAMEN)
7036#define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_DTSAMEN)
7037#endif
7038#if defined(RCC_D3AMR_BKPRAMAMEN)
7039#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)
7040#endif
7041#if defined(RCC_D3AMR_SRAM4AMEN)
7042#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)
7043#endif
7044
7045#if defined(BDMA2)
7046#define __HAL_RCC_BDMA2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)
7047#endif
7048#if defined(RCC_SRDAMR_GPIOAMEN)
7049#define __HAL_RCC_GPIO_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)
7050#endif
7051#if defined(RCC_SRDAMR_LPUART1AMEN)
7052#define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)
7053#endif
7054#if defined(RCC_SRDAMR_SPI6AMEN)
7055#define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)
7056#endif
7057#if defined(RCC_SRDAMR_I2C4AMEN)
7058#define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)
7059#endif
7060#if defined(RCC_SRDAMR_LPTIM2AMEN)
7061#define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)
7062#endif
7063#if defined(RCC_SRDAMR_LPTIM3AMEN)
7064#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)
7065#endif
7066#if defined(RCC_SRDAMR_DAC2AMEN)
7067#define __HAL_RCC_DAC2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)
7068#endif
7069#if defined(RCC_SRDAMR_COMP12AMEN)
7070#define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)
7071#endif
7072#if defined(RCC_SRDAMR_VREFAMEN)
7073#define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)
7074#endif
7075#if defined(RCC_SRDAMR_RTCAMEN)
7076#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)
7077#endif
7078#if defined(RCC_SRDAMR_DTSAMEN)
7079#define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)
7080#endif
7081#if defined(DFSDM2_BASE)
7082#define __HAL_RCC_DFSDM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)
7083#endif
7084#if defined(RCC_SRDAMR_BKPRAMAMEN)
7085#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)
7086#endif
7087#if defined(RCC_SRDAMR_SRDSRAMAMEN)
7088#define __HAL_RCC_SRDSRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)
7089#endif
7090
7091
7092#if defined(RCC_CKGAENR_AXICKG)
7096#define __HAL_RCC_AXI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)
7097#define __HAL_RCC_AHB_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)
7098#define __HAL_RCC_CPU_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)
7099#define __HAL_RCC_SDMMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)
7100#define __HAL_RCC_MDMA_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)
7101#define __HAL_RCC_DMA2D_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)
7102#define __HAL_RCC_LTDC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)
7103#define __HAL_RCC_GFXMMUM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)
7104#define __HAL_RCC_AHB12_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)
7105#define __HAL_RCC_AHB34_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)
7106#define __HAL_RCC_FLIFT_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)
7107#define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)
7108#define __HAL_RCC_FMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)
7109#define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)
7110#define __HAL_RCC_AXIRAM1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)
7111#define __HAL_RCC_AXIRAM2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)
7112#define __HAL_RCC_AXIRAM3_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)
7113#define __HAL_RCC_GFXMMUS_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)
7114#define __HAL_RCC_ECCRAM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)
7115#define __HAL_RCC_EXTI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)
7116#define __HAL_RCC_JTAG_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)
7117
7118
7119#define __HAL_RCC_AXI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)
7120#define __HAL_RCC_AHB_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)
7121#define __HAL_RCC_CPU_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)
7122#define __HAL_RCC_SDMMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)
7123#define __HAL_RCC_MDMA_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)
7124#define __HAL_RCC_DMA2D_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)
7125#define __HAL_RCC_LTDC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)
7126#define __HAL_RCC_GFXMMUM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)
7127#define __HAL_RCC_AHB12_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)
7128#define __HAL_RCC_AHB34_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)
7129#define __HAL_RCC_FLIFT_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)
7130#define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)
7131#define __HAL_RCC_FMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)
7132#define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)
7133#define __HAL_RCC_AXIRAM1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)
7134#define __HAL_RCC_AXIRAM2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)
7135#define __HAL_RCC_AXIRAM3_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)
7136#define __HAL_RCC_GFXMMUS_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)
7137#define __HAL_RCC_ECCRAM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)
7138#define __HAL_RCC_EXTI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)
7139#define __HAL_RCC_JTAG_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)
7140
7141#endif /* RCC_CKGAENR_AXICKG */
7142
7143
7144
7145
7165#define __HAL_RCC_HSI_CONFIG(__STATE__) \
7166 MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))
7167
7168
7177#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
7178
7194#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
7195#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
7196
7197
7204#if defined(RCC_VER_X)
7205#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
7206 do { \
7207 if(HAL_GetREVID() <= REV_ID_Y) \
7208 { \
7209 if((__HSICalibrationValue__) == RCC_HSICALIBRATION_DEFAULT) \
7210 { \
7211 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, ((uint32_t)0x20) << HAL_RCC_REV_Y_HSITRIM_Pos); \
7212 } \
7213 else \
7214 { \
7215 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos); \
7216 } \
7217 } \
7218 else \
7219 { \
7220 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); \
7221 } \
7222 } while(0)
7223
7224#else
7225#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
7226 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);
7227#endif /*RCC_VER_X*/
7237#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
7238#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
7239
7240
7248#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON);
7249
7250#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
7251
7268#define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)
7269#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)
7270
7277#if defined(RCC_VER_X)
7278#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \
7279 do { \
7280 if(HAL_GetREVID() <= REV_ID_Y) \
7281 { \
7282 if((__CSICalibrationValue__) == RCC_CSICALIBRATION_DEFAULT) \
7283 { \
7284 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, ((uint32_t)0x10) << HAL_RCC_REV_Y_CSITRIM_Pos); \
7285 } \
7286 else \
7287 { \
7288 MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \
7289 } \
7290 } \
7291 else \
7292 { \
7293 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \
7294 } \
7295 } while(0)
7296
7297#else
7298#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \
7299 do { \
7300 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \
7301 } while(0)
7302
7303#endif /*RCC_VER_X*/
7313#define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)
7314#define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)
7315
7316
7325#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
7326#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
7327
7350#if defined(RCC_CR_HSEEXT)
7351#define __HAL_RCC_HSE_CONFIG(__STATE__) \
7352 do { \
7353 if ((__STATE__) == RCC_HSE_ON) \
7354 { \
7355 SET_BIT(RCC->CR, RCC_CR_HSEON); \
7356 } \
7357 else if ((__STATE__) == RCC_HSE_OFF) \
7358 { \
7359 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
7360 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \
7361 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
7362 } \
7363 else if ((__STATE__) == RCC_HSE_BYPASS) \
7364 { \
7365 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
7366 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \
7367 SET_BIT(RCC->CR, RCC_CR_HSEON); \
7368 } \
7369 else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \
7370 { \
7371 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
7372 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \
7373 SET_BIT(RCC->CR, RCC_CR_HSEON); \
7374 } \
7375 else \
7376 { \
7377 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
7378 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
7379 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \
7380 } \
7381 } while(0)
7382#else
7383#define __HAL_RCC_HSE_CONFIG(__STATE__) \
7384 do { \
7385 if ((__STATE__) == RCC_HSE_ON) \
7386 { \
7387 SET_BIT(RCC->CR, RCC_CR_HSEON); \
7388 } \
7389 else if ((__STATE__) == RCC_HSE_OFF) \
7390 { \
7391 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
7392 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
7393 } \
7394 else if ((__STATE__) == RCC_HSE_BYPASS) \
7395 { \
7396 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
7397 SET_BIT(RCC->CR, RCC_CR_HSEON); \
7398 } \
7399 else \
7400 { \
7401 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
7402 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
7403 } \
7404 } while(0)
7405#endif /* RCC_CR_HSEEXT */
7406
7436#if defined(RCC_BDCR_LSEEXT)
7437#define __HAL_RCC_LSE_CONFIG(__STATE__) \
7438 do { \
7439 if((__STATE__) == RCC_LSE_ON) \
7440 { \
7441 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7442 } \
7443 else if((__STATE__) == RCC_LSE_OFF) \
7444 { \
7445 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7446 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
7447 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7448 } \
7449 else if((__STATE__) == RCC_LSE_BYPASS) \
7450 { \
7451 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7452 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
7453 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7454 } \
7455 else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \
7456 { \
7457 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7458 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
7459 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7460 } \
7461 else \
7462 { \
7463 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7464 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7465 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \
7466 } \
7467 } while(0)
7468#else
7469
7470#define __HAL_RCC_LSE_CONFIG(__STATE__) \
7471 do { \
7472 if((__STATE__) == RCC_LSE_ON) \
7473 { \
7474 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7475 } \
7476 else if((__STATE__) == RCC_LSE_OFF) \
7477 { \
7478 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7479 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7480 } \
7481 else if((__STATE__) == RCC_LSE_BYPASS) \
7482 { \
7483 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7484 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7485 } \
7486 else \
7487 { \
7488 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
7489 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
7490 } \
7491 } while(0)
7492
7493#endif /* RCC_BDCR_LSEEXT */
7501#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
7502#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
7503
7525#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
7526 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
7527
7528#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
7529 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
7530 } while (0)
7531
7532#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
7533
7534
7540#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
7541#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
7542
7550#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
7551#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)
7552
7570#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
7571
7572#define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
7573
7574
7580#define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
7581
7582#define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
7583
7584
7626#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \
7627 do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); \
7628 WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
7629 ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
7630 } while(0)
7631
7632
7642#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
7643
7644
7661#define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
7662
7663
7673#define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \
7674 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
7675
7676
7687#define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \
7688 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
7689
7690
7691
7700#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
7701
7702
7712#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
7713
7722#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
7723
7741#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
7742 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
7743
7757#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
7758 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));
7759
7779#if defined(RCC_VER_X)
7780#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
7781 do{ \
7782 if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH))) \
7783 { \
7784 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk); \
7785 } \
7786 else \
7787 { \
7788 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); \
7789 } \
7790 } while(0)
7791#else
7792#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
7793 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
7794#endif /*RCC_VER_X*/
7803#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \
7804 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
7805
7814#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \
7815 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
7816
7836#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
7837
7852#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
7853
7869#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
7870
7887#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
7888
7891#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)
7892
7893#if defined(DUAL_CORE)
7894#define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF)
7895
7896#define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF)
7897#endif /*DUAL_CORE*/
7898
7899#if defined(DUAL_CORE)
7933#define RCC_FLAG_MASK ((uint8_t)0x1F)
7934#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
7935((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
7936
7937#define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
7938((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
7939
7940#define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
7941((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
7942
7943#else
7944
7979#define RCC_FLAG_MASK ((uint8_t)0x1F)
7980#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
7981((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
7982#endif /*DUAL_CORE*/
7983
7988#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)
7989
7994/* Include RCC HAL Extension module */
7995#include "stm32h7xx_hal_rcc_ex.h"
7996
7997/* Exported functions --------------------------------------------------------*/
8005/* Initialization and de-initialization functions ******************************/
8006HAL_StatusTypeDef HAL_RCC_DeInit(void);
8007HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
8008HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
8009
8017/* Peripheral Control functions ************************************************/
8018void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
8019void HAL_RCC_EnableCSS(void);
8020void HAL_RCC_DisableCSS(void);
8021uint32_t HAL_RCC_GetSysClockFreq(void);
8022uint32_t HAL_RCC_GetHCLKFreq(void);
8023uint32_t HAL_RCC_GetPCLK1Freq(void);
8024uint32_t HAL_RCC_GetPCLK2Freq(void);
8025void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
8026void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
8027/* CSS NMI IRQ handler */
8028void HAL_RCC_NMI_IRQHandler(void);
8029/* User Callbacks in non blocking mode (IT mode) */
8030void HAL_RCC_CSSCallback(void);
8031
8040/* Private types -------------------------------------------------------------*/
8041/* Private variables ---------------------------------------------------------*/
8042/* Private constants ---------------------------------------------------------*/
8048#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
8049#define HSI_TIMEOUT_VALUE (2U) /* 2 ms */
8050#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms */
8051#define CSI_TIMEOUT_VALUE (2U) /* 2 ms */
8052#define LSI_TIMEOUT_VALUE (2U) /* 2 ms */
8053#define PLL_TIMEOUT_VALUE (2U) /* 2 ms */
8054#define PLL_FRAC_TIMEOUT_VALUE (1U) /* PLL Fractional part waiting time before new latch enable : 1 ms */
8055#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
8056#define RCC_DBP_TIMEOUT_VALUE (100U)
8057#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
8058
8063/* Private macros ------------------------------------------------------------*/
8073#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
8074 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
8075 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
8076 (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
8077 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
8078 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
8079 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
8080
8081#if defined(RCC_CR_HSEEXT)
8082#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
8083 ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL))
8084#else
8085#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
8086 ((HSE) == RCC_HSE_BYPASS))
8087#endif /* RCC_CR_HSEEXT */
8088
8089#if defined(RCC_BDCR_LSEEXT)
8090#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
8091 ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL))
8092#else
8093#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
8094 ((LSE) == RCC_LSE_BYPASS))
8095#endif /* RCC_BDCR_LSEEXT */
8096
8097#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \
8098 ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \
8099 ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))
8100
8101#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
8102
8103#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
8104
8105#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
8106
8107#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
8108 ((PLL) == RCC_PLL_ON))
8109
8110#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || \
8111 ((SOURCE) == RCC_PLLSOURCE_HSI) || \
8112 ((SOURCE) == RCC_PLLSOURCE_NONE) || \
8113 ((SOURCE) == RCC_PLLSOURCE_HSE))
8114
8115#define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1VCIRANGE_0) || \
8116 ((VALUE) == RCC_PLL1VCIRANGE_1) || \
8117 ((VALUE) == RCC_PLL1VCIRANGE_2) || \
8118 ((VALUE) == RCC_PLL1VCIRANGE_3))
8119
8120#define IS_RCC_PLLVCO_VALUE(VALUE) (((VALUE) == RCC_PLL1VCOWIDE) || ((VALUE) == RCC_PLL1VCOMEDIUM))
8121
8122#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U)
8123
8124#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
8125#if !defined(RCC_VER_2_0)
8126#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
8127#else
8128#define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U))
8129#endif /* !RCC_VER_2_0 */
8130#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
8131#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
8132#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
8133
8134#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
8135 ((VALUE) == RCC_PLL1_DIVQ) || \
8136 ((VALUE) == RCC_PLL1_DIVR))
8137
8138#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))
8139
8140#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \
8141 ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
8142 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
8143 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
8144
8145#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \
8146 ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \
8147 ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \
8148 ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \
8149 ((SYSCLK) == RCC_SYSCLK_DIV512))
8150
8151
8152#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \
8153 ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \
8154 ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \
8155 ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \
8156 ((HCLK) == RCC_HCLK_DIV512))
8157
8158#define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \
8159 ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \
8160 ((CDPCLK1) == RCC_APB3_DIV16))
8161
8162#define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */
8163
8164#define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \
8165 ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \
8166 ((PCLK1) == RCC_APB1_DIV16))
8167
8168#define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \
8169 ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \
8170 ((PCLK2) == RCC_APB2_DIV16))
8171
8172#define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \
8173 ((SRDPCLK1) == RCC_APB4_DIV4) || ((SRDPCLK1) == RCC_APB4_DIV8) || \
8174 ((SRDPCLK1) == RCC_APB4_DIV16))
8175
8176#define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/
8177
8178#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
8179 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
8180 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
8181 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
8182 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
8183 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
8184 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
8185 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
8186 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
8187 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
8188 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
8189 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
8190 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
8191 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
8192 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
8193 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \
8194 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \
8195 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \
8196 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \
8197 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \
8198 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \
8199 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \
8200 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \
8201 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \
8202 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \
8203 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \
8204 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \
8205 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \
8206 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \
8207 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \
8208 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \
8209 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))
8210
8211#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
8212
8213#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
8214 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \
8215 ((SOURCE) == RCC_MCO1SOURCE_HSI48))
8216
8217#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \
8218 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \
8219 ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))
8220
8221#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
8222 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
8223 ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \
8224 ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \
8225 ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \
8226 ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \
8227 ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \
8228 ((DIV) == RCC_MCODIV_15))
8229
8230#if defined(DUAL_CORE)
8231#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \
8232 ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
8233 ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \
8234 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \
8235 ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
8236 ((FLAG) == RCC_FLAG_LSIRDY) || \
8237 ((FLAG) == RCC_FLAG_C1RST) || ((FLAG) == RCC_FLAG_C2RST) || \
8238 ((FLAG) == RCC_FLAG_SFTR2ST) || ((FLAG) == RCC_FLAG_WWDG2RST)|| \
8239 ((FLAG) == RCC_FLAG_IWDG2RST) || ((FLAG) == RCC_FLAG_D1RST) || \
8240 ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \
8241 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
8242 ((FLAG) == RCC_FLAG_SFTR1ST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
8243 ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
8244 ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV))
8245
8246#else
8247
8248#if defined(RCC_CR_D2CKRDY)
8249#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \
8250 ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
8251 ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \
8252 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \
8253 ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
8254 ((FLAG) == RCC_FLAG_LSIRDY) || \
8255 ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || \
8256 ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \
8257 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
8258 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
8259 ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
8260 ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV ))
8261#else
8262#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \
8263 ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
8264 ((FLAG) == RCC_FLAG_CPUCKRDY) || ((FLAG) == RCC_FLAG_CDCKRDY) || \
8265 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \
8266 ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
8267 ((FLAG) == RCC_FLAG_LSIRDY) || \
8268 ((FLAG) == RCC_FLAG_CDRST) || ((FLAG) == RCC_FLAG_BORRST) || \
8269 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
8270 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \
8271 ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \
8272 ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV ))
8273#endif /* RCC_CR_D2CKRDY */
8274
8275#endif /*DUAL_CORE*/
8276
8277#define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)
8278#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)
8279
8280#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \
8281 ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))
8282
8283#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \
8284 ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))
8300#ifdef __cplusplus
8301}
8302#endif
8303
8304#endif /* STM32H7xx_HAL_RCC_H */
8305
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
stm32h7xx_hal_rcc_ex.h
Header file of RCC HAL Extension module.
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition: stm32h7xx_hal_rcc.h:124
RCC_ClkInitTypeDef::APB1CLKDivider
uint32_t APB1CLKDivider
Definition: stm32h7xx_hal_rcc.h:140
RCC_ClkInitTypeDef::APB4CLKDivider
uint32_t APB4CLKDivider
Definition: stm32h7xx_hal_rcc.h:144
RCC_ClkInitTypeDef::SYSCLKSource
uint32_t SYSCLKSource
Definition: stm32h7xx_hal_rcc.h:128
RCC_ClkInitTypeDef::ClockType
uint32_t ClockType
Definition: stm32h7xx_hal_rcc.h:125
RCC_ClkInitTypeDef::SYSCLKDivider
uint32_t SYSCLKDivider
Definition: stm32h7xx_hal_rcc.h:131
RCC_ClkInitTypeDef::APB2CLKDivider
uint32_t APB2CLKDivider
Definition: stm32h7xx_hal_rcc.h:142
RCC_ClkInitTypeDef::APB3CLKDivider
uint32_t APB3CLKDivider
Definition: stm32h7xx_hal_rcc.h:137
RCC_ClkInitTypeDef::AHBCLKDivider
uint32_t AHBCLKDivider
Definition: stm32h7xx_hal_rcc.h:134
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition.
Definition: stm32h7xx_hal_rcc.h:86
RCC_OscInitTypeDef::HSIState
uint32_t HSIState
Definition: stm32h7xx_hal_rcc.h:96
RCC_OscInitTypeDef::LSEState
uint32_t LSEState
Definition: stm32h7xx_hal_rcc.h:93
RCC_OscInitTypeDef::HSEState
uint32_t HSEState
Definition: stm32h7xx_hal_rcc.h:90
RCC_OscInitTypeDef::HSI48State
uint32_t HSI48State
Definition: stm32h7xx_hal_rcc.h:106
RCC_OscInitTypeDef::LSIState
uint32_t LSIState
Definition: stm32h7xx_hal_rcc.h:103
RCC_OscInitTypeDef::HSICalibrationValue
uint32_t HSICalibrationValue
Definition: stm32h7xx_hal_rcc.h:99
RCC_OscInitTypeDef::CSIState
uint32_t CSIState
Definition: stm32h7xx_hal_rcc.h:109
RCC_OscInitTypeDef::CSICalibrationValue
uint32_t CSICalibrationValue
Definition: stm32h7xx_hal_rcc.h:112
RCC_OscInitTypeDef::PLL
RCC_PLLInitTypeDef PLL
Definition: stm32h7xx_hal_rcc.h:116
RCC_OscInitTypeDef::OscillatorType
uint32_t OscillatorType
Definition: stm32h7xx_hal_rcc.h:87
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition: stm32h7xx_hal_rcc.h:48
RCC_PLLInitTypeDef::PLLFRACN
uint32_t PLLFRACN
Definition: stm32h7xx_hal_rcc.h:77
RCC_PLLInitTypeDef::PLLN
uint32_t PLLN
Definition: stm32h7xx_hal_rcc.h:58
RCC_PLLInitTypeDef::PLLQ
uint32_t PLLQ
Definition: stm32h7xx_hal_rcc.h:67
RCC_PLLInitTypeDef::PLLVCOSEL
uint32_t PLLVCOSEL
Definition: stm32h7xx_hal_rcc.h:74
RCC_PLLInitTypeDef::PLLR
uint32_t PLLR
Definition: stm32h7xx_hal_rcc.h:70
RCC_PLLInitTypeDef::PLLP
uint32_t PLLP
Definition: stm32h7xx_hal_rcc.h:63
RCC_PLLInitTypeDef::PLLState
uint32_t PLLState
Definition: stm32h7xx_hal_rcc.h:49
RCC_PLLInitTypeDef::PLLSource
uint32_t PLLSource
Definition: stm32h7xx_hal_rcc.h:52
RCC_PLLInitTypeDef::PLLRGE
uint32_t PLLRGE
Definition: stm32h7xx_hal_rcc.h:72
RCC_PLLInitTypeDef::PLLM
uint32_t PLLM
Definition: stm32h7xx_hal_rcc.h:55
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